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050802
FEATURES
Incorporates industry standard DS1287 PC clock
plus enhanced features:
§ Y2K compliant
§ +3V or +5V operation
§ SMI recovery stack
§ 64-bit silicon serial number
§ Power-control circuitry supports system
power-on from date/time alarm or key
closure
§ 32kHz output on power-up
§ Crystal select bit allows RTC to operate with
6pF or 12.5pF crystal
§ 114 bytes user NV RAM
§ Auxiliary battery input
§ 2kB additional NV RAM
§ RAM clear input
§ Century register
§ Date alarm register
§ Compatible with existing BIOS for original
DS1287 functions
§ Available as chip (DS17285) or standalone
module with embedded battery and crystal
(DS17287)
§ Timekeeping algorithm includes leap-year
compensation valid up to 2100
§ Underwriters Laboratory (UL) recognized
TYPICAL OPERATING CIRCUIT
PIN ASSIGNMENT
PWR
1
2
3
4
5
6
7
8
9
10
11
12
23
DS17287 24-Pin
Encapsulated Package
NC
AD1
AD3
AD4
AD5
AD6
AD7
GND
VCC
SQW
VBAUX
RCLR
NC
IRQ
KS
RD
NC
WR
ALE
CS
24
22
21
20
19
18
17
16
15
14
13
NC
AD0
AD2
PWR
1
2
3
4
5
6
7
8
9
10
11
12
23
DS17285 24-Pin DIP
DS17285S 24-Pin SO
X2
AD1
AD3
AD4
AD5
AD6
AD7
GND
VCC
SQW
VBAUX
RCLR
VBAT
IRQ
KS
RD
GND
WR
ALE
CS
24
22
21
20
19
18
17
16
15
14
13
X1
AD0
AD2
IRQ
1
28
KS
VBAT
2
27
RD
RCLR
3
26
GND
VBAUX
4
25
WR
SQW
5
24
ALE
VCC
6
23
CS
VCC
7
22
GND
PWR
8
21
GND
X1
9
20
AD7
X2
10
19
AD6
NC
11
18
NC
ADO
12
17
AD5
AD1
13
16
AD4
AD2
14
15
AD3
DS17285E 28-Pin TSOP
DS17285/DS17287
3V/5V Real-Time Clock
www.maxim-ic.com
DS17285/DS17287
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ORDERING INFORMATION
PART #
DESCRIPTION
DS17285XX-X RTC
Chip
DS17287X-X RTC Module; 24-pin DIP
PIN DESCRIPTION
X1
- Crystal Input
X2
- Crystal Output
RCLR
- RAM Clear Input
AD0AD7 - Multiplexed Address/Data Bus
PWR
- Power-On Interrupt Output (Open Drain)
KS
- Kickstart Input
CS
- RTC Chip-Select Input
ALE
- RTC Address Strobe
WR
- RTC Write Data Strobe
RD
- RTC Read Data Strobe
IRQ
- Interrupt Request Output (Open Drain)
SQW
- Square-Wave Output
VCC
- +3V or +5V Main Supply
GND
- Ground
VBAT
- Battery + Supply
VBAUX
- Auxiliary Battery Supply
NC
- No Connect
DESCRIPTION
The DS17285/DS17287 are real-time clocks (RTCs) designed as successors to the industry standard
DS1285, DS1385, DS1485, DS1585, and DS1685 PC real-time clocks. These devices provide the
industry standard DS1285 clock function with either +3V or +5V operation. The DS17285 also
incorporates a number of enhanced features including a silicon serial number, power-on/off control
circuitry, 114 bytes of user NV SRAM plus 2kB of additional NV RAM, and 32.768kHz output for
sustaining power management activities.
3 +3V operating rang
5 +5V operating range
blank commercial temp range
N industrial
3 +3V operating range
5 +5V operating range
blank commercial temp range
N
industrial temp range
blank 24-pin DIP
E
28- pin TSOP
S
24- pin SO
DS17285/DS17287
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The DS17285/DS17287 power-control circuitry allows the system to be powered on by an external
stimulus such as a keyboard or by a time-and-date (wake-up) alarm. The
PWR
output pin is triggered by
one or either of these events, and is used to turn on an external power supply. The
PWR
pin is under
software control, so that when a task is complete, the system power can then be shut down.
The DS17285 is a clock/calendar chip with the features described above. An external crystal and battery
are the only components required to maintain time-of-day and memory status in the absence of power.
The DS17287 incorporates the DS17285 chip, a 32.768kHz crystal, and a lithium battery in a complete,
self-contained timekeeping module. The entire unit is fully tested at Dallas Semiconductor such that a
minimum of 10 years of timekeeping and data retention in the absence of V
CC
is guaranteed.
OPERATION
The block diagram in Figure 1 shows the pin connections with the major internal functions of the
DS17285/DS17287. The following paragraphs describe the function of each pin.
SIGNAL DESCRIPTIONS
GND, V
CC
DC power is provided to the device on these pins. V
CC
is the +3V or +5V input.
SQW Square-Wave Output. The SQW pin provides a 32kHz square-wave output, t
REC
, after a power-
up condition has been detected. This condition sets the following bits, enabling the 32kHz output;
DV1 = 1, and E32k = 1. A square wave is output on this pin if either SQWE = 1 or E32k = 1. If E32k = 1,
then 32kHz is output regardless of the other control bits. If E32k = 0, then the output frequency is
dependent on the control bits in register A. The SQW pin can output a signal from one of 13 taps
provided by the 15 internal divider stages of the RTC. The frequency of the SQW pin can be changed by
programming Register A, as shown in Table 2. The SQW signal can be turned on and off using the
SQWE bit in register B or the E32k bit in extended register 4Bh. A 32kHz SQW signal is output when the
enable 32kHz (E32k) bit in extended register 4Bh is a logic 1 and V
CC
is above V
PF
. A 32kHz square
wave is also available when V
CC
is less than V
PF
if E32k = 1, ABE = 1, and voltage is applied to the
V
BAUX
pin.
AD0 to AD7 Multiplexed Bidirectional Address/Data Bus. Multiplexed buses save pins because
address information time and data information time share the same signal paths. The addresses are
present during the first portion of the bus cycle and the same pins and signal paths are used for data in the
second portion of the cycle. Address/data multiplexing does not slow the access time of the DS17285
since the bus change from address to data occurs during the internal RAM access time. Addresses must
be valid prior to the latter portion of ALE, at which time the DS17285/DS17287 latches the address.
Valid write data must be present and held stable during the latter portion of the
WR
pulse. In a read cycle
the DS17285/DS17287 outputs 8 bits of data during the latter portion of the
RD
pulse. The read cycle is
terminated and the bus returns to a high impedance state as
RD
transitions high. The address/data bus
also serves as a bidirectional data path for the external extended RAM.
ALE RTC Address Strobe Input; Active High. A pulse on the address strobe pin serves to
demultiplex the bus. The falling edge of ALE causes the RTC address to be latched within the
DS17285/DS17287.
RD
RTC Read Input; Active Low.
RD
identifies the time period when the DS17285/DS17287 drives
the bus with RTC read data. The
RD
signal is an enable signal for the output buffers of the clock.
DS17285/DS17287
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WR
RTC Write Input; Active Low. The
WR
signal is an active low signal. The
WR
signal defines
the time period during which data is written to the addressed register.
CS
RTC Chip-Select Input; Active Low. The chip select signal must be asserted low during a bus
cycle for DS17285/DS17287 to be accessed.
CS
must be kept in the active state during
RD
and
WR
timing. Bus cycles that take place with ALE asserted but without asserting
CS
latches addresses.
However, no data transfer occurs.
IRQ
Interrupt Request Output; Open Drain, Active Low. The
IRQ
pin is an active low output of
the DS17285/DS17287 that can be tied to the interrupt input of a processor. The
IRQ
output remains low
as long as the status bit causing the interrupt is present and the corresponding interrupt-enable bit is set.
To clear the
IRQ
pin, the application software must clear all enabled flag bits contributing to
IRQ
's active
state.
When no interrupt conditions are present, the
IRQ
level is in the high-impedance state. Multiple
interrupting devices can be connected to an
IRQ
bus. The
IRQ
pin is an open-drain output and requires an
external pullup resistor. The voltage on the pullup supply should be no greater than V
CC
+ 0.2V.
PWR
Power-On Output; Open-Drain, Active Low. The
PWR
pin is intended for use as an on/off
control for the system power. With V
CC
voltage removed from the DS17285/DS17287,
PWR
can be
automatically activated from a kickstart input by the
KS
pin or from a wake-up interrupt. Once the
system is powered on, the state of
PWR
can be controlled by bits in the Dallas registers. The
PWR
pin
can be connected through a pullup resistor to a positive supply. For 5V operation, the voltage of the
pullup supply should be no greater than 5.7V. For 3V operation, the voltage on the pullup supply should
be no greater than 3.9V.
KS
Kickstart Input; Active Low. When V
CC
is removed from the DS17285/DS17287, the system can
be powered on in response to an active low transition on the
KS
pin, as might be generated from a key
closure. V
BAUX
must be present and auxiliary-battery-enable bit (ABE) must be set to 1 if the kickstart
function is used, and the
KS
pin must be pulled up to the V
BAUX
supply. While V
CC
is applied, the
KS
pin
can be used as an interrupt input.
RCLR
RAM Clear Input; Active Low. If enabled by software, taking
RCLR
low results in the
clearing of the 114 bytes of user RAM. When enabled,
RCLR
can be activated whether or not V
CC
is
present.
RCLR
has an internal pullup and should not be connected to an external pullup resistor.
V
BAUX
Auxiliary battery input required for kickstart and wake-up features. This input also supports
clock/calendar and user RAM if V
BAT
is at lower voltage or is not present. A standard +3V lithium cell or
other energy source can be used. For 3V operation, V
BAUX
must be held between +2.5V and +3.7V. For
5V operation, V
BAUX
must be held between +2.5V and +5.2V. If V
BAUX
is not going to be used it should
be grounded and the auxiliary-battery-enable bit bank 1, register 4BH, should = 0.
UL recognized to ensure against reverse charging current when used with a lithium battery. See
"Conditions of Acceptability" at
www.maxim-ic.com/TechSupport/QA/ntrl.htm
.
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