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Part Number GVT71128F36

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128K x 36/256K x 18
Synchronous-Pipelined Cache RAM
CY7C1328A/GVT71256F18
CY7C1348A/GVT71128F36
Cypress Semiconductor Corporation
·
3901 North First Street
·
San Jose
·
CA 95134
·
408-943-2600
Document #: 38-05152 Rev. *B
Revised January 19, 2003
327
Features
· Fast access times: 3.5, 3.8, and 4.0 ns
· Fast clock speed: 166, 150, 133, and 117 MHz
· Provide high performance 3-1-1-1 access rate
· Fast OE access times: 3.5 ns and 3.8 ns
· Optimal for performance (double cycle chip deselect,
depth expansion without wait state)
· 3.3V ­5% and +10% core power supply
· 2.5V or 3.3V I/O supply
· 5V tolerant inputs except I/Os
· Clamp diodes to V
SSQ
at all inputs and outputs
· Common data inputs and data outputs
· Byte Write Enable and Global Write control
· Three chip enables for depth expansion and address
pipeline
· Address, data and control registers
· Internally self-timed Write Cycle
· Burst control pins (interleaved or linear burst se-
quence)
· Automatic power-down for portable applications
· High-density, high-speed packages
Functional Description
The Cypress Synchronous Burst SRAM family employs
high-speed, low-power CMOS designs using advanced tri-
ple-layer polysilicon, double-layer metal technology. Each
memory cell consists of four transistors and two high-valued
resistors.
The CY7C1348A/GVT71128F36 and CY7C1328A/
GVT71256F18 SRAM integrate 262,144x18 and 131,072x36
SRAM cells with advanced synchronous peripheral circuitry
and a 2-bit counter for internal burst operation. All synchro-
nous inputs are gated by registers controlled by a posi-
tive-edge-triggered Clock Input (CLK). The synchronous in-
puts include all addresses, all data inputs, address-pipelining
Chip Enable (CE), depth-expansion Chip Enables (CE2 and
CE2), Burst Control inputs (ADSC, ADSP, and ADV), Write En-
ables (BW1, BW2, BW3, BW4, and BWE), and Global Write
(GW).
Asynchronous inputs include the Output Enable (OE) and
Burst Mode Control (MODE). The data outputs (Q), enabled
by OE, are also asynchronous.
Addresses and chip enables are registered with either Ad-
dress Status Processor (ADSP) or Address Status Controller
(ADSC) input pins. Subsequent burst addresses can be inter-
nally generated as controlled by the Burst Advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate self-timed WRITE cycle. WRITE cycles can be one
to four bytes wide as controlled by the write control inputs.
Individual byte write allows individual byte to be written. BW1
controls DQ1­DQ8 and DQP1. BW2 controls DQ9­DQ16 and
DQP2. BW3 controls DQ17­DQ24 and DQP3. BW4 controls
DQ25­DQ32 and DQP4. BW1, BW2, BW3, and BW4 can be
active only with BWE being LOW. GW being LOW causes all
bytes to be written. WRITE pass-through capability allows writ-
ten data available at the output for the immediately next READ
cycle. This device also incorporates pipelined enable circuit for
easy depth expansion without penalizing system performance.
The CY7C1348A/GVT71128F36/CY7C1328A/GVT71256F18
operates from a +3.3V core power supply and all outputs op-
erate on a +2.5V supply. All inputs and outputs are JEDEC
standard JESD8-5 compatible. The device is ideally suited for
486, Pentium®, 680x0, and PowerPCTM systems and for sys-
tems that benefit from a wide synchronous data bus.
Pentium is a registered trademark of Intel Corporation.
PowerPC is a trademark of International Business Machines, Incorporated.
Selection Guide
7C1328A-166
71256F18-3
7C1348A-166
71128F36-3
7C1328A-150
71256F18-4
7C1348A-150
71128F36-4
7C1328A-133
71256F18-5
7C1348A-133
71128F36-5
7C1328A-117
71256F18-6
7C1348A-117
71128F36-6
Maximum Access Time (ns)
3.5
3.8
4.0
4.0
Maximum Operating Current (mA)
425
400
375
350
Maximum CMOS Standby Current (mA)
10
10
10
10
CY7C1328A/GVT71256F18
CY7C1348A/GVT71128F36
Document #: 38-05152 Rev. *B
Page 2 of 13
Note:
1.
The Functional Block Diagram illustrates simplified device operation. See Truth Table, pin descriptions and timing diagrams for detailed information.
Functional Block Diagram--128Kx36
[1]
D
Q
D
Q
BW3#
BWE#
BW4#
CE#
CE2
CE2#
BYTE 3 WRITE
BYTE 4 WRITE
OUTPUT
REGISTER
OE#
by
t
e
3 w
r
i
t
e
ADSP#
ADSC#
Address
Register
Binary
Counter
& Logic
CLR
A16-A2
A1-A0
ADV#
MODE
128K
x 9 x 4
S
RAM Ar
r
a
y
Ou
tp
u
t
Bu
ffe
r
s
Input
Register
by
t
e
4 w
r
i
t
e
DQ1-DQ32,
DQP1,DQP2
DQp3,DQp4
D
Q
D
Q
D
Q
BW1#
BW2#
GW#
BYTE 1 WRITE
BYTE 2 WRITE
CLK
by
t
e
2 w
r
i
t
e
by
t
e
1 w
r
i
t
e
D
Q
D
Q
ENABLE
Power Down Logic
ZZ
Functional Block Diagram--256Kx18
[1]
D
Q
D
Q
WEH#
BWE#
WEL#
GW#
CE#
CE2
CE2#
UPPER BYTE
WRITE
LOWER BYTE
WRITE
OUTPUT
REGISTER
OE#
hi byte w
r
ite
ADSP#
ADSC#
Address
Register
Binary
Counter
& Logic
CLR
A17-A2
A1-A0
ADV#
MODE
256K
x 9 x 2
S
RAM Ar
r
a
y
O
u
tput B
u
ffers
Input
Register
lo byte w
r
ite
DQ1-
DQ16,
DQP1,
DQP2
D
Q
D
Q
D
Q
ENABLE
Power Down Logic
ZZ
CY7C1328A/GVT71256F18
CY7C1348A/GVT71128F36
Document #: 38-05152 Rev. *B
Page 3 of 13
Pin Configurations
100-Pin TQFP
Top View
A5
A4
A3
A2
A1
A0
NC
NC
V
SS
V
CC
NC
NC
A1
0
A1
1
A1
2
A1
3
A1
4
A1
5
A1
6
DQP2
DQ16
DQ15
V
CCQ
V
SSQ
DQ14
DQ13
DQ12
DQ11
V
SSQ
V
CCQ
DQ10
DQ9
V
SS
NC
V
CC
ZZ
DQ8
DQ7
V
CCQ
V
SSQ
DQ6
DQ5
DQ4
DQ3
V
SSQ
V
CCQ
DQ2
DQ1
DQP1
DQP3
DQ17
DQ18
V
CCQ
V
SSQ
DQ19
DQ20
DQ21
DQ22
V
SSQ
V
CCQ
DQ23
DQ24
V
CC
NC
V
SS
DQ25
DQ26
V
CCQ
V
SSQ
DQ27
DQ28
DQ29
DQ30
V
SSQ
V
CCQ
DQ31
DQ32
DQP4
A6
A7
CE
CE
2
BW
4
BW
3
BW
2
BW
1
CE
2
V
CC
V
SS
CL
K
GW
BW
E
OE
AD
SC
AD
SP
AD
V
A8
A9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
10
0
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
MO
D
E
CY7C1348A/GVT71128F36
(128K X 36)
NC
A10
NC
NC
V
CCQ
V
SSQ
NC
DQP1
DQ8
DQ7
V
SSQ
V
CCQ
DQ6
DQ5
V
SS
NC
V
CC
ZZ
DQ4
DQ3
V
CCQ
V
SSQ
DQ2
DQ1
NC
NC
V
SSQ
V
CCQ
NC
NC
NC
NC
NC
NC
V
CCQ
V
SSQ
NC
NC
DQ9
DQ10
V
SSQ
V
CCQ
DQ11
DQ12
V
CC
NC
V
SS
DQ13
DQ14
V
CCQ
V
SSQ
DQ15
DQ16
DQP2
NC
V
SSQ
V
CCQ
NC
NC
NC
A6
A7
CE
CE
2
NC
NC
WE
H
WE
L
CE
2
V
CC
V
SS
CL
K
GW
BW
E
OE
AD
SC
AD
SP
AD
V
A8
A9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
10
0
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
CY7C1328A/GVT71256F18
(256K x 18)
NC
A5
A4
A3
A2
A1
A0
NC
NC
V
SS
V
CC
NC
NC
A1
5
A1
4
A1
3
A1
2
A1
1
A1
6
A1
7
MO
D
E
CY7C1328A/GVT71256F18
CY7C1348A/GVT71128F36
Document #: 38-05152 Rev. *B
Page 4 of 13
Pin Descriptions
Name
Type
Description
A0
A1
A2­A17
(A17 for X18)
Input-
Synchronous
Addresses: These inputs are registered and must meet the set-up and hold times around the
rising edge of CLK. The burst counter generates internal addresses associated with A0 and
A1, during burst cycle and wait cycle.
BW1
BW2
BW3
BW4
Input-
Synchronous
Byte Write Enables: A byte write enable is LOW for a WRITE cycle and HIGH for a READ
cycle. BW1 controls DQ1­DQ8 and DQP1. BW2 controls DQ9­DQ16 and DQP2. BW3 con-
trols DQ17­DQ24 and DQP3. BW4 controls DQ25­DQ32 and DQP4. Data I/O are high im-
pedance if either of these inputs are LOW, conditioned by BWE being LOW. BW1 is equal to
WEL and BW2 is equal to WEH for X18 device.
BWE
Input-
Synchronous
Write Enable: This active LOW input gates byte write operations and must meet the set-up
and hold times around the rising edge of CLK.
GW
Input-
Synchronous
Global Write: This active LOW input allows a full 38-bit (18-bit for X18 device) WRITE to occur
independent of the BWE and BWn lines and must meet the set-up and hold times around the
rising edge of CLK.
CLK
Input-
Synchronous
Clock: This signal registers the addresses, data, chip enables, write control and burst control
inputs on its rising edge. All synchronous inputs must meet set-up and hold times around the
clock's rising edge.
CE
Input-
Synchronous
Chip Enable: This active LOW input is used to enable the device and to gate ADSP.
CE2
Input-
Synchronous
Chip Enable: This active LOW input is used to enable the device.
CE2
Input-
Synchronous
Chip Enable: This active HIGH input is used to enable the device.
OE
Input
Output Enable: This active LOW asynchronous input enables the data output drivers.
ADV
Input-
Synchronous
Address Advance: This active LOW input is used to control the internal burst counter. A HIGH
on this pin generates wait cycle (no address advance).
ADSP
Input-
Synchronous
Address Status Processor: This active LOW input, along with CE being LOW, causes a new
external address to be registered and a READ cycle is initiated using the new address.
ADSC
Input-
Synchronous
Address Status Controller: This active LOW input causes device to be deselected or selected
along with new external address to be registered. A READ or WRITE cycle is initiated depend-
ing upon write control inputs.
MODE
Input-
Static
Mode: This input selects the burst sequence. A LOW on this pin selects Linear Burst. A NC or
HIGH on this pin selects Interleaved Burst.
ZZ
Input-
Asynchronous
Snooze: This active HIGH input puts the device in low power consumption standby mode. For
normal operation, this input has to be either LOW or NC (No Connect).
DQ1­8
DQ9­16
DQ17­24
DQ25­32
Input/
Output
Data Inputs/Outputs: Byte one is DQ1­DQ8. Byte two is DQ9­DQ16. Byte three is
DQ17­DQ24. Byte four is DQ25­DQ32. Input data must meet set-up and hold times around
the rising edge of CLK. X18 only has two bytes (Byte one and Byte two).
DQP1­
DQP4
Input/
Output
Parity Inputs/Outputs: DQP1 is parity bit for DQ1­DQ8 and DQP2 is parity bit for DQ9­DQ16.
DQP3 is parity bit for DQ17­DQ24 and DQP4 is parity bit for DQ25­DQ32.
V
CC
Supply
Power Supply: +3.3V ­5% and +10%.
V
SS
Ground
Ground: GND.
V
CCQ
I/O Supply
Output Buffer Supply: +2.5V (from 2.375V to V
CC
).
V
SSQ
I/O Ground
Output Buffer Ground: GND.
NC
-
No Connect: These signals are not internally connected. User can connect them to V
CC
, V
SS
,
or any signal. They can be left unconnected as floating.
CY7C1328A/GVT71256F18
CY7C1348A/GVT71128F36
Document #: 38-05152 Rev. *B
Page 5 of 13
Notes:
2.
X = "Don't Care." H = logic HIGH. L = logic LOW.
WRITE = L means [BWE + BWa*BWb]*GW equals LOW. WRITE = H means [BWE + BWa*BWb]*GW equals HIGH.
3.
BWa enables write to DQa. BWb enables write to DQb.
4.
All inputs except OE must meet set-up and hold times around the rising edge (LOW to HIGH) of CLK.
5.
Suspending burst generates wait cycle.
6.
For a write operation following a read operation, OE must be HIGH before the input data required setup time plus High-Z time for OE and staying HIGH throughout
the input data hold time.
7.
This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
8.
ADSP LOW along with chip being selected always initiates a READ cycle at the L-H edge of CLK. A WRITE cycle can be performed by setting WRITE LOW for
the CLK L-H edge of the subsequent wait cycle. Refer to WRITE timing diagram for clarification.
Burst Address Table (MODE = NC/V
CC
)
First
Address
(external)
Second
Address
(internal)
Third
Address
(internal)
Fourth
Address
(internal)
A...A00
A...A01
A...A10
A...A11
A...A01
A...A00
A...A11
A...A10
A...A10
A...A11
A...A00
A...A01
A...A11
A...A10
A...A01
A...A00
Burst Address Table (MODE = GND)
First
Address
(external)
Second
Address
(internal)
Third
Address
(internal)
Fourth
Address
(internal)
A...A00
A...A01
A...A10
A...A11
A...A01
A...A10
A...A11
A...A00
A...A10
A...A11
A...A00
A...A01
A...A11
A...A00
A...A01
A...A10
Truth Table
[2, 3, 4, 5, 6, 7, 8]
Operation
Address
Used
CE
CE2
CE2
ADSP
ADSC
ADV
WRITE
OE
CLK
DQ
Deselected Cycle, Power Down
None
H
X
X
X
L
X
X
X
L-H
High-Z
Deselected Cycle, Power Down
None
L
X
L
L
X
X
X
X
L-H
High-Z
Deselected Cycle, Power Down
None
L
H
X
L
X
X
X
X
L-H
High-Z
Deselected Cycle, Power Down
None
L
X
L
H
L
X
X
X
L-H
High-Z
Deselected Cycle, Power Down
None
L
H
X
H
L
X
X
X
L-H
High-Z
READ Cycle, Begin Burst
External
L
L
H
L
X
X
X
L
L-H
Q
READ Cycle, Begin Burst
External
L
L
H
L
X
X
X
H
L-H
High-Z
WRITE Cycle, Begin Burst
External
L
L
H
H
L
X
L
X
L-H
D
READ Cycle, Begin Burst
External
L
L
H
H
L
X
H
L
L-H
Q
READ Cycle, Begin Burst
External
L
L
H
H
L
X
H
H
L-H
High-Z
READ Cycle, Continue Burst
Next
X
X
X
H
H
L
H
L
L-H
Q
READ Cycle, Continue Burst
Next
X
X
X
H
H
L
H
H
L-H
High-Z
READ Cycle, Continue Burst
Next
H
X
X
X
H
L
H
L
L-H
Q
READ Cycle, Continue Burst
Next
H
X
X
X
H
L
H
H
L-H
High-Z
WRITE Cycle, Continue Burst
Next
X
X
X
H
H
L
L
X
L-H
D
WRITE Cycle, Continue Burst
Next
H
X
X
X
H
L
L
X
L-H
D
READ Cycle, Suspend Burst
Current
X
X
X
H
H
H
H
L
L-H
Q
READ Cycle, Suspend Burst
Current
X
X
X
H
H
H
H
H
L-H
High-Z
READ Cycle, Suspend Burst
Current
H
X
X
X
H
H
H
L
L-H
Q
READ Cycle, Suspend Burst
Current
H
X
X
X
H
H
H
H
L-H
High-Z
WRITE Cycle, Suspend Burst
Current
X
X
X
H
H
H
L
X
L-H
D
WRITE Cycle, Suspend Burst
Current
H
X
X
X
H
H
L
X
L-H
D