CY7C63000A/CY7C63001A
CY7C63100A/CY7C63101A

FOR

Document #: 38-08026 Rev. **

Page 2 of 31

TABLE OF CONTENTS

1.0 FEATURES ...................................................................................................................................... 4

2.0 FUNCTIONAL OVERVIEW .............................................................................................................. 4

3.0 PIN DEFINITIONS ............................................................................................................................ 6

4.0 PIN DESCRIPTION .......................................................................................................................... 6

5.0 FUNCTIONAL DESCRIPTION ......................................................................................................... 7

5.1 Memory Organization ..................................................................................................................... 7

5.1.1 Program Memory Organization ............................................................................................................ 7
5.1.2 Security Fuse Bit ................................................................................................................................... 7
5.1.3 Data Memory Organization ................................................................................................................... 8

5.2 I/O Register Summary .................................................................................................................... 9
5.3 Reset ................................................................................................................................................ 9

5.3.1 Power-On Reset (POR) ........................................................................................................................ 10
5.3.2 Watch Dog Reset (WDR) ..................................................................................................................... 10
5.3.3 USB Bus Reset .................................................................................................................................... 10

5.4 Instant-on Feature (Suspend Mode) ........................................................................................... 10
5.5 On-Chip Timer ............................................................................................................................... 11
5.6 General Purpose I/O Ports ........................................................................................................... 12
5.7 XTALIN/XTALOUT ......................................................................................................................... 13
5.8 Interrupts ....................................................................................................................................... 14

5.8.1 Interrupt Latency ................................................................................................................................. 15
5.8.2 GPIO Interrupt ...................................................................................................................................... 15
5.8.3 USB Interrupt ....................................................................................................................................... 16
5.8.4 Timer Interrupt ..................................................................................................................................... 16
5.8.5 Wake-Up Interrupt ............................................................................................................................... 16

5.9 USB Engine ................................................................................................................................... 16

5.9.1 USB Enumeration Process ................................................................................................................. 17
5.9.2 Endpoint 0 ............................................................................................................................................ 17

5.9.2.1 Endpoint 0 Receive ...................................................................................................................................... 17
5.9.2.2 Endpoint 0 Transmit ..................................................................................................................................... 18

5.9.3 Endpoint 1 ............................................................................................................................................ 19

5.9.3.1 Endpoint 1 Transmit ..................................................................................................................................... 19

5.9.4 USB Status and Control ...................................................................................................................... 19

5.10 USB Physical Layer Characteristics ......................................................................................... 20

5.10.1 Low-Speed Driver Characteristics ................................................................................................... 20
5.10.2 Receiver Characteristics ................................................................................................................... 20

5.11 External USB Pull-Up Resistor .................................................................................................. 21
5.12 Instruction Set Summary ........................................................................................................... 21

6.0 ABSOLUTE MAXIMUM RATINGS ................................................................................................ 22

7.0 ELECTRICAL CHARACTERISTICS .............................................................................................. 23

8.0 SWITCHING CHARACTERISTICS ................................................................................................ 25

9.0 ORDERING INFORMATION .......................................................................................................... 27

10.0 PACKAGE DIAGRAMS ............................................................................................................... 28

CY7C63000A/CY7C63001A
CY7C63100A/CY7C63101A

FOR

Document #: 38-08026 Rev. **

Page 3 of 31

LIST OF FIGURES

Figure 5-1. Program Memory Space .................................................................................................... 7
Figure 5-2. Data Memory Space ........................................................................................................... 8
Figure 5-4. Watch Dog Reset (WDR) .................................................................................................. 10
Figure 5-3. Status and Control Register (SCR - Address 0xFF) ...................................................... 10
Figure 5-5. The Cext Register (Address 0x22) .................................................................................. 11
Figure 5-6. Timer Register (Address 0x23)........................................................................................ 11
Figure 5-7. Timer Block Diagram........................................................................................................ 11
Figure 5-8. Port 0 Data Register (Address 0x00) .............................................................................. 12
Figure 5-9. Port 1 Data Register (Address 0x01) .............................................................................. 12
Figure 5-10. Block Diagram of an I/O Line......................................................................................... 12
Figure 5-11. Port 0 Pull-up Register (Address 0x08) ........................................................................ 13
Figure 5-12. Port 1 Pull-up Register (Address 0x09) ........................................................................ 13
Figure 5-13. Port Isink Register for One GPIO Line.......................................................................... 13
Figure 5-14. Clock Oscillator On-chip Circuit ................................................................................... 14
Figure 5-16. Interrupt Controller Logic Block Diagram .................................................................... 14
Figure 5-15. Global Interrupt Enable Register (GIER - Address 0x20)............................................ 14
Figure 5-17. Port 0 Interrupt Enable Register (P0 IE - Address 0x04)............................................. 15
Figure 5-18. Port 1 Interrupt Enable Register (P1 IE - Address 0x05)............................................. 15
Figure 5-19. GPIO Interrupt Logic Block Diagram ............................................................................ 16
Figure 5-20. USB Device Address Register (USB DA - Address 0x12) ........................................... 17
Figure 5-21. USB Endpoint 0 RX Register (Address 0x14) .............................................................. 17
Figure 5-22. USB Endpoint 0 TX Configuration Register (Address 0x10) ...................................... 18
Figure 5-23. USB Endpoint 1 TX Configuration Register (Address 0x11) ...................................... 19
Figure 5-24. USB Status and Control Register (USB SCR - Address 0x13) ................................... 19
Figure 5-25. Low-speed Driver Signal Waveforms ........................................................................... 20
Figure 5-26. Differential Input Sensitivity Over Entire Common Mode Range............................... 20
Figure 5-27. Application Showing 7.5kW±1% Pull-Up Resistor....................................................... 21
Figure 5-28. Application Showing 1.5-kW±5% Pull-Up Resistor ..................................................... 21
Figure 8-1. Clock Timing ..................................................................................................................... 26
Figure 8-2. USB Data Signal Timing and Voltage Levels ................................................................. 26
Figure 8-3. Receiver Jitter Tolerance ................................................................................................. 26
Figure 8-4. Differential to EOP Transition Skew and EOP Width .................................................... 27
Figure 8-5. Differential Data Jitter ...................................................................................................... 27

LIST OF TABLES

Table 5-1. I/O Register Summary ......................................................................................................... 9
Table 5-2. Output Control Truth Table .............................................................................................. 13
Table 5-3. Interrupt Vector Assignments .......................................................................................... 15
Table 5-4. USB Engine Response to SETUP and OUT Transactions on Endpoint 0 .................... 18
Table 5-5. Instruction Set Map ........................................................................................................... 21

CY7C63000A/CY7C63001A
CY7C63100A/CY7C63101A

FOR

Document #: 38-08026 Rev. **

Page 4 of 31

1.0

Features

· Low-cost solution for low-speed USB peripherals such as mouse, joystick, and gamepad
· USB Specification Compliance

-- Conforms to USB 1.5 Mbps Specification, Version 1.1

-- Supports 1 device address and 2 endpoints (1 control endpoint and 1 data endpoint)

· 8-bit RISC microcontroller

-- Harvard architecture

-- 6-MHz external ceramic resonator

-- 12-MHz internal operation

-- USB optimized instruction set

· Internal memory

-- 128 bytes of RAM

-- 2 Kbytes of EPROM (CY7C63000A, CY7C63100A)

-- 4 Kbytes of EPROM (CY7C63001A, CY7C63101A)

· I/O ports

-- Integrated USB transceiver

-- Up to 16 Schmitt trigger I/O pins with internal pull-up

-- Up to 8 I/O pins with LED drive capability

-- Special purpose I/O mode supports optimization of photo transistor and LED in mouse application

-- Maskable Interrupts on all I/O pins

· 8-bit free-running timer
· Watch dog timer (WDT)
· Internal power-on reset (POR)
· Instant-On NowTM for Suspend and Periodic Wake-up Modes
· Improved output drivers to reduce EMI
· Operating voltage from 4.0V to 5.25 VDC
· Operating temperature from 0 to 70 degree Celsius
· Available in space saving and low cost 20-pin PDIP, 20-pin SOIC, 24-pin SOIC and 24-pin QSOP packages
· Industry standard programmer support

2.0

Functional Overview

The CY7C630/1XXA is a family of 8-bit RISC One Time Programmable (OTP) microcontrollers with a built-in 1.5-Mbps USB Serial
Interface Engine (SIE). The microcontroller features 35 instructions that are optimized for USB applications. In addition, the
microcontroller features 128 bytes of internal RAM and either 2 or 4 Kbytes of program memory space. The Cypress USB
Controller accepts a 6-MHz ceramic resonator as its clock source. This clock signal is doubled within the chip to provide a 12-
MHz clock for the microprocessor.

The microcontroller features two ports of up to sixteen general purpose I/Os (GPIOs). Each GPIO pin can be used to generate
an interrupt to the microcontroller. Additionally, all pins in Port 1 are equipped with programmable drivers strong enough to drive
LEDs. The GPIO ports feature low EMI emissions as a result of controlled rise and fall times and unique output driver circuits.
The Cypress microcontrollers have a range of GPIOs to fit various applications; the CY7C6300XA has twelve GPIOs and the
CY7C6310XA has sixteen GPIOs. Notice that each part has eight `low-current' ports (Port 0) with the remaining ports (Port 1)
being `high-current' ports.

The 12-GPIO CY7C6300XA is available in 20-pin PDIP (-PC) and 20-pin SOIC (-SC) packages. The 26-GPIO CY7C6310XA is
available in 24-pin SOIC (-SC) and 24-pin QSOP (-QC) packages.

Part Number CY7C63001A