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1
Selection Guide
7C198-15 7C198-20 7C198-25 7C198-35 7C198-45
Maximum Access Time (ns)
15
20
25
35
45
Maximum Operating Current (mA)
Commercial
150
Military
180
170
150
150
150
Maximum Standby Current (mA)
30
30
30
25
25
Shaded area contains preliminary information.
32K x 8 Static RAM
7c198: 10/25/89
Revision: February 29, 1996
CY7C198
12
I/O
0
31
Logic Block Diagram
Pin Configurations
Features
D
High speed
15 ns
D
CMOS for optimum speed/power
D
Low active power
990 mW
D
Low standby power
195 mW
D
Easy memory expansion with CE and
OE features
D
TTL compatible inputs and outputs
D
Automatic power down when
deselected
Functional Description
The CY7C198 is a high performance
CMOS static RAM organized as 32,768
words by 8 bits. Easy memory expansion is
provided by an active LOW chip enable
(CE) and active LOW output enable (OE)
and three state drivers. This device has an
automatic power down feature, reducing
the power consumption by 80% when de
selected. The CY7C198 is available in a
600 mil wide cerDIP and LCC package
and a 32 lead TSOP package.
An active LOW write enable signal (WE)
controls the writing/reading operation of
the memory. When CE and WE inputs
areboth LOW,dataontheeightdatainput/
output pins (I/O
0
through I/O
7
) is written
into the memory location addressed by the
address present on the address pins (A
0
through A
14
). Reading the device is ac
complished by selecting the device and en
abling the outputs, CE and OE active
LOW, while WE remains inactive or
HIGH. Under these conditions, the con
tents of the location addressed by the in
formation onaddresspinsispresentonthe
eight data input/output pins.
The input/output pins remain in a high im
pedance state unless the chip is selected,
outputs are enabled, and write enable
(WE) is HIGH.
A die coat is used to ensure alpha immunity.
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
COLUMN
DECODER
ROW
DECODER
SENSE
AMPS
INPUT BUFFER
POWER
DOWN
WE
OE
I/O
0
CE
I/O
1
I/O
2
I/O
3
4
5
6
7
8
9
10
3 2 1
30
13
14 15 16 17
26
25
24
23
22
21
11
A 7
V CC
A
6
A
5
A
4
A
3
A
2
A
1
A
0
CE
A
9
A
11
NC
A
10
I/O
7
I/O
6
I/O
4
GND
WE
Top View
LCC
1
2
3
4
5
6
7
8
9
10
11
14
15
16
20
19
18
17
21
24
23
22
Top View
CerDIP
12
13
25
28
27
26
GND
A
6
A
7
A
8
A
9
A
10
A
11
A
12
A
13
WE
V
CC
A
4
A
3
A
2
A
1
I/O
7
I/O
6
I/O
5
I/O
4
A
14
A
5
I/O
0
I/O
1
I/O
2
CE
OE
A
0
I/O
3
A
8
OE
A
12
A
14
I/O
3
I/O
2
I/O
1
1024 x 32 x 8
ARRAY
I/O
7
I/O
6
I/O
5
I/O
4
A
9
A
0
A
11
A
13
A
12
A
14
A
10
1819 20
27
28
29
32
NC
A 13
NC
I/O
5
NC
C198 2
C198 3
C198 1
Cypress Semiconductor Corporation
D
3901 North First Street
D
San Jose
D
CA 95134
D
408-943-2600
February 1988 - Revised February 1996
7c198: 10/25/89
Revision: February 29, 1996
CY7C198
2
1
2
3
4
5
6
7
8
9
10
11
14
19
20
24
23
22
21
25
28
27
26
Top View
TSOP
12
13
29
32
21
30
OE
A
1
A
2
A
3
A
4
WE
V
CC
NC
A
5
A
6
A
7
A
8
A
9
A
0
CE
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
NC
NC
GND
I/O
2
I/O
1
I/O
0
A
14
C198 4
Pin Configurations
(continued)
NC
16
17
18
15
A
10
A
11
A
13
A
12
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Temperature
-65
_
C to +150
_
C
. . . . . . . . . . . . . . . . . . .
Ambient Temperature with
Power Applied
-55
_
C to +125
_
C
. . . . . . . . . . . . . . . . . . . . . . . .
Supply Voltage to Ground Potential
(Pin 28 to Pin 14)
-0.5V to +7.0V
. . . . . . . . . . . . . . . . . . . . . . . .
DC Voltage Applied to Outputs
in High Z State
[15]
-0.5V to V
CC
+ 0.5V
. . . . . . . . . . . . . . . . . .
DC Input Voltage
[15]
-0.5V to V
CC
+ 0.5V
. . . . . . . . . . . . . . . .
Output Current into Outputs (LOW)
20 mA
. . . . . . . . . . . . . . .
Static Discharge Voltage
>2001V
. . . . . . . . . . . . . . . . . . . . . . . .
(per MIL STD 883, Method 3015)
Latch Up Current
>200 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Range
Range
Ambient
Temperature
V
CC
Commercial
0
_
C to +70
_
C
5V ± 10%
Military
[16]
-55
_
C to +125
_
C
5V ± 10%
Notes:
15. V
IL
(min.) = -2.0V for pulse durations less than 20 ns.
16. T
A
is the instant on" case temperature.
7c198: 10/25/89
Revision: February 29, 1996
CY7C198
3
Electrical Characteristics
Over the Operating Range
[17]
7C198-15
7C198-20
7C198-25
7C198-35, 45
Parameter
Description
Test Conditions
Min.
Max. Min. Max. Min. Max. Min.
Max. Unit
V
OH
Output HIGH
Voltage
V
CC
= Min.,
I
OH
= -4.0 mA
2.4
2.4
2.4
2.4
V
V
OL
Output LOW
Voltage
V
CC
= Min.,
I
OL
= 8.0 mA
0.4
0.4
0.4
0.4
V
V
IH
Input HIGH
Voltage
2.2
V
CC
+0.3V
2.2
V
CC
+0.3V
2.2
V
CC
2.2
V
CC
V
V
IL
Input LOW
Voltage
[15]
-0.5
0.8
-0.5
0.8
-0.5
0.8
-0.5
0.8
V
I
IX
Input Load Current GND < V
I
< V
CC
-5
+5
-5
+5
-5
+5
-5
+5
mA
I
OZ
Output Leakage
Current
GND < V
O
< V
CC
,
Output Disabled
-5
+5
-5
+5
-5
+5
-5
+5
mA
I
OS
Output Short
Circuit Current
[18]
V
CC
= Max.,
V
OUT
= GND
-300
-300
-300
-300 mA
I
CC
V
CC
Operating
Supply Current
V
CC
= Max.,
I
OUT
= 0 mA
Com'l
150
mA
Supply Current
I
OUT
= 0 mA,
f = f
MAX
= 1/t
RC
Mil
180
170
150
150
I
SB1
Automatic CE
Power Down
Current TTL
Inputs
Max. V
CC
, CE > V
IH
,
V
IN
> V
IH
or V
IN
< V
IL
, f = f
MAX
30
30
30
25
mA
I
SB2
Automatic CE
Power Down
Current CMOS
Inputs
Max. V
CC
,
CE > V
CC
- 0.3V
V
IN
> V
CC
- 0.3V or
V
IN
< 0.3V, f = 0
15
15
15
15
mA
Shaded area contains preliminary information
Capacitance
[19]
Parameter
Description
Test Conditions
Max.
Unit
C
IN
Input Capacitance
T
A
= 25
_
C, f = 1 MHz,
V
5 0V
10
pF
C
OUT
Output Capacitance
V
CC
= 5.0V
10
pF
Notes:
17. See the last page of this specification for Group A subgroup testing in
formation.
18. Not more than one output should be shorted at one time. Duration of
the short circuit should not exceed 30 seconds.
19. Tested initially and after any design or process changes that may affect
these parameters.
7c198: 10/25/89
Revision: February 29, 1996
CY7C198
4
AC Test Loads and Waveforms
[20]
3.0V
5V
OUTPUT
R1 481W
R2
255W
30 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
< f
r
< t
r
5V
OUTPUT
R1 481W
R2
255W
5 pF
INCLUDING
JIG AND
SCOPE
(a)
(b)
OUTPUT
1.73V
Equivalent to:
THЙVENIN EQUIVALENT
ALL INPUT PULSES
C198 5
C198 6
167W
Switching Characteristics
Over the Operating Range
[17, 21]
7C198-15
7C198-20
7C198-25
7C198-35
7C198-45
Parameter
Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
Unit
READ CYCLE
t
RC
Read Cycle Time
15
20
25
35
45
ns
t
AA
Address to Data Valid
15
20
25
35
45
ns
t
OHA
Data Hold from Address Change
3
3
3
3
3
ns
t
ACE
CE LOW to Data Valid
15
20
25
35
45
ns
t
DOE
OE LOW to Data Valid
7
9
10
16
16
ns
t
LZOE
OE LOW to Low Z
[22]
0
0
3
3
3
ns
t
HZOE
OE HIGH to High Z
[22, 23]
7
9
11
15
15
ns
t
LZCE
CE LOW to Low Z
[22]
3
3
3
3
3
ns
t
HZCE
CE HIGH to High Z
[22, 23]
7
9
11
15
15
ns
t
PU
CE LOW to Power Up
0
0
0
0
0
ns
t
PD
CE HIGH to Power Down
15
20
20
20
25
ns
WRITE CYCLE
[24, 25]
t
WC
Write Cycle Time
15
20
25
35
45
ns
t
SCE
CE LOW to Write End
10
15
20
22
22
ns
t
AW
Address Set Up to Write End
10
15
20
30
40
ns
t
HA
Address Hold from Write End
0
0
0
0
0
ns
t
SA
Address Set Up to Write Start
0
0
0
0
0
ns
t
PWE
WE Pulse Width
9
15
20
22
22
ns
t
SD
Data Set Up to Write End
9
10
15
15
15
ns
t
HD
Data Hold from Write End
0
0
0
0
0
ns
t
HZWE
WE LOW to High Z
[23]
7
10
11
15
15
ns
t
LZWE
WE HIGH to Low Z
[22]
3
3
3
3
3
ns
Shaded area contains preliminary information.
Notes:
20 t
r
3 ns for the 15 ns and 20 ns speeds, t
r
5 ns for the 20 ns and
slower speeds.
21. Test conditions assume signal transition time of 3 ns or less for the
12 ns and15 ns speeds and 5 ns for the 20 ns and slower speeds, timing
reference levelsof1.5V, input pulse levels of 0 to 3.0V,andoutputload
ing of the specified I
OL
/I
OH
and 30 pF load capacitance.
22. At any given temperature and voltage condition, t
HZCE
is less than
t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any
given device.
23. t
HZOE
, t
HZCE
, and t
HZWE
are specified with C
L
= 5 pF as in part (b)
of AC Test Loads. Transition is measured ±500 mV from steady state
voltage.
24. The internal write time of the memory is defined by the overlap of CE
LOW and WE LOW. Both signals must be LOW to initiate a write and
either signal can terminate a write by going HIGH. The data input set
up and hold timing should be referenced to the rising edge of the signal
that terminates the write.
25. The minimum write cycle time for write cycle #3 (WE controlled, OE
LOW) is the sum of t
HZWE
and t
SD
.
7c198: 10/25/89
Revision: February 29, 1996
CY7C198
5
Switching Waveforms
Read Cycle No. 1
[26, 27]
ADDRESS
DATA OUT
PREVIOUS DATA VALID
DATA VALID
t
RC
t
AA
t
OHA
C198 7
Read Cycle No. 2
[27, 28]
50%
50%
DATA VALID
t
RC
t
ACE
t
DOE
t
LZOE
t
LZCE
t
PU
DATA OUT
HIGH IMPEDANCE
IMPEDANCE
ICC
ISB
t
HZOE
t
HZCE
t
PD
OE
CE
HIGH
V
CC
SUPPLY
CURRENT
C198 8
Write Cycle No. 1 (WE Controlled)
[24, 29, 30]
t
HD
t
SD
t
PWE
t
SA
t
HA
t
AW
t
WC
DATA I/O
ADDRESS
CE
WE
OE
t
HZOE
C198 9
DATA
IN
VALID
Notes:
26. Device is continuously selected. OE, CE = V
IL
.
27. WE is HIGH for read cycle.
28. Address valid prior to or coincident with CE transition LOW.
29. Data I/O is high impedance ifOE = V
IH
.
30. IfCE goes HIGH simultaneously with WE HIGH, the output remains
in a high impedance state.
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