PRELIMINARY
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined
SRAM with NoBLTM Architecture
CY7C1462AV25
CY7C1464AV25
CY7C1460AV25
Cypress Semiconductor Corporation
·
3901 North First Street
·
San Jose
,
CA 95134
·
408-943-2600
Document #: 38-05354 Rev. *A
Revised December 14, 2004
Features
· Pin-compatible and functionally equivalent to ZBTTM
· Supports 250-MHz bus operations with zero wait states
-- Available speed grades are 250, 200 and 167 MHz
· Internally self-timed output buffer control to eliminate
the need to use asynchronous OE
· Fully registered (inputs and outputs) for pipelined
operation
· Byte Write capability
· Single 2.5V power supply
· 2.5V/1.8V I/O operation
· Fast clock-to-output times
-- 2.6 ns (for 250-MHz device)
-- 3.2 ns (for 200-MHz device)
-- 3.4 ns (for 167-MHz device)
· Clock Enable (CEN) pin to suspend operation
· Synchronous self-timed writes
· CY7C1460AV25 and CY7C1462AV25 available in
lead-free 100 TQFP and 165 fBGA packages
CY7C1464AV25 available in 209-Ball fBGA package
· IEEE 1149.1 JTAG Boundary Scan
· Burst capability--linear or interleaved burst order
· "ZZ" Sleep Mode option and Stop Clock option
Functional Description
The CY7C1460AV25/CY7C1462AV25/CY7C1464AV25 are
2.5V, 1-Mbit x 36/2-Mbit x 18/Synchronous pipelined burst
SRAMs with No Bus LatencyTM (NoBL
TM)
logic, respectively.
They are designed to support unlimited true back-to-back
Read/Write operations with no wait states. The
CY7C1460AV25/CY7C1462AV25/CY7C1464AV25 are
equipped with the advanced (NoBL) logic required to enable
consecutive Read/Write operations with data being trans-
ferred on every clock cycle. This feature dramatically improves
the throughput of data in systems that require frequent
Write/Read transitions. The CY7C1460AV25/ CY7C1462AV25/
CY7C1464AV25 are pin-compatible and functionally equiv-
alent to ZBT devices.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. The
clock input is qualified by the Clock Enable (CEN) signal,
which when deasserted suspends operation and extends the
previous clock cycle. Write operations are controlled by the
Byte Write Selects (BW
a
BW
h
for CY7C1464AV25,
BW
a
BW
d
for CY7C1460AV25 and BW
a
BW
b
for
CY7C1462AV25) and a Write Enable (WE) input. All writes are
conducted with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE
1
, CE
2
, CE
3
) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output three-state control. In order to avoid bus
contention, the output drivers are synchronously three-stated
during the data portion of a write sequence.
A0, A1, A
C
MODE
BW
a
BW
b
WE
CE1
CE2
CE3
OE
READ LOGIC
DQs
DQP
a
DQP
b
DQP
c
DQP
d
D
A
T
A
S
T
E
E
R
I
N
G
O
U
T
P
U
T
B
U
F
F
E
R
S
MEMORY
ARRAY
E
E
INPUT
REGISTER 0
ADDRESS
REGISTER 0
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
REGISTER 2
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
BURST
LOGIC
A0'
A1'
D1
D0
Q1
Q0
A0
A1
C
ADV/LD
ADV/LD
E
INPUT
REGISTER 1
S
E
N
S
E
A
M
P
S
E
CLK
CEN
WRITE
DRIVERS
BW
c
BW
d
ZZ
SLEEP
CONTROL
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
Logic Block DiagramCY7C1460AV25 (1 Mbit x 36)
PRELIMINARY
CY7C1462AV25
CY7C1464AV25
CY7C1460AV25
Document #: 38-05354 Rev. *A
Page 5 of 27
Pin Configurations
(continued)
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
1
2
3
4
5
6
7
8
9
11
10
DQg
DQg
DQg
DQg
DQg
DQg
DQg
DQg
DQc
DQc
DQc
DQc
NC
DQPg
DQh
DQh
DQh
DQh
DQd
DQd
DQd
DQd
DQPd
DQPc
DQc
DQc
DQc
DQc
NC
DQh
DQh
DQh
DQh
DQPh
DQd
DQd
DQd
DQd
DQb
DQb
DQb
DQb
DQb
DQb
DQb
DQb
DQf
DQf
DQf
DQf
NC
DQPf
DQa
DQa
DQa
DQa
DQe
DQe
DQe
DQe
DQPa
DQPb
DQf
DQf
DQf
DQf
NC
DQa
DQa
DQa
DQa
DQPe
DQe
DQe
DQe
DQe
A
A
A
A
NC
NC
NC
NC/72M
A
NC
A
A
A
A
A
A
A1
A0
A
A
A
A
A
A
NC
NC
NC
NC
NC
NC
BWS
b
BWS
f
BWS
e
BWS
a
BWS
c
BWS
g
BWS
d
BWS
h
TMS
TDI
TDO
TCK
NC
NC
MODE
NC
CEN
V
SS
NC
CLK
NC
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
V
DD
NC
OE
CE
3
CE
1
CE
2
ADV/LD
WE
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
ZZ
V
SS
V
SS
V
SS
V
SS
NC
V
DDQ
V
SS
V
SS
NC
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
209-Ball PBGA
CY7C1464AV25 (512K x 72)
Pin Definitions
Pin Name
I/O Type
Pin Description
A0
A1
A
Input-
Synchronous
Address Inputs used to select one of the address locations. Sampled at the rising edge of
the CLK.
BW
a
BW
b
BW
c
BW
d
BW
e
BW
f
BW
g
BW
h
Input-
Synchronous
Byte Write Select Inputs, active LOW. Qualified with WE to conduct writes to the SRAM.
Sampled on the rising edge of CLK. BW
a
controls DQ
a
and DQP
a
, BW
b
controls DQ
b
and DQP
b
,
BW
c
controls DQ
c
and DQP
c
, BW
d
controls DQ
d
and DQP
d
, BW
e
controls DQ
e
and DQP
e
, BW
f
controls DQ
f
and DQP
f
, BW
g
controls DQ
g
and DQP
g
, BW
h
controls DQ
h
and DQP
h
.
WE
Input-
Synchronous
Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This
signal must be asserted LOW to initiate a write sequence.
A0
A1
A
Input-
Synchronous
Address Inputs used to select one of the address locations. Sampled at the rising edge of
the CLK.
PDF 
ZIP
