9-Mb (256K x 36/512K x 18) Pipelined SRAM
with NoBLTM Architecture
CY7C1354B
CY7C1356B
Cypress Semiconductor Corporation
·
3901 North First Street
·
San Jose
,
CA 95134
·
408-943-2600
Document #: 38-05114 Rev. *C
Revised June 16, 2004
Features
· Pin-compatible and functionally equivalent to ZBT
· Supports 225-MHz bus operations with zero wait states
-- Available speed grades are 225, 200, and 166 MHz
· Internally self-timed output buffer control to eliminate
the need to use asynchronous OE
· Fully registered (inputs and outputs) for pipelined op-
eration
· Byte Write capability
· Separate V
DDQ
for 3.3V or 2.5V I/O
· Single 3.3V power supply
· Fast clock-to-output times
-- 2.8 ns (for 225-MHz device)
-- 3.2ns (for 200-MHz device)
-- 3.5 ns (for 166-MHz device)
· Clock Enable (CEN) pin to suspend operation
· Synchronous self-timed writes
· Available in 100 TQFP, 119 BGA, and 165 fBGA packag-
es
· IEEE 1149.1 JTAG Boundary Scan
· Burst capabilitylinear or interleaved burst order
· "ZZ" Sleep Mode option and Stop Clock option
Functional Description
The CY7C1354B and CY7C1356B are 3.3V, 256K x 36 and
512K x 18 Synchronous pipelined burst SRAMs with No Bus
LatencyTM (NoBL
) logic, respectively. They are designed to
support unlimited true back-to-back Read/Write operations
with no wait states. The CY7C1354B and CY7C1356B are
equipped with the advanced (NoBL) logic required to enable
consecutive Read/Write operations with data being trans-
ferred on every clock cycle. This feature dramatically improves
the throughput of data in systems that require frequent
Write/Read transitions. The CY7C1354B and CY7C1356B are
pin compatible and functionally equivalent to ZBT devices.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. The
clock input is qualified by the Clock Enable (CEN) signal,
which when deasserted suspends operation and extends the
previous clock cycle.
Write operations are controlled by the Byte Write Selects
(BW
a
BW
d
for CY7C1354B and BW
a
BW
b
for CY7C1356B)
and a Write Enable (WE) input. All writes are conducted with
on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE
1
, CE
2
, CE
3
) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output three-state control. In order to avoid bus
contention, the output drivers are synchronously three-stated
during the data portion of a write sequence.
A0, A1, A
C
MODE
BW
a
BW
b
WE
CE1
CE2
CE3
OE
READ LOGIC
DQs
DQP
a
DQP
b
DQP
c
DQP
d
D
A
T
A
S
T
E
E
R
I
N
G
O
U
T
P
U
T
B
U
F
F
E
R
S
MEMORY
ARRAY
E
E
INPUT
REGISTER 0
ADDRESS
REGISTER 0
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
REGISTER 2
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
BURST
LOGIC
A0'
A1'
D1
D0
Q1
Q0
A0
A1
C
ADV/LD
ADV/LD
E
INPUT
REGISTER 1
S
E
N
S
E
A
M
P
S
E
CLK
CEN
WRITE
DRIVERS
BW
c
BW
d
ZZ
SLEEP
CONTROL
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
Logic Block Diagram-CY7C1354B (256K x 36)
PDF 
ZIP
