4-Mb (256K x 18) Flow-through SRAM with NoBLTM Architecture
CY7C1353F
Cypress Semiconductor Corporation
·
3901 North First Street
·
San Jose
,
CA 95134
·
408-943-2600
Document #: 38-05212 Rev. *B
Revised January 13, 2004
Features
· Can support up to 133-MHz bus operations with zero
wait states
-- Data is transferred on every clock
· Pin compatible and functionally equivalent to ZBTTM
devices
· Internally self-timed output buffer control to eliminate
the need to use OE
· Registered inputs for flow-through operation
· Byte Write capability
· 256K x 18 common I/O architecture
· 2.5V / 3.3V I/O power supply
· Fast clock-to-output times
-- 6.5 ns (for 133-MHz device)
-- 7.5 ns (for 117-MHz device)
-- 8.0 ns (for 100-MHz device)
-- 11.0 ns (for 66-MHz device)
· Clock Enable (CEN) pin to suspend operation
· Synchronous self-timed writes
· Asynchronous Output Enable
· JEDEC-standard 100 TQFP package
· Burst Capability--linear or interleaved burst order
· Low standby power
Functional Description
[1]
The CY7C1353F is a 3.3V, 256K x 18 Synchronous
Flow-through Burst SRAM designed specifically to support
unlimited true back-to-back Read/Write operations without the
insertion of wait states. The CY7C1353F is equipped with the
advanced No Bus LatencyTM (NoBLTM) logic required to
enable consecutive Read/Write operations with data being
transferred on every clock cycle. This feature dramatically
improves the throughput of data through the SRAM, especially
in systems that require frequent Write-Read transitions.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. The clock input is qualified by
the Clock Enable (CEN) signal, which when deasserted
suspends operation and extends the previous clock cycle.
Maximum access delay from the clock rise is 6.5 ns (133-MHz
device).
Write operations are controlled by the two Byte Write Select
(BW
[A:B]
) and a Write Enable (WE) input. All writes are
conducted with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE
1
, CE
2
, CE
3
) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output three-state control. In order to avoid bus
contention, the output drivers are synchronously three-stated
during the data portion of a write sequence.
1
Note:
1. For bestpractices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
C
MODE
BW
A
BW
B
WE
CE
1
CE
2
CE
3
OE
READ LOGIC
DQs
DQP
A
DQP
B
MEMORY
ARRAY
E
INPUT
REGISTER
ADDRESS
REGISTER
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
BURST
LOGIC
A0'
A1'
D1
D0
Q1
Q0
A0
A1
ADV/LD
CE
ADV/LD
C
CLK
CEN
WRITE
DRIVERS
D
A
T
A
S
T
E
E
R
I
N
G
S
E
N
S
E
A
M
P
S
WRITE ADDRESS
REGISTER
A0, A1, A
O
U
T
P
U
T
B
U
F
F
E
R
S
E
ZZ
SLEEP
CONTROL
Logic Block Diagram
CY7C1353F
Document #: 38-05212 Rev. *B
Page 2 of 13
Selection Guide
133 MHz
117 MHz
100 MHz
66 MHz
Unit
Maximum Access Time
6.5
7.5
8.0
11.0
ns
Maximum Operating Current
225
220
205
195
mA
Maximum CMOS Standby Current
40
40
40
40
mA
Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts.
Pin Configurations
100-lead TQFP
A
A
A
A
A1
A0
NC
NC
V
SS
V
DD
NC /
36M
A
A
A
A
A
A
A
NC
NC
V
DDQ
V
SS
NC
DQP
A
DQ
A
DQ
A
V
SS
V
DDQ
DQ
A
DQ
A
V
SS
NC
V
DD
DQ
A
DQ
A
V
DDQ
V
SS
DQ
A
DQ
A
NC
NC
V
SS
V
DDQ
NC
NC
NC
NC
NC
NC
V
DDQ
V
SS
NC
NC
DQ
B
DQ
B
V
SS
V
DDQ
DQ
B
DQ
B
NC
V
DD
NC
V
SS
DQ
B
DQ
B
V
DDQ
V
SS
DQ
B
DQ
B
DQP
B
NC
V
SS
V
DDQ
NC
NC
NC
A
A
CE
1
CE
2
NC
NC
BW
B
BW
A
CE
3
V
DD
V
SS
CLK
WE
CEN
OE
NC /
18
M
A
A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
A
NC /
9M
ADV/LD
ZZ
MODE
NC /
72M
CY7C1353F
BYTE A
BYTE B
CY7C1353F
Document #: 38-05212 Rev. *B
Page 3 of 13
Pin Definitions
(100-pin TQFP Package)
Name
TQFP
I/O
Description
A
0
, A
1
, A
37,36,32,33,34,
35,44,45,46,47,
48,49,50,80,81,
82,99,100
Input-
Synchronous
Address Inputs used to select one of the 256K address locations. Sampled
at the rising edge of the CLK. A
[1:0]
are fed to the two-bit burst counter.
BW
[A:B]
93,94
Input-
Synchronous
Byte Write Inputs, active LOW. Qualified with WE to conduct writes to the
SRAM. Sampled on the rising edge of CLK.
WE
88
Input-
Synchronous
Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is
active LOW. This signal must be asserted LOW to initiate a write sequence.
ADV/LD
85
Input-
Synchronous
Advance/Load Input. Used to advance the on-chip address counter or load a
new address. When HIGH (and CEN is asserted LOW) the internal burst counter
is advanced. When LOW, a new address can be loaded into the device for an
access. After being deselected, ADV/LD should be driven LOW in order to load
a new address.
CLK
89
Input-Clock
Clock Input. Used to capture all synchronous inputs to the device. CLK is
qualified with CEN. CLK is only recognized if CEN is active LOW.
CE
1
98
Input-
Synchronous
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE
2
, and CE
3
to select/deselect the device.
CE
2
97
Input-
Synchronous
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in
conjunction with CE
1
and CE
3
to select/deselect the device.
CE
3
92
Input-
Synchronous
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE
1
and
CE
2
to select/deselect the device.
OE
86
Input-
Asynchronous
Output Enable, asynchronous input, active LOW. Combined with the
synchronous logic block inside the device to control the direction of the I/O pins.
When LOW, the I/O pins are allowed to behave as outputs. When deasserted
HIGH, I/O pins are three-stated, and act as input data pins. OE is masked during
the data portion of a write sequence, during the first clock when emerging from
a deselected state, when the device has been deselected.
CEN
87
Input-
Synchronous
Clock Enable Input, active LOW. When asserted LOW the Clock signal is recog-
nized by the SRAM. When deasserted HIGH the Clock signal is masked. Since
deasserting CEN does not deselect the device, CEN can be used to extend the
previous cycle when required.
ZZ
64
Input-
Asynchronous
ZZ "sleep" Input. This active HIGH input places the device in a non-time critical
"sleep" condition with data integrity preserved. During normal operation, this pin
can be connected to Vss or left floating.
DQ
s
58,59,62,63,68,
69,72,73,8,9,
12,13,18,19,22,
23
I/O-
Synchronous
Bidirectional Data I/O Lines. As inputs, they feed into an on-chip data register
that is triggered by the rising edge of CLK. As outputs, they deliver the data
contained in the memory location specified by address during the clock rise of
the read cycle. The direction of the pins is controlled by OE and the internal control
logic. When OE is asserted LOW, the pins can behave as outputs. When HIGH,
DQ
s
and DQP
[A:B]
are placed in a three-state condition. The outputs are automat-
ically three-stated during the data portion of a write sequence, during the first
clock when emerging from a deselected state, and when the device is deselected,
regardless of the state of OE.
DQP
[A:B]
74,24
I/O-
Synchronous
Bidirectional Data Parity I/O Lines. Functionally, these signals are identical to
DQ
s
. During write sequences, DQP
[A:B]
is controlled by BW
x
correspondingly.
Mode
31
Input
Strap Pin
Mode Input. Selects the burst order of the device.
When tied to Gnd selects linear burst sequence. When tied to V
DD
or left floating
selects interleaved burst sequence.
V
DD
15,41,65,91
Power Supply Power supply inputs to the core of the device.
V
DDQ
4,11,20,27,54,
61,70,77
I/O Power
Supply
Power supply for the I/O circuitry.
V
SS
5,10,17,21,26,
40,55,60,67,71,
76,90
Ground
Ground for the device.
CY7C1353F
Document #: 38-05212 Rev. *B
Page 4 of 13
Functional Overview
The CY7C1353F is a synchronous flow-through burst SRAM
designed specifically to eliminate wait states during
Write-Read transitions. All synchronous inputs pass through
input registers controlled by the rising edge of the clock. The
clock signal is qualified with the Clock Enable input signal
(CEN). If CEN is HIGH, the clock signal is not recognized and
all internal states are maintained. All synchronous operations
are qualified with CEN. Maximum access delay from the clock
rise (t
CDV
) is 6.5 ns (133-MHz device).
Accesses can be initiated by asserting all three Chip Enables
(CE
1
, CE
2
, CE
3
) active at the rising edge of the clock. If Clock
Enable (CEN) is active LOW and ADV/LD is asserted LOW,
the address presented to the device will be latched. The
access can either be a read or write operation, depending on
the status of the Write Enable (WE). BW
[A:B]
can be used to
conduct byte write operations.
Write operations are qualified by the Write Enable (WE). All
writes are simplified with on-chip synchronous self-timed write
circuitry.
Three synchronous Chip Enables (CE
1
, CE
2
, CE
3
) and an
asynchronous Output Enable (OE) simplify depth expansion.
All operations (Reads, Writes, and Deselects) are pipelined.
ADV/LD should be driven LOW once the device has been
deselected in order to load a new address for the next
operation.
Single Read Accesses
A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE
1
, CE
2
,
and CE
3
are ALL asserted active, (3) the Write Enable input
signal WE is deasserted HIGH, and 4) ADV/LD is asserted
LOW. The address presented to the address inputs is latched
into the Address Register and presented to the memory array
and control logic. The control logic determines that a read
access is in progress and allows the requested data to
propagate to the output buffers. The data is available within 6.5
ns (133-MHz device) provided OE is active LOW. After the first
clock of the read access, the output buffers are controlled by
OE and the internal control logic. OE must be driven LOW in
order for the device to drive out the requested data. On the
subsequent clock, another operation (Read/Write/Deselect)
can be initiated. When the SRAM is deselected at clock rise
by one of the chip enable signals, its output will be three-stated
immediately.
Burst Read Accesses
The CY7C1353F has an on-chip burst counter that allows the
user the ability to supply a single address and conduct up to
four Reads without reasserting the address inputs. ADV/LD
must be driven LOW in order to load a new address into the
SRAM, as described in the Single Read Access section above.
The sequence of the burst counter is determined by the MODE
input signal. A LOW input on MODE selects a linear burst
mode, a HIGH selects an interleaved burst sequence. Both
burst counters use A0 and A1 in the burst sequence, and will
wrap around when incremented sufficiently. A HIGH input on
ADV/LD will increment the internal burst counter regardless of
the state of chip enable inputs or WE. WE is latched at the
beginning of a burst cycle. Therefore, the type of access (Read
or Write) is maintained throughout the burst sequence.
Single Write Accesses
Write access are initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE
1
, CE
2
,
and CE
3
are ALL asserted active, and (3) the write signal WE
is asserted LOW. The address presented to the address bus
is loaded into the Address Register. The write signals are
latched into the Control Logic block. The data lines are
automatically three-stated regardless of the state of the OE
input signal. This allows the external logic to present the data
on DQs and DQP
[A:B]
.
On the next clock rise the data presented to DQs and DQP
[A:B]
(or a subset for byte write operations, see truth table for
details) inputs is latched into the device and the write is
complete. Additional accesses (Read/Write/Deselect) can be
initiated on this cycle.
The data written during the Write operation is controlled by
BW
[A:B]
signals. The CY7C1353F provides byte write
capability that is described in the truth table. Asserting the
Write Enable input (WE) with the selected Byte Write Select
input will selectively write to only the desired bytes. Bytes not
selected during a byte write operation will remain unaltered. A
synchronous self-timed write mechanism has been provided
to simplify the write operations. Byte write capability has been
included in order to greatly simplify Read/Modify/Write
sequences, which can be reduced to simple byte write opera-
tions.
Because the CY7C1353F is a common I/O device, data should
not be driven into the device while the outputs are active. The
Output Enable (OE) can be deasserted HIGH before
presenting data to the DQs and DQP
[A:B]
inputs. Doing so will
three-state the output drivers. As a safety precaution, DQs and
DQP
[A:B]
.are automatically three-stated during the data
portion of a write cycle, regardless of the state of OE.
Burst Write Accesses
The CY7C1353F has an on-chip burst counter that allows the
user the ability to supply a single address and conduct up to
four Write operations without reasserting the address inputs.
ADV/LD must be driven LOW in order to load the initial
address, as described in the Single Write Access section
above. When ADV/LD is driven HIGH on the subsequent clock
rise, the Chip Enables (CE
1
, CE
2
, and CE
3
) and WE inputs are
ignored and the burst counter is incremented. The correct
NC
1,2,3,6,7,14,16,
25,28,29,30,38,
39,42,43,51,52,
53,56,57,66,75,
78,79,83,84,95,
96
No Connects. Not Internally connected to the die.
9M,18M,36M and 72M are address expansion pins and are not internally
connected to the die.
Pin Definitions
(100-pin TQFP Package) (continued)
Name
TQFP
I/O
Description
CY7C1353F
Document #: 38-05212 Rev. *B
Page 5 of 13
BW
[A:B]
inputs must be driven in each cycle of the burst write,
in order to write the correct bytes of data.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation "sleep" mode. Two
clock cycles are required to enter into or exit from this "sleep"
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the "sleep" mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the "sleep" mode. CE
1
, CE
2
, and CE
3
, must remain inactive for
the duration of t
ZZREC
after the ZZ input returns LOW.
Linear Burst Address Table (MODE = GND)
First
Address
A1, A0
Second
Address
A1, A0
Third
Address
A1, A0
Fourth
Address
A1, A0
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
Interleaved Burst Address Table (MODE =
Floating or V
DD
)
First
Address
A1, A0
Second
Address
A1, A0
Third
Address
A1, A0
Fourth
Address
A1, A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
ZZ Mode Electrical Characteristics
Parameter
Description
Test Conditions
Min.
Max.
Unit
I
DDZZ
Snooze mode standby current
ZZ > V
DD
- 0.2V
40
mA
t
ZZS
Device operation to ZZ
ZZ > V
DD
- 0.2V
2t
CYC
ns
t
ZZREC
ZZ recovery time
ZZ < 0.2V
2t
CYC
ns
t
ZZI
ZZ active to snooze current
This parameter is sampled
2t
CYC
ns
t
RZZI
ZZ inactive to exit snooze current
This parameter is sampled
0
ns
Truth Table
[2, 3, 4, 5, 6, 7, 8]
Operation
ADDRESS
Used
CE
1
CE
2
CE
3
ZZ
ADV/LD
WE
BW
X
OE
CEN
CLK
DQ
Deselect Cycle
None
H
X
X
L
L
X
X
X
L
L->H
three-state
Deselect Cycle
None
X
X
H
L
L
X
X
X
L
L->H
three-state
Deselect Cycle
None
X
L
X
L
L
X
X
X
L
L->H
three-state
Continue Deselect Cycle
None
X
X
X
L
H
X
X
X
L
L->H
three-state
READ Cycle
(Begin Burst)
External
L
H
L
L
L
H
X
L
L
L->H Data Out (Q)
READ Cycle
(Continue Burst)
Next
X
X
X
L
H
X
X
L
L
L->H Data Out (Q)
NOP/DUMMY READ
(Begin Burst)
External
L
H
L
L
L
H
X
H
L
L->H
three-state
DUMMY READ
(Continue Burst)
Next
X
X
X
L
H
X
X
H
L
L->H
three-state
WRITE Cycle
(Begin Burst)
External
L
H
L
L
L
L
L
X
L
L->H Data In (D)
Notes:
2. X ="Don't Care." H = Logic HIGH, L = Logic LOW. BWx = 0 signifies at least one Byte Write Select is active, BWx = Valid signifies that the desired byte write
selects are asserted, see truth table for details.
3. Write is defined by BW
[A:B]
, and WE. See truth table for Read/Write.
4. When a write cycle is detected, all I/Os are three-stated, even during byte writes.
5. The DQs and DQP
[A:B]
pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
6. CEN = H, inserts wait states.
7. Device will power-up deselected and the I/Os in a three-state condition, regardless of OE.
8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQP
[A:B]
= Three-state when
OE is inactive or when the device is deselected, and DQs and DQP
[A:B]
= data when OE is active.
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