PRELIMINARY

128Kx36 Pipelined SRAM with NoBLTM Architecture

CY7C1350B

Cypress Semiconductor Corporation

3901 North First Street

San Jose

CA 95134

408-943-2600

Document #: 38-05045 Rev. **

Revised September 7, 2001

350B

Features

· Pin compatible and functionally equivalent to ZBTTM

devices IDT71V546, MT55L128L36P, and MCM63Z736

· Supports 166-MHz bus operations with zero wait states

-- Data is transferred on every clock

· Internally self-timed output buffer control to eliminate

the need to use OE

· Fully registered (inputs and outputs) for pipelined

operation

· Byte Write capability
· 128K x 36 common I/O architecture
· Single 3.3V power supply
· Fast clock-to-output times

-- 3.5 ns (for 166-MHz device)

-- 3.8 ns (for 150-MHz device)

-- 4.0 ns (for 143-MHz device)

-- 4.2 ns (for 133-MHz device)

-- 5.0 ns (for 100-MHz device)

-- 7.0 ns (for 80-MHz device)

· Clock Enable (CEN) pin to suspend operation
· Synchronous self-timed writes
· Asynchronous output enable
· JEDEC-standard 100 TQFP package
· Burst Capability--linear or interleaved burst order
· Low standby power (17.325 mW max.)

Functional Description

The CY7C1350B is a 3.3V, 128K by 36 synchronous-pipelined
Burst SRAM designed specifically to support unlimited true
back-to-back Read/Write operations without the insertion of
wait states. The CY7C1350B is equipped with the advanced
No Bus LatencyTM (NoBLTM) logic required to enable consec-
utive Read/Write operations with data being transferred on ev-
ery clock cycle. This feature dramatically improves the
throughput of the SRAM, especially in systems that require
frequent Write/Read transitions. The CY7C1350B is pin/func-
tionally compatible to ZBT SRAMs IDT71V546,
MT55L128L36P, and MCM63Z736.

All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. The
clock input is qualified by the Clock Enable (CEN) signal, which
when deasserted suspends operation and extends the previ-
ous clock cycle. Maximum access delay from the clock rise is
3.5 ns (166-MHz device).

Write operations are controlled by the four Byte Write Select
(BWS

[3:0]

) and a Write Enable (WE) input. All writes are con-

ducted with on-chip synchronous self-timed write circuitry.

Three synchronous Chip Enables (CE

, CE

) and an

asynchronous Output Enable (OE) provide for easy bank se-
lection and output three-state control. In order to avoid bus
contention, the output drivers are synchronously three-stated
during the data portion of a write sequence.

NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation.
ZBT is a trademark of Integrated Device Technology.

CLK

[16:0]

CEN

BWS

[3:0]

CE1

CE2

OOUTP

128Kx36

MEMORY

ARRAY

CLK

Logic Block Diagram

[31:0]

Data-In REG.

CONTROL

and WRITE

LOGIC

I
S

and LO

I
C

ADV/LD

[3:0]

MODE

Selection Guide

-166

-150

-143

-133

-100

-80

Maximum Access Time (ns)

3.5

3.8

4.0

4.2

5.0

7.0

Maximum Operating Current (mA)

Commercial

400

375

350

300

250

200

Maximum CMOS Standby Current (mA)

Commercial

Shaded areas contain advance information.

CY7C1350B

PRELIMINARY

Document #: 38-05045 Rev. **

Page 2 of 14

Pin Configuration

DNU

DDQ

CLK

100

DNU

CY7C1350B

100-Pin TQFP

CY7C1350B

PRELIMINARY

Document #: 38-05045 Rev. **

Page 3 of 14

Pin Definitions

Pin Number

Name

I/O

Description

5044,
8182, 99,
100, 3237

[16:0]

Input-
Synchronous

Address Inputs used to select one of the 131,072 address locations. Sampled at
the rising edge of the CLK.

9693

BWS

[3:0]

Input-
Synchronous

Byte Write Select Inputs, active LOW. Qualified with WE to conduct writes to the
SRAM. Sampled on the rising edge of CLK. BWS

controls DQ

[7:0]

and DP

, BWS

controls DQ

[15:8]

and DP

, BWS

controls DQ

[23:16]

and DP

, BWS

controls

[31:24]

and DP

. See Write Cycle Description table for details.

Input-
Synchronous

Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active
LOW. This signal must be asserted LOW to initiate a write sequence.

ADV/LD

Input-
Synchronous

Advance/Load Input used to advance the on-chip address counter or load a new
address. When HIGH (and CEN is asserted LOW) the internal burst counter is
advanced. When LOW, a new address can be loaded into the device for an access.
After being deselected, ADV/LD should be driven LOW in order to load a new
address.

CLK

Input-Clock

Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified
with CEN. CLK is only recognized if CEN is active LOW.

Input-
Synchronous

Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE

, and CE

to select/deselect the device.

Input-
Synchronous

Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in
conjunction with CE

and CE

to select/deselect the device.

Input-
Synchronous

Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE

and

to select/deselect the device.

Input-
Asynchronous

Output Enable, active LOW. Combined with the synchronous logic block inside the
device to control the direction of the I/O pins. When LOW, the I/O pins are allowed
to behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act
as input data pins. OE is masked during the data portion of a write sequence,
during the first clock when emerging from a deselected state, when the device has
been deselected.

CEN

Input-
Synchronous

Clock Enable Input, active LOW. When asserted LOW the clock signal is recog-
nized by the SRAM. When deasserted HIGH the Clock signal is masked. Since
deasserting CEN does not deselect the device, CEN can be used to extend the
previous cycle when required.

2928,
2522,
1918,
1312, 96,
32, 7978,
7572,
6968, 6362
5956, 5352

[31:0]

I/O-
Synchronous

Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that
is triggered by the rising edge of CLK. As outputs, they deliver the data contained
in the memory location specified by A

[16:0]

during the previous clock rise of the

read cycle. The direction of the pins is controlled by OE and the internal control
logic. When OE is asserted LOW, the pins can behave as outputs. When HIGH,
DQ

[31:0]

are placed in a three-state condition. The outputs are automatically

three-stated during the data portion of a write sequence, during the first clock when
emerging from a deselected state, and when the device is deselected, regardless
of the state of OE.

30, 1, 80 51

[3:0]

I/O-
Synchronous

Bidirectional Data Parity I/O lines. Functionally, these signals are identical to
DQ

[31:0]

. During write sequences, DP

is controlled by BWS

, DP

is controlled by

BWS

, DP

is controlled by BWS

, and DP

is controlled by BWS

MODE

Input Strap pin

Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved
burst order. Pulled LOW selects the linear burst order. MODE should not change
states during operation. When left floating MODE will default HIGH, to an inter-
leaved burst order.

15, 16, 41, 65,
66, 91

Power Supply

Power supply inputs to the core of the device. Should be connected to 3.3V power
supply.

4, 11, 14, 20,
27, 54, 61, 70,
77

DDQ

I/O Power
Supply

Power supply for the I/O circuitry. Should be connected to a 3.3V power supply.

CY7C1350B

PRELIMINARY

Document #: 38-05045 Rev. **

Page 4 of 14

Introduction

Functional Overview

The CY7C1350B is a synchronous-pipelined Burst SRAM de-
signed specifically to eliminate wait states during Write/Read
transitions. All synchronous inputs pass through input regis-
ters controlled by the rising edge of the clock. The clock signal
is qualified with the Clock Enable input signal (CEN). If CEN is
HIGH, the clock signal is not recognized and all internal states
are maintained. All synchronous operations are qualified with
CEN. All data outputs pass through output registers controlled
by the rising edge of the clock. Maximum access delay from
the clock rise (t

) is 3.5 ns (166-MHz device).

Accesses can be initiated by asserting all three Chip Enables
(CE

, CE

) active at the rising edge of the clock. If Clock

Enable (CEN) is active LOW and ADV/LD is asserted LOW,
the address presented to the device will be latched. The ac-
cess can either be a read or write operation, depending on the
status of the Write Enable (WE). BWS

[3:0]

can be used to con-

duct byte write operations.

Write operations are qualified by the Write Enable (WE). All
writes are simplified with on-chip synchronous self-timed write
circuitry.

Three synchronous Chip Enables (CE

, CE

) and an

asynchronous Output Enable (OE) simplify depth expansion.
All operations (Reads, Writes, and Deselects) are pipelined.
ADV/LD should be driven LOW once the device has been de-
selected in order to load a new address for the next operation.

Single Read Accesses

A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE

, CE

and CE

are ALL asserted active, (3) the Write Enable input

signal WE is deasserted HIGH, and (4) ADV/LD is asserted
LOW. The address presented to the address inputs (A

)

is latched into the Address Register and presented to the
memory core and control logic. The control logic determines
that a read access is in progress and allows the requested
data to propagate to the input of the output register. At the
rising edge of the next clock the requested data is allowed to
propagate through the output register and onto the data bus
within 3.5 ns (166-MHz device) provided OE is active LOW.
After the first clock of the read access the output buffers are
controlled by OE and the internal control logic. OE must be
driven LOW in order for the device to drive out the requested
data. During the second clock, a subsequent operation
(Read/Write/Deselect) can be initiated. Deselecting the device
is also pipelined. Therefore, when the SRAM is deselected at
clock rise by one of the chip enable signals, its output will
three-state following the next clock rise.

Burst Read Accesses

The CY7C1350B has an on-chip burst counter that allows the
user the ability to supply a single address and conduct up to
four Reads without reasserting the address inputs. ADV/LD
must be driven LOW in order to load a new address into the
SRAM, as described in the Single Read Access section above.
The sequence of the burst counter is determined by the MODE
input signal. A LOW input on MODE selects a linear burst
mode, a HIGH selects an interleaved burst sequence. Both
burst counters use A0 and A1 in the burst sequence, and will
wrap-around when incremented sufficiently. A HIGH input on
ADV/LD will increment the internal burst counter regardless of
the state of chip enables inputs or WE. WE is latched at the
beginning of a burst cycle. Therefore, the type of access (Read
or Write) is maintained throughout the burst sequence.

Single Write Accesses

Write access are initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE

, CE

and CE

are ALL asserted active, and (3) the write signal WE

is asserted LOW. The address presented to A

is loaded

into the Address Register. The write signals are latched into
the Control Logic block.

On the subsequent clock rise the data lines are automatically
three-stated regardless of the state of the OE input signal. This
allows the external logic to present the data on DQ

[31:0]

and

[3:0]

. In addition, the address for the subsequent access

(Read/Write/Deselect) is latched into the Address Register
(provided the appropriate control signals are asserted).

On the next clock rise the data presented to DQ

[31:0]

and

[3:0]

(or a subset for byte write operations, see Write Cycle

Description table for details) inputs is latched into the device
and the write is complete.

The data written during the Write operation is controlled by
BWS

[3:0]

signals. The CY7C1350B provides byte write capa-

bility that is described in the Write Cycle Description table.
Asserting the Write Enable input (WE) with the selected Byte
Write Select (BWS

[3:0]

) input will selectively write to only the

desired bytes. Bytes not selected during a byte write operation
will remain unaltered. A synchronous self-timed write mecha-
nism has been provided to simplify the write operations. Byte
write capability has been included in order to greatly simplify
Read/Modify/Write sequences, which can be reduced to sim-
ple byte write operations.

Because the CY7C1350B is a common I/O device, data
should not be driven into the device while the outputs are ac-
tive. The Output Enable (OE) can be deasserted HIGH before
presenting data to the DQ

[31:0]

and DP

[3:0]

inputs. Doing so will

three-state the output drivers. As a safety precaution, DQ

[31:0]

5, 10, 17, 21,
26, 40, 55, 60,
64, 67, 71, 76,
90

Ground

Ground for the device. Should be connected to ground of the system.

83, 84

No connects. Reserved for address inputs for depth expansion. Pin 83 and 84 will
be used for 256K and 512K depths respectively.

38, 39, 42, 43

DNU

Do Not Use pins. These pins should be left floating or tied to V

Pin Definitions

(continued)

Pin Number

Name

I/O

Description

CY7C1350B

PRELIMINARY

Document #: 38-05045 Rev. **

Page 5 of 14

and DP

[3:0]

are automatically three-stated during the data por-

tion of a write cycle, regardless of the state of OE.

Burst Write Accesses

The CY7C1350B has an on-chip burst counter that allows the
user the ability to supply a single address and conduct up to
four WRITE operations without reasserting the address inputs.
ADV/LD must be driven LOW in order to load the initial ad-
dress, as described in the Single Write Access section above.
When ADV/LD is driven HIGH on the subsequent clock rise,
the chip enables (CE

, CE

, and CE

) and WE inputs are ig-

nored and the burst counter is incremented. The correct
BWS

[3:0]

inputs must be driven in each cycle of the burst write

in order to write the correct bytes of data.

Interleaved Burst Sequence

First

Address

Second

Address

Third

Address

Fourth

Address

Ax+1, Ax

Linear Burst Sequence

First

Address

Second

Address

Third

Address

Fourth

Address

Ax+1, Ax

Cycle Description Truth Table

[

1, 2, 3, 4, 5, 6

]

Operation

Address

Used

CEN

ADV/

LD/

BWS

CLK

Comments

Deselected

External

L-H

I/Os three-state following next rec-
ognized clock.

Suspend

L-H

Clock ignored, all operations sus-
pended.

Begin Read

External

L-H

Address latched.

Begin Write

External

Valid

L-H

Address latched, data presented
two valid clocks later.

Burst Read
Operation

Internal

L-H

Burst Read operation. Previous ac-
cess was a Read operation. Ad-
dresses incremented internally in
conjunction with the state of
MODE.

Burst Write
Operation

Internal

Valid

L-H

Burst Write operation. Previous ac-
cess was a Write operation. Ad-
dresses incremented internally in
conjunction with the state of
MODE. Bytes written are deter-
mined by BWS

[3:0]

Notes:

X="Don't Care", 1=Logic HIGH, 0=Logic LOW, CE stands for ALL Chip Enables active. BWSx = 0 signifies at least one Byte Write Select is active, BWSx =
Valid signifies that the desired byte write selects are asserted, see Write Cycle Description table for details.

Write is defined by WE and BWS[3:0]. See Write Cycle Description table for details.

The DQ and DP pins are controlled by the current cycle and the OE signal.

CEN=1 inserts wait states.

Device will power-up deselected and the I/Os in a three-state condition, regardless of OE.

OE assumed LOW.

Part Number CY7C1350B