PRELIMINARY

4-Mbit (128K x 32) Pipelined Sync SRAM

CY7C1339G

Cypress Semiconductor Corporation

3901 North First Street

San Jose

CA 95134

408-943-2600

Document #: 38-05520 Rev. *A

Revised November 10, 2004

Features

ˇ Registered inputs and outputs for pipelined operation
ˇ 128K × 32 common I/O architecture
ˇ 3.3V core power supply
ˇ 2.5V / 3.3V I/O operation
ˇ Fast clock-to-output times

-- 2.6 ns (for 250-MHz device)
-- 2.8 ns (for 200-MHz device)
-- 3.5 ns (for 166-MHz device)
-- 4.0 ns (for 133-MHz device)

ˇ Provide high-performance 3-1-1-1 access rate
ˇ User-selectable burst counter supporting Intel

Pentium

interleaved or linear burst sequences

ˇ Separate processor and controller address strobes
ˇ Synchronous self-timed writes
ˇ Asynchronous output enable
ˇ Lead-Free 100-pin TQFP and 119-ball BGA packages
ˇ "ZZ" Sleep Mode Option

Functional Description

[1]

The CY7C1339G SRAM integrates 131,072 x 32 SRAM cells

with advanced synchronous peripheral circuitry and a two-bit

counter for internal burst operation. All synchronous inputs are

gated by registers controlled by a positive-edge-triggered

Clock Input (CLK). The synchronous inputs include all

addresses, all data inputs, address-pipelining Chip Enable

(CE

), depth-expansion Chip Enables (CE

and

), Burst

Control inputs (ADSC, ADSP, and ADV), Write Enables

(BW

[A:D]

, and BWE), and Global Write (GW). Asynchronous

inputs include the Output Enable (OE) and the ZZ pin.
Addresses and chip enables are registered at rising edge of

clock when either Address Strobe Processor (ADSP) or

Address Strobe Controller (ADSC) are active. Subsequent

burst addresses can be internally generated as controlled by

the Advance pin (ADV).
Address, data inputs, and write controls are registered on-chip

to initiate a self-timed Write cycle.This part supports Byte Write

operations (see Pin Descriptions and Truth Table for further

details). Write cycles can be one to four bytes wide as

controlled by the byte write control inputs. GW when active

LOW causes all bytes to be written.
The CY7C1339G operates from a +3.3V core power supply

while all outputs may operate with either a +2.5 or +3.3V

supply. All inputs and outputs are JEDEC-standard

JESD8-5-compatible.

Note:

1. For bestpractices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

A DDRESS
REGISTER

A DV

CLK

BURST

COUNTER

A ND

LOGIC

CLR

A DSP

A DSC

M ODE

BW E

ENA BLE

OUTPUT

REGISTERS

SENSE
A M PS

OUTPUT
BUFFERS

PIPELINED

ENA BLE

INPUT

REGISTERS

A 0, A 1, A

M EM ORY

A RRA Y

D Q s

SLEEP

CONTROL

[1:0]

BY TE

W RITE REGISTER

BY TE

W RITE REGISTER

BY TE

W RITE REGISTER

BY TE

W RITE REGISTER

BY TE

W RITE DRIVER

BY TE

W RITE DRIVER

BY TE

W RITE DRIVER

BY TE

W RITE DRIVER

Logic Block Diagram

PRELIMINARY

CY7C1339G

Document #: 38-05520 Rev. *A

Page 2 of 17

Pin Configurations

Selection Guide

250 MHz

200 MHz

166 MHz

133 MHz

Unit

Maximum Access Time

2.6

2.8

3.5

4.0

Maximum Operating Current

325

265

240

225

Maximum CMOS Standby Current

Shaded area contains advanced information. Please contact your local Cypress sales representative for availability of these parts.

NC NC

NC
DQ

DDQ

SSQ

DDQ

NC
V

ZZ
DQ

DDQ

SSQ

DDQ

SSQ

DDQ

SSQ

DDQ

CLK

BWE

ADSC

ADSP

ADV

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

100

MODE

BYTE A

BYTE B

BYTE D

BYTE C

100-pin TQFP

CY7C1339G

PRELIMINARY

CY7C1339G

Document #: 38-05520 Rev. *A

Page 3 of 17

Pin Configurations

(continued)

Pin Definitions

Name

I/O

Description

, A

Input-

Synchronous

Address Inputs used to select one of the 128K address locations. Sampled at the rising edge

of the CLK if ADSP or ADSC is active LOW, and CE

, and

are sampled active. A1, A0

are fed to the two-bit counter..

Input-

Synchronous

Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM.

Sampled on the rising edge of CLK.

Input-

Synchronous

Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a global

write is conducted (ALL bytes are written, regardless of the values on BW

[A:D]

and BWE).

BWE

Input-

Synchronous

Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must be

asserted LOW to conduct a byte write.

CLK

Input-

Clock

Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the

burst counter when ADV is asserted LOW, during a burst operation.

Input-

Synchronous

Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with

and CE

to select/deselect the device. ADSP is ignored if CE

is HIGH. CE

is sampled only

when a new external address is loaded.

Input-

Synchronous

Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with

and CE

to select/deselect the device.CE

is sampled only when a new external address is

loaded.

Input-

Synchronous

Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with

and

to select/deselect the device. CE

is sampled only when a new external address is

loaded.Not connected for BGA. Where referenced, CE

is assumed active throughout this

document for BGA.

Input-

Asynchronous

Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When

LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as

input data pins. OE is masked during the first clock of a read cycle when emerging from a

deselected state.

B
C
D
E

G
H

P
R
T
U

DDQ

NC
NC

ADSP

DDQ

NC
NC

DDQ

CLK

NC
NC

DDQ

ADSC

ADV

MODE

BWE

CY7C1339G (128K × 32)

119-ball BGA

PRELIMINARY

CY7C1339G

Document #: 38-05520 Rev. *A

Page 4 of 17

Functional Overview

All synchronous inputs pass through input registers controlled

by the rising edge of the clock. All data outputs pass through

output registers controlled by the rising edge of the clock.

Maximum access delay from the clock rise (t

) is 2.6 ns

(250-MHz device).
The CY7C1339G supports secondary cache in systems

utilizing either a linear or interleaved burst sequence. The

interleaved burst order supports Pentium and i486

processors. The linear burst sequence is suited for processors

that utilize a linear burst sequence. The burst order is user

selectable, and is determined by sampling the MODE input.

Accesses can be initiated with either the Processor Address

Strobe (ADSP) or the Controller Address Strobe (ADSC).

Address advancement through the burst sequence is

controlled by the ADV input. A two-bit on-chip wraparound

burst counter captures the first address in a burst sequence

and automatically increments the address for the rest of the

burst access.
Byte Write operations are qualified with the Byte Write Enable

(BWE) and Byte Write Select (BW

[A:D]

) inputs. A Global Write

Enable (GW) overrides all Byte Write inputs and writes data to

all four bytes. All writes are simplified with on-chip

synchronous self-timed Write circuitry.
Three synchronous Chip Selects (CE

, CE

) and an

asynchronous Output Enable (OE) provide for easy bank

selection and output tri-state control. ADSP is ignored if CE

is HIGH.

Single Read Accesses
This access is initiated when the following conditions are

satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2)
CE

, CE

are all asserted active, and (3) the Write

signals (GW, BWE) are all deserted HIGH. ADSP is ignored if
CE

is HIGH. The address presented to the address inputs (A)

is stored into the address advancement logic and the Address

corresponding data is allowed to propagate to the input of the

Output Registers. At the rising edge of the next clock the data

is allowed to propagate through the output register and onto

the data bus within 2.6 ns (250-MHz device) if OE is active

LOW. The only exception occurs when the SRAM is emerging

from a deselected state to a selected state, its outputs are

always tri-stated during the first cycle of the access. After the

first cycle of the access, the outputs are controlled by the OE

signal. Consecutive single Read cycles are supported. Once

the SRAM is deselected at clock rise by the chip select and

either ADSP or ADSC signals, its output will tri-state immedi-

ately.
Single Write Accesses Initiated by ADSP
This access is initiated when both of the following conditions

are satisfied at clock rise: (1) ADSP is asserted LOW, and

(2) CE

, CE

are all asserted active. The address

presented to A is loaded into the address register and the

ADV

Input-

Synchronous

Advance Input signal, sampled on the rising edge of CLK, active LOW. When asserted, it

automatically increments the address in a burst cycle.

ADSP

Input-

Synchronous

Address Strobe from Processor, sampled on the rising edge of CLK, active LOW. When

asserted LOW, addresses presented to the device are captured in the address registers. A1, A0

are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is

recognized. ASDP is ignored when CE

is deasserted HIGH.

ADSC

Input-

Synchronous

Address Strobe from Controller, sampled on the rising edge of CLK, active LOW. When

asserted LOW, addresses presented to the device are captured in the address registers. A1, A0

are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is

recognized.

Input-

Asynchronous

ZZ "sleep" Input, active HIGH. When asserted HIGH places the device in a non-time-critical

"sleep" condition with data integrity preserved. For normal operation, this pin has to be LOW or

left floating. ZZ pin has an internal pull-down.

DQs

I/O-

Synchronous

Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered

by the rising edge of CLK. As outputs, they deliver the data contained in the memory location

specified by the addresses presented during the previous clock rise of the read cycle. The direction

of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs. When

HIGH, DQs are placed in a tri-state condition.

Power Supply Power supply inputs to the core of the device.

Ground

Ground for the core of the device.

DDQ

I/O Power

Supply

Power supply for the I/O circuitry.

SSQ

I/O Ground

Ground for the I/O circuitry.

MODE

Input-

Static

Selects Burst Order. When tied to GND selects linear burst sequence. When tied to V

or left

floating selects interleaved burst sequence. This is a strap pin and should remain static during

device operation. Mode Pin has an internal pull-up.

No Connects. Not internally connected to the die

Pin Definitions

(continued)

Name

I/O

Description

PRELIMINARY

CY7C1339G

Document #: 38-05520 Rev. *A

Page 5 of 17

address advancement logic while being delivered to the

memory array. The Write signals (GW, BWE, and BW

[A:D]

) and

ADV inputs are ignored during this first cycle.
ADSP-triggered Write accesses require two clock cycles to

complete. If GW is asserted LOW on the second clock rise, the

data presented to the DQs inputs is written into the corre-

sponding address location in the memory array. If GW is HIGH,

then the Write operation is controlled by BWE and BW

[A:D]

signals. The CY7C1339G provides Byte Write capability that

is described in the Write Cycle Descriptions table. Asserting

the Byte Write Enable input (BWE) with the selected Byte

Write (BW

[A:D]

) input, will selectively write to only the desired

bytes. Bytes not selected during a Byte Write operation will

remain unaltered. A synchronous self-timed Write mechanism

has been provided to simplify the Write operations.
Because the CY7C1339G is a common I/O device, the Output

Enable (OE) must be deserted HIGH before presenting data

to the DQs inputs. Doing so will tri-state the output drivers. As

a safety precaution, DQs are automatically tri-stated whenever

a Write cycle is detected, regardless of the state of OE.

Single Write Accesses Initiated by ADSC
ADSC Write accesses are initiated when the following condi-

tions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is

deserted HIGH, (3) CE

, CE

are all asserted active, and

(4) the appropriate combination of the Write inputs (GW, BWE,

and BW

[A:D]

) are asserted active to conduct a Write to the

desired byte(s). ADSC-triggered Write accesses require a

single clock cycle to complete. The address presented to A is

loaded into the address register and the address

advancement logic while being delivered to the memory array.

The ADV input is ignored during this cycle. If a global Write is

conducted, the data presented to the DQs is written into the

corresponding address location in the memory core. If a Byte

Write is conducted, only the selected bytes are written. Bytes

not selected during a Byte Write operation will remain

unaltered. A synchronous self-timed Write mechanism has

been provided to simplify the Write operations.
Because the CY7C1339G is a common I/O device, the Output

Enable (OE) must be deserted HIGH before presenting data

to the DQs inputs. Doing so will tri-state the output drivers. As

a safety precaution, DQs are automatically tri-stated whenever

a Write cycle is detected, regardless of the state of OE.

Burst Sequences
The CY7C1339G provides a two-bit wraparound counter, fed

by A1, A0, that implements either an interleaved or linear burst

sequence. The interleaved burst sequence is designed specif-

ically to support Intel Pentium applications. The linear burst

sequence is designed to support processors that follow a

linear burst sequence. The burst sequence is user selectable

through the MODE input.
Asserting ADV LOW at clock rise will automatically increment

the burst counter to the next address in the burst sequence.

Both Read and Write burst operations are supported.

Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ

places the SRAM in a power conservation "sleep" mode. Two

clock cycles are required to enter into or exit from this "sleep"

mode. While in this mode, data integrity is guaranteed.

Accesses pending when entering the "sleep" mode are not

considered valid nor is the completion of the operation

guaranteed. The device must be deselected prior to entering

the "sleep" mode. CE

, CE

, ADSP, and ADSC must

remain inactive for the duration of t

ZZREC

after the ZZ input

returns LOW.

Interleaved Burst Address Table

(MODE = Floating or V

)

First

Address

A1, A0

Second

Address

A1, A0

Third

Address

A1, A0

Fourth

Address

A1, A0

Linear Burst Address Table (MODE = GND)

First

Address

A1, A0

Second

Address

A1, A0

Third

Address

A1, A0

Fourth

Address

A1, A0

ZZ Mode Electrical Characteristics

Parameter

Description

Test Conditions

Min.

Max.

Unit

DDZZ

Snooze mode standby current

ZZ > V

0.2V

ZZS

Device operation to ZZ

ZZ > V

0.2V

CYC

ZZREC

ZZ recovery time

ZZ < 0.2V

CYC

ZZI

ZZ active to snooze current

This parameter is sampled

CYC

RZZI

ZZ Inactive to exit snooze current

This parameter is sampled

Part Number CY7C1339G