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Part Number CY7C1328F

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PRELIMINARY
256K x 18 Pipelined DCD Sync SRAM
CY7C1328F
Cypress Semiconductor Corporation
·
3901 North First Street
·
San Jose
,
CA 95134
·
408-943-2600
Document #: 38-05220 Rev. **
Revised December 19, 2002
Features
· Fully registered inputs and outputs for pipelined
operation
· Optimal for performance (Double-Cycle chip deselect,
depth expansion without wait state)
· 256K × 18-bit common I/O architecture
· 3.3V ­5% and +10% core power supply
· 2.5V or 3.3V I/O supply
· Fast clock-to-output times
-- 2.6 ns (for 250-MHz device)
-- 2.6 ns (for 225-MHz device)
-- 2.8 ns (for 200-MHz device)
-- 3.5 ns (for 166-MHz device)
-- 4.0 ns (for 133-MHz device)
-- 4.5 ns (for 100-MHz device)
· Provide high-performance 3-1-1-1 access rate
· User-selectable burst counter supporting Intel
Pentium
interleaved or linear burst sequences
· Separate processor and controller address strobes
· Synchronous self-timed writes
· Asynchronous Output Enable
· JEDEC-standard 100-pin TQFP package and pinout
· "ZZ" Sleep Mode option
Functional Description
The CY7C1328F SRAM integrates 262,144x18 SRAM cells
with advanced synchronous peripheral circuitry and a two-bit
counter for internal burst operation. All synchronous inputs are
gated by registers controlled by a positive-edge-triggered
Clock Input (CLK). The synchronous inputs include all
addresses, all data inputs, address-pipelining Chip Enable
(CE), depth-expansion Chip Enables (CE2 and CE2), Burst
Control inputs (ADSC, ADSP, and ADV), Write Enables (BW0,
BW1 and BWE), and Global Write (GW).
Asynchronous inputs include the Output Enable (OE) and
Burst Mode Control (MODE). The data outputs (Q), enabled
by OE, are also asynchronous.
Addresses and chip enables are registered with either
Address Status Processor (ADSP) or Address Status
Controller (ADSC) input pins. Subsequent burst addresses
can be internally generated as controlled by the Burst Advance
pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed Write cycle. Write cycles can be one to
two bytes wide as controlled by the write control inputs.
Individual byte write allows individual bytes to be written. BW0
controls DQ1­DQ8 and DQP1. BW1 controls DQ9­DQ16 and
DQP2. BW0 and BW1 can be active only with BWE being
LOW. GW being LOW causes all bytes to be written. Write
pass-through capability allows written data available at the
output for the immediately next Read cycle. This device also
incorporates a pipelined enable circuit for easy depth
expansion without penalizing system performance.
The CY7C1328F operates from a +3.3V core power supply
while all outputs may operate with either a +2.5 or +3.3V
supply. All inputs and outputs are JEDEC standard JESD8-5
compatible. The device is ideally suited for Pentium, 680x0,
and PowerPC
®
systems and for systems that benefit from a
wide synchronous data bus.
Selection Guide
-250
-225
-200
-166
-133
-100
Maximum Access Time
2.6
2.6
2.8
3.5
4.0
4.5
Maximum Operating Current
325
290
265
240
225
205
Maximum CMOS Standby Current
40
40
40
40
40
40
Shaded areas contain advance information.
PRELIMINARY
CY7C1328F
Document #: 38-05220 Rev. **
Page 2 of 15
Note:
1.
The Functional Block Diagram illustrates simplified device operation. See Truth Table, pin descriptions and timing diagrams for detailed information.
D
Q
D
Q
WEH#
BWE#
WEL#
GW#
CE#
CE2
CE2#
UPPER BYTE
WRITE
LOWER BYTE
WRITE
OUTPUT
REGISTER
OE#
hi byte w
r
ite
ADSP#
ADSC#
Address
Register
Binary
Counter
& Logic
CLR
A17-A2
A1-A0
ADV#
MODE
256K
x 9 x 2
S
RAM Ar
r
a
y
O
u
tput B
u
ffers
Input
Register
lo byte w
r
ite
DQ1-
DQ16,
DQP1,
DQP2
D
Q
D
Q
D
Q
ENABLE
Power Down Logic
ZZ
Functional Block Diagram--256Kx18
[1]
PRELIMINARY
CY7C1328F
Document #: 38-05220 Rev. **
Page 3 of 15
Pin Configurations
Pin Descriptions
Name
(100TQFP)
I/O
Description
A
[17:0]
Input-
Synchronous
Address Inputs used to select one of the 256K address locations. Sampled at the rising edge
of the CLK if ADSP or ADSC is active LOW, and CE
1
,
CE
2
, and
CE
3
are sampled active. A
[1:0]
feed
the two-bit counter.
BW
[1:0]
Input-
Synchronous
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM.
Sampled on the rising edge of CLK.
GW
Input-
Synchronous
Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a global
write is conducted (ALL bytes are written, regardless of the values on BW
[1:0]
and BWE).
BWE
Input-
Synchronous
Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must be
asserted LOW to conduct a byte write.
CLK
Input-
Clock
Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the burst
counter when ADV is asserted LOW, during a burst operation.
CE
1
Input-
Synchronous
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE
2
and CE
3
to select/deselect the device. ADSP is ignored if CE
1
is HIGH.
CE
2
Input-
Synchronous
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with
CE
1
and CE
3
to select/deselect the device.
CE
3
Input-
Synchronous
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE
1
and
CE
2
to select/deselect the device.
OE
Input-
Asynchronous
Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When
LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act
as input data pins. OE is masked during the first clock of a read cycle when emerging from a
deselected state.
100-pin TQFP
Top View
A10
NC
NC
V
DDQ
V
SSQ
NC
DQP1
DQ8
DQ7
V
SSQ
V
DDQ
DQ6
DQ5
V
SS
NC
V
DD
ZZ
DQ4
DQ3
V
DDQ
V
SSQ
DQ2
DQ1
NC
NC
V
SSQ
V
DDQ
NC
NC
NC
NC
NC
NC
V
DDQ
V
SSQ
NC
NC
DQ9
DQ10
V
SSQ
V
DDQ
DQ11
DQ12
V
DD
NC
V
SS
DQ13
DQ14
V
DDQ
V
SSQ
DQ15
DQ16
DQP2
NC
V
SSQ
V
DDQ
NC
NC
NC
A6
A7
CE
CE
2
NC
NC
BW
1
BW
0
CE
2
V
CC
V
SS
CL
K
GW
BW
E
OE
AD
SC
AD
SP
AD
V
A8
A9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
10
0
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
CY7C1328F
(256K x 18)
NC
A5
A4
A3
A2
A1
A0
NC
NC
V
SS
V
DD
NC
NC
A1
5
A1
4
A1
3
A1
2
A1
1
A1
6
A1
7
MO
D
E
PRELIMINARY
CY7C1328F
Document #: 38-05220 Rev. **
Page 4 of 15
ADV
Input-
Synchronous
Advance Input signal, sampled on the rising edge of CLK. When asserted, it automatically
increments the address in a burst cycle.
ADSP
Input-
Synchronous
Address Strobe from Processor, sampled on the rising edge of CLK. When asserted LOW,
A
[17:0]
is captured in the address registers. A
[1:0]
are also loaded into the burst counter. When ADSP
and ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE
1
is deasserted
HIGH.
ADSC
Input-
Synchronous
Address Strobe from Controller, sampled on the rising edge of CLK. When asserted LOW,
A
[17:0]
is captured in the address registers. A
[1:0]
are also loaded into the burst counter. When ADSP
and ADSC are both asserted, only ADSP is recognized.
ZZ
Input-
Asynchronous
ZZ "sleep" Input. This active-HIGH input places the device in a non-time-critical "sleep" condition
with data integrity preserved. For normal operation, this pin has to be LOW or left floating. ZZ pin
has an internal pull-down.
DQ
[15:0]
DP
[1:0]
I/O-
Synchronous
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered by
the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified
by A
[17:0]
during the previous clock rise of the read cycle. The direction of the pins is controlled by
OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQ
[15:0]
and DP
[1:0]
are
placed in a three-state condition.
V
DD
Power Supply Power supply inputs to the core of the device. Should be connected to 3.3V power supply.
V
SS
Ground
Ground for the core of the device. Should be connected to ground of the system.
V
DDQ
I/O Power
Supply
Power supply for the I/O circuitry. Should be connected to a 3.3V or 2.5V power supply.
V
SSQ
I/O Ground
Ground for the I/O circuitry. Should be connected to ground of the system.
MODE
Input-
Static
Selects Burst Order. When tied to GND selects linear burst sequence. When tied to V
DDQ
or left
floating selects interleaved burst sequence. This is a strap pin and should remain static during
device operation. Mode Pin has an internal pull-up.
NC
No Connects.
Pin Descriptions
(continued)
Name
(100TQFP)
I/O
Description
Burst Address Table (MODE = NC/V
CC
)
First
Address
(external)
Second
Address
(internal)
Third
Address
(internal)
Fourth
Address
(internal)
A...A00
A...A01
A...A10
A...A11
A...A01
A...A00
A...A11
A...A10
A...A10
A...A11
A...A00
A...A01
A...A11
A...A10
A...A01
A...A00
Burst Address Table (MODE = GND)
First
Address
(external)
Second
Address
(internal)
Third
Address
(internal)
Fourth
Address
(internal)
A...A00
A...A01
A...A10
A...A11
A...A01
A...A10
A...A11
A...A00
A...A10
A...A11
A...A00
A...A01
A...A11
A...A00
A...A01
A...A10
Truth Table
[2, 3, 4, 5, 6, 7, 8]
Operation
Address
Used
CE
CE2
CE2
ADSP
ADSC
ADV
WRITE
OE
CLK
DQ
Deselected Cycle, Power Down
None
H
X
X
X
L
X
X
X
L-H
High-Z
Deselected Cycle, Power Down
None
L
X
L
L
X
X
X
X
L-H
High-Z
Deselected Cycle, Power Down
None
L
H
X
L
X
X
X
X
L-H
High-Z
Deselected Cycle, Power Down
None
L
X
L
H
L
X
X
X
L-H
High-Z
Deselected Cycle, Power Down
None
L
H
X
H
L
X
X
X
L-H
High-Z
Notes:
2.
X = "Don't Care." H = logic HIGH. L = logic LOW.
WRITE = L means [BWE + BWa*BWb]*GW equals LOW. WRITE = H means [BWE + BWa*BWb]*GW equals HIGH.
3.
BWa enables write to DQa. BWb enables write to DQb.
4.
All inputs except OE must meet set-up and hold times around the rising edge (LOW to HIGH) of CLK.
5.
Suspending burst generates wait cycle.
6.
For a write operation following a read operation, OE must be HIGH before the input data required setup time plus High-Z time for OE and staying HIGH
throughout the input data hold time.
7.
This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
8.
ADSP LOW along with chip being selected always initiates a Read cycle at the L-H edge of CLK. A WRITE cycle can be performed by setting WRITE LOW
for the CLK L-H edge of the subsequent wait cycle. Refer to Write timing diagram for clarification.
PRELIMINARY
CY7C1328F
Document #: 38-05220 Rev. **
Page 5 of 15
Read Cycle, Begin Burst
External
L
L
H
L
X
X
X
L
L-H
Q
Read Cycle, Begin Burst
External
L
L
H
L
X
X
X
H
L-H
High-Z
Write Cycle, Begin Burst
External
L
L
H
H
L
X
L
X
L-H
D
Read Cycle, Begin Burst
External
L
L
H
H
L
X
H
L
L-H
Q
Read Cycle, Begin Burst
External
L
L
H
H
L
X
H
H
L-H
High-Z
Read Cycle, Continue Burst
Next
X
X
X
H
H
L
H
L
L-H
Q
Read Cycle, Continue Burst
Next
X
X
X
H
H
L
H
H
L-H
High-Z
Read Cycle, Continue Burst
Next
H
X
X
X
H
L
H
L
L-H
Q
Read Cycle, Continue Burst
Next
H
X
X
X
H
L
H
H
L-H
High-Z
Write Cycle, Continue Burst
Next
X
X
X
H
H
L
L
X
L-H
D
Write Cycle, Continue Burst
Next
H
X
X
X
H
L
L
X
L-H
D
Read Cycle, Suspend Burst
Current
X
X
X
H
H
H
H
L
L-H
Q
Read Cycle, Suspend Burst
Current
X
X
X
H
H
H
H
H
L-H
High-Z
Read Cycle, Suspend Burst
Current
H
X
X
X
H
H
H
L
L-H
Q
Read Cycle, Suspend Burst
Current
H
X
X
X
H
H
H
H
L-H
High-Z
Write Cycle, Suspend Burst
Current
X
X
X
H
H
H
L
X
L-H
D
Write Cycle, Suspend Burst
Current
H
X
X
X
H
H
L
X
L-H
D
Truth Table
(continued)
[2, 3, 4, 5, 6, 7, 8]
Operation
Address
Used
CE
CE2
CE2
ADSP
ADSC
ADV
WRITE
OE
CLK
DQ
Partial Truth Table for Read/Write
Function
GW
BWE
BW1
BW2
BW3
BW4
Read
H
H
X
X
X
X
Read
H
L
H
H
H
H
Write one byte
H
L
L
H
H
H
Write all bytes
H
L
L
L
L
L
Write all bytes
L
X
X
X
X
X