PRELIMINARY
512K x 24 Static RAM
CY7C1012AV25
Cypress Semiconductor Corporation
·
3901 North First Street
·
San Jose
,
CA 95134
·
408-943-2600
Document #: 38-05337 Rev. **
Revised January 27, 2003
Features
· High speed
-- t
AA
= 8, 10, 12 ns
· Low active power
-- 1080 mW (max.)
· Operating voltages of 2.5 ± 0.2V
· 1.5V data retention
· Automatic power-down when deselected
· TTL-compatible inputs and outputs
· Easy memory expansion with CE
0
, CE
1
and CE
2
features
Functional Description
The CY7C1012AV25 is a high-performance CMOS static
RAM organized as 512K words by 24 bits. Each data byte is
separately controlled by the individual chip selects (CE
0
, CE
1
,
CE
2
). CE
0
controls the data on the I/O
0
I/O
7
, while CE
1
controls the data on I/O
8
I/O
15
, and CE
2
controls the data on
the data pins I/O
16
I/O
23
. This device has an automatic
power-down feature that significantly reduces power
consumption when deselected.
Writing the data bytes into the SRAM is accomplished when
the chip select controlling that byte is LOW and the write
enable input (WE) input is LOW. Data on the respective
input/output (I/O) pins is then written into the location specified
on the address pins (A
0
A
16
). Asserting all of the chip selects
LOW and write enable LOW will write all 24 bits of data into
the SRAM. Output enable (OE) is ignored while in WRITE
mode.
Data bytes can also be individually read from the device.
Reading a byte is accomplished when the chip select
controlling that byte is LOW and write enable (WE) HIGH while
output enable (OE) remains LOW. Under these conditions, the
contents of the memory location specified on the address pins
will appear on the specified data input/output (I/O) pins.
Asserting all the chip selects LOW will read all 24 bits of data
from the SRAM.
The 24 I/O pins (I/O
0
I/O
23
) are placed in a high-impedance
state when all the chip selects are HIGH or when the output
enable (OE) is HIGH during a READ mode. For further details,
refer to the truth table of this data sheet.
The CY7C1012AV25 is available in a standard 119-ball BGA.
Selection Guide
-8
-10
-12
Unit
Maximum Access Time
8
10
12
ns
Maximum Operating Current
Commercial
300
275
260
mA
Industrial
300
275
260
Maximum CMOS Standby Current
Commercial/Industrial
50
50
50
mA
Functional Block Diagram
1
5
1
6
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
COLUMN
DECODER
R
O
W
D
E
C
O
D
E
R
S
E
N
S
E
A
M
P
S
INPUT BUFFER
512K x 24
ARRAY
A
0
A
1
2
A
1
4
A
1
3
A A A
1
7
A
1
8
A
1
0
A
1
1
4096 x 4096
I/O
0
I/O
7
OE
I/O
8
I/O
15
CE
0
, CE
1
, CE
2
WE
A
9
I/O
16
I/O
23
CONTROL LOGIC
PRELIMINARY
CY7C1012AV25
Document #: 38-05337 Rev. **
Page 2 of 9
Pin Configurations
119 BGA
Top View
1
2
3
4
5
6
7
A
NC
A
A
A
A
A
NC
B
NC
A
A
CE0
A
A
NC
C
I/O
12
NC
CE1
NC
CE2
NC
I/O
0
D
I/O
13
V
DD
V
SS
V
SS
V
SS
V
DD
I/O
1
E
I/O
14
V
SS
V
DD
V
SS
V
DD
V
SS
I/O
2
F
I/O
15
V
DD
V
SS
V
SS
V
SS
V
DD
I/O
3
G
I/O
16
V
SS
V
DD
V
SS
V
DD
V
SS
I/O
4
H
I/O
17
V
DD
V
SS
V
SS
V
SS
V
DD
I/O
5
J
NC
V
SS
V
DD
V
SS
V
DD
V
SS
DNU
K
I/O
18
V
DD
V
SS
V
SS
V
SS
V
DD
I/O
6
L
I/O
19
V
SS
V
DD
V
SS
V
DD
V
SS
I/O
7
M
I/O
20
V
DD
V
SS
V
SS
V
SS
V
DD
I/O
8
N
I/O
21
V
SS
V
DD
V
SS
V
DD
V
SS
I/O
9
P
I/O
22
V
DD
V
SS
V
SS
V
SS
V
DD
I/O
10
R
I/O
23
A
NC
NC
NC
A
I/O
11
T
NC
A
A
WE
A
A
NC
U
NC
A
A
OE
A
A
NC
PRELIMINARY
CY7C1012AV25
Document #: 38-05337 Rev. **
Page 3 of 9
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature .................................65
°
C to +150
°
C
Ambient Temperature with
Power Applied.............................................55
°
C to +125
°
C
Supply Voltage on V
CC
to Relative GND
[1]
.... 0.5V to +3.6V
DC Voltage Applied to Outputs
in High-Z State
[1]
....................................0.5V to V
CC
+ 0.5V
DC Input Voltage
[1]
................................ 0.5V to V
CC
+ 0.5V
Current into Outputs (LOW)......................................... 20 mA
Operating Range
Range
Ambient
Temperature
V
CC
Commercial
0
°
C to +70
°
C
2.5V
±
0.2V
Industrial
40
°
C to +85
°
C
DC Electrical Characteristics
Over the Operating Range
Parameter
Description
Test Conditions
[2]
-8
-10
-12
Unit
Min. Max. Min. Max. Min. Max.
V
OH
Output HIGH Voltage
V
CC
= Min.,
I
OH
= 1.0 mA
2.0
2.0
2.0
V
V
OL
Output LOW Voltage
V
CC
= Min.,
I
OL
= 1.0 mA
0.4
0.4
0.4
V
V
IH
Input HIGH Voltage
2.0
V
CC
+ 0.3
2.0
V
CC
+ 0.3
2.0
V
CC
+ 0.3
V
V
IL
[1]
Input LOW Voltage
0.3
0.8
0.3
0.8
0.3
0.8
V
I
IX
Input Load Current
GND < V
I
< V
CC
1
+1
1
+1
1
+1
µ
A
I
OZ
Output Leakage Current GND < V
OUT
< V
CC
, Output Disabled
1
+1
1
+1
1
+1
µ
A
I
CC
V
CC
Operating
Supply Current
V
CC
= Max.,
f = f
MAX
= 1/t
RC
Commercial
300
275
260
mA
Industrial
300
275
260
mA
I
SB1
Automatic CE
Power-down Current
--TTL Inputs
Max. V
CC
, CE > V
IH
V
IN
> V
IH
or
V
IN
< V
IL
, f = f
MAX
100
100
100
mA
I
SB2
Automatic CE
Power-down Current
--CMOS Inputs
Max. V
CC
,
CE > V
CC
0.2V,
V
IN
> V
CC
0.2V,
or V
IN
< 0.2V, f = 0
Commercial
/Industrial
50
50
50
mA
Capacitance
[3]
Parameter
Description
Test Conditions
Max.
Unit
C
IN
Input Capacitance
T
A
= 25
°
C, f = 1 MHz, V
CC
= 2.5V
8
pF
C
OUT
I/O Capacitance
10
pF
Notes:
1.
V
IL
(min.) = 2.0V for pulse durations of less than 20 ns.
2.
CE refers to a combination of CE
0
, CE
1
, and CE
2
. CE is active LOW when all three of these signals are active LOW at the same time.
3.
Tested initially and after any design or process changes that may affect these parameters.
PRELIMINARY
CY7C1012AV25
Document #: 38-05337 Rev. **
Page 4 of 9
AC Test Loads and Waveforms
[4]
90%
10%
2.5V
GND
90%
10%
ALL INPUT PULSES
2.5V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
(a)
(b)
R1 317
R2
351
Rise time > 1 V/ns
Fall time:
> 1 V/ns
(c)
OUTPUT
50
Z
0
= 50
V
TH
= V
DD
/2
30 pF*
* Capacitive Load consists of all compo-
nents of the test environment.
AC Switching Characteristics
Over the Operating Range
[5]
Parameter
Description
-8
-10
-12
Unit
Min.
Max.
Min.
Max.
Min.
Max.
Read Cycle
t
power
[6]
V
CC
(typical) to the first access
1
1
1
ms
t
RC
Read Cycle Time
8
10
12
ns
t
AA
Address to Data Valid
8
10
12
ns
t
OHA
Data Hold from Address Change
3
3
3
ns
t
ACE
CE
1
, CE
2
, and CE
3
LOW to Data Valid
8
10
12
ns
t
DOE
OE LOW to Data Valid
5
5
6
ns
t
LZOE
OE LOW to Low Z
[7]
1
1
1
ns
t
HZOE
OE HIGH to High Z
[7]
5
5
6
ns
t
LZCE
CE
1
, CE
2
, and CE
3
LOW to Low Z
[7]
3
3
3
ns
t
HZCE
CE
1
, CE
2
, or CE
3
HIGH to High Z
[7]
5
5
6
ns
t
PU
CE
1
, CE
2
, and CE
3
LOW to Power-up
[8]
0
0
0
ns
t
PD
CE
1
, CE
2
, or CE
3
HIGH to Power-down
[8]
8
10
12
ns
t
DBE
Byte Enable to Data Valid
5
5
6
ns
t
LZBE
Byte Enable to Low Z
[7]
1
1
1
ns
t
HZBE
Byte Disable to High Z
[7]
5
5
6
ns
Write Cycle
[9, 10]
t
WC
Write Cycle Time
8
10
12
ns
t
SCE
CE
1
, CE
2
, and CE
3
LOW to Write End
6
7
8
ns
Notes:
4.
Valid SRAM operation does not occur until the power supplies have reached the minimum operating V
DD
(2.3V). As soon as 1ms (T
power
) after reaching the
minimum operating V
DD
, normal SRAM operation can begin including reduction in V
DD
to the data retention (V
CCDR
, 1.5V) voltage.
5.
Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.1V, input pulse levels of 0 to 2.3V, and output loading of the specified
I
OL
/I
OH
and transmission line loads. Test conditions for the read cycle use output loading as shown in part a) of the AC test loads, unless specified otherwise.
6.
This part has a voltage regulator which steps down the voltage from 3V to 2V internally. t
power
time has to be provided initially before a read/write operation
is started.
7.
t
HZOE
, t
HZCE
, t
HZWE
, t
HZBE
, and t
LZOE
, t
LZCE
, t
LZWE
, t
LZBE
are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured
±
200 mV from steady-state voltage.
8.
These parameters are guaranteed by design and are not tested.
9.
The internal write time of the memory is defined by the overlap of CE
1
, CE
2
, and CE
3
LOW and WE LOW. The chip enables must be active and WE must be
LOW to initiate a write, and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the
leading edge of the signal that terminates the write.
10. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of t
HZWE
and t
SD
.
PRELIMINARY
CY7C1012AV25
Document #: 38-05337 Rev. **
Page 5 of 9
t
AW
Address Set-Up to Write End
6
7
8
ns
t
HA
Address Hold from Write End
0
0
0
ns
t
SA
Address Set-Up to Write Start
0
0
0
ns
t
PWE
WE Pulse Width
6
7
8
ns
t
SD
Data Set-Up to Write End
5
5.5
6
ns
t
HD
Data Hold from Write End
0
0
0
ns
t
LZWE
WE HIGH to Low Z
[7]
3
3
3
ns
t
HZWE
WE LOW to High Z
[7]
5
5
6
ns
t
BW
Byte Enable to End of Write
6
7
8
ns
Data Retention Waveform
AC Switching Characteristics
Over the Operating Range (continued)
[5]
Parameter
Description
-8
-10
-12
Unit
Min.
Max.
Min.
Max.
Min.
Max.
2.3V
2.3V
t
CDR
V
DR
> 1.5V
DATA RETENTION MODE
t
R
CE
V
CC
Switching Waveforms
Read Cycle No. 1
[11, 12]
Read Cycle No. 2 (OE Controlled)
[2, 12, 13]
Notes:
11. Device is continuously selected. OE, CE = V
IL
.
12. WE is HIGH for read cycle.
13. Address valid prior to or coincident with CE transition LOW.
PREVIOUS DATA VALID
DATA VALID
t
RC
t
AA
t
OHA
ADDRESS
DATA OUT
50%
50%
DATA VALID
t
RC
t
ACE
t
DOE
t
LZOE
t
LZCE
t
PU
HIGH IMPEDANCE
t
HZOE
t
HZCE
t
PD
HIGH
OE
CE
I
CC
I
SB
IMPEDANCE
ADDRESS
DATA OUT
V
CC
SUPPLY
CURRENT
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