Copyright

Cirrus Logic, Inc. 2005

http://www.cirrus.com

CS5510/11/12/13

16-bit and 20-bit, 8-pin

ADC

Features

Delta-sigma Analog-to-digital Converter

Linearity Error: 0.0015% FS
Noise-free Resolution: Up to 17 Bits

Differential Bipolar Analog Inputs
V

REF

Input Range from 250 mV to 5 V

50/60 Hz Simultaneous Rejection
(CS5510/12)
16 to 326 Sps Output Word Rate
On-chip Oscillator (CS5511/13)
Power Supply Configurations:

V+ = 5 V, V- = 0 V
Multiple Dual-supply Arrangements

Low Power Consumption

Normal Mode, 2.5 mW
Sleep Mode, 10

Low-cost, Compact, 8-pin Package
Lead-free Device Package Options

General Description

The CS5510/11/12/13 are low-cost, easy-to-use,

an-

alog-to-digital converters (ADCs) which use charge-
balance techniques to achieve 16-bit (CS5510/11) and
20-bit (CS5512/13) performance. The ADCs are avail-
able in a space-efficient, 8-pin SOIC package and are
optimized for measuring signals in weigh scale, process
control, and other industrial applications.

To accommodate these applications, the ADCs include
a fourth-order

modulator and a digital filter. When

configured with an external master clock of 32.768 kHz,
the filter in the CS5510/12 provides better than 80 dB of
simultaneous 50 and 60 Hz line rejection, and outputs
conversion words at 53.5 Sps. The CS5511/13 include
an on-chip oscillator which eliminates the need for an ex-
ternal clock source.

Low-power, flexible supply configurations, compact pi-
nout, and ease of use make these products ideal
solutions for cost-conscience and space-constrained
applications.

ORDERING INFORMATION

See

page 23

V+

AIN+

AIN-

VREF

Clock

Gen.

~0.8X

Differential

4th-order

Delta-sigma

Modulator

Digital Filter

Control

Output

SCLK

SDO

Logic

Oscillator

(CS5511/13 only)

V-

(CS5510/12 only)

AUG `05

DS337F3

CS5510/11/12/13

DS337F3

TABLE OF CONTENTS

1. CHARACTERISTICS AND SPECIFICATIONS ........................................................................ 4

ANALOG CHARACTERISTICS ................................................................................................ 4
DIGITAL CHARACTERISTICS ................................................................................................. 5
DYNAMIC CHARACTERISTICS .............................................................................................. 6
ABSOLUTE MAXIMUM RATINGS ........................................................................................... 6
SWITCHING CHARACTERISTICS - CS5510/12 ..................................................................... 7
SWITCHING CHARACTERISTICS - CS5511/13 ..................................................................... 8

2. GENERAL DESCRIPTION ..................................................................................................... 10

2.1 Analog Input ..................................................................................................................... 10

2.1.1 Analog Input Model ............................................................................................. 10

2.2 Voltage Reference Input .................................................................................................. 10

2.2.1 Voltage Reference Input Model ........................................................................... 11

2.3 Power Supply Arrangements ........................................................................................... 11

2.3.1 Digital Logic Levels ............................................................................................. 11

2.4 Clock Generator ............................................................................................................... 14

2.4.1 External Clock Source for CS5510/12 ................................................................ 14
2.4.2 Internal Oscillator for CS5511/13 ........................................................................ 14

2.5 Performing Conversions .................................................................................................. 15

2.5.1 Reading Conversions - CS5510/12 ..................................................................... 16
2.5.2 Reading Conversions - CS5511/13 ..................................................................... 16
2.5.3 Output Coding ..................................................................................................... 17
2.5.4 Digital Filter ......................................................................................................... 18
2.5.5 Multiplexed Applications ...................................................................................... 19

2.6 Digital Off-chip System Calibration .................................................................................. 20
2.7 Power Consumption, Sleep and Reset ............................................................................ 20
2.8 PCB Layout ...................................................................................................................... 20

3. PIN DESCRIPTIONS .............................................................................................................. 21
4. SPECIFICATION DEFINITIONS ............................................................................................. 22
5. ORDERING INFORMATION ................................................................................................... 23
6. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION ............................ 23
7. REVISION HISTORY ............................................................................................................. 23
8. PACKAGE DIMENSIONS ....................................................................................................... 24

Contacting Cirrus Logic Support

For all product questions and inquiries contact a Cirrus Logic Sales Representative.
To find the one nearest to you go to

www.cirrus.com

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CS5510/11/12/13

DS337F3

LIST OF FIGURES

Figure 1. SDO Read Timing CS5510/12 (Not to Scale).................................................................. 9
Figure 2. SDO Read Timing CS5511/13 (Not to Scale).................................................................. 9
Figure 3. Input models for AIN+ and AIN- pins. ............................................................................ 10
Figure 4. CS5512/13 Measured Noise-Free Bits vs. VREF. ......................................................... 11
Figure 5. Input model for VREF pin............................................................................................... 11
Figure 6. CS5510/11/12/13 Configured with a +5.0 V Analog Supply. ......................................... 12
Figure 7. CS5510/11/12/13 Configured with ą2.5 V Analog Supplies........................................... 12
Figure 8. CS5510/11/12/13 Configured with V+ = +3.3 V and V- = -1.7 V;

or V+ = +3.0 V and V- = -2.0 V. .................................................................................... 13

Figure 9. CS and SCLK Digital Input Levels. ................................................................................ 14
Figure 10. SDO Digital Output Levels. .......................................................................................... 14
Figure 11. Serial Port Output Drive Logic. .................................................................................... 14
Figure 12. External (CMOS Compatible) Clock Source. ............................................................... 15
Figure 13. Using a Microcontroller as a Clock Source. ................................................................. 15
Figure 14. Typical Linearity Error for CS5510............................................................................... 15
Figure 15. Typical Linearity Error for CS5512............................................................................... 15
Figure 16. Data Word Timing for the CS5510............................................................................... 16
Figure 17. Data Word Timing for the CS5511............................................................................... 17
Figure 18. Data Word Timing for the CS5512............................................................................... 17
Figure 19. Data Word Timing for the CS5513............................................................................... 17
Figure 20. Digital Filter Response................................................................................................. 19

LIST OF TABLES

Table 1. CS5512/13 Output Conversion Data Register Description (Flags + 20 bits). ................. 18
Table 2. CS5510/11 Output Conversion Data Register Description (Flags + 16 bits). ................. 18
Table 3. CS5510/11/12/13 Output Coding. ................................................................................... 18
Table 4. Digital Filter Response at 32.768 kHz............................................................................. 19
Table 5. Device Ordering Information ........................................................................................... 23

CS5510/11/12/13

DS337F3

CHARACTERISTICS AND SPECIFICATIONS

ANALOG CHARACTERISTICS

= 25° C; V+ = 5 V ą5%; V- = 0 V; VREF = 2.5 V (relative to V-);

CS5510/12, SCLK = 32.768 kHz; CS5511/13, f

osc

= 64 kHz ą32 kHz; OWR (Output Word Rate) = 53.5 Sps for

CS5510/12; OWR = 107 Sps ą 50% for CS5511/13)
(See Note 1.)

Notes: 1. Specifications guaranteed by design, characterization, and/or test.

2. Specification applies to the device only and does not include any effects by external parasitic

thermocouples.

3. Drift over specified temperature range after power-up at 25

4. Wideband noise aliased into the baseband. Referred to the input. Typical values shown for 25° C.
5. For peak-to-peak noise multiply by 6.6.
6. See the section of the data sheet which discusses Analog Input Models.
7. For CS5511/13, OWR = 107 Sps ą 50%.

Specifications are subject to change without notice.

Parameter

Min

Typ

Max

Unit

Accuracy
Linearity Error (CS5510/11)

ą0.0015

ą0.003

% FS

Linearity Error (CS5512/13)

ą0.0007

ą0.0015

% FS

No Missing Codes (CS5510/11)

Bits

No Missing Codes (CS5512/13)

Bits

Bipolar Offset (CS5510/11)

(Note 2)

ą3

ą7

LSB

Bipolar Offset (CS5512/13)

(Note 2)

ą40

ą100

LSB

Offset Drift Over Temperature

(Notes 2 and 3)

nV/°C

Gain Drift Over Temperature

(Note 3)

ppm/°C

Analog Input
Common Mode + Signal on AIN+ or AIN-

Dual Supply

V-

V+

Input Range (Bipolar)

|(AIN+ - AIN-)/(VREF - V-)|

% VREF

Common Mode Rejection

dc
50, 60Hz (CS5510/12)

-
-

120
120

-
-

dB
dB

Input Capacitance

CVF Current

AIN+, AIN-

(Note 6)

Typical Noise (Notes 4, 5 and 7)

Output Word Rate (Hz)

-3 dB Filter Frequency (Hz)

Noise (ľV RMS)

53.5

12.5

7.5

CS5510/11/12/13

DS337F3

ANALOG CHARACTERISTICS

(Continued)

Notes: 8. VREF is referenced to V- and must be less than or equal to V+.

9. Due to current through the CS pin, I

V+

and I

V-

may not always be the same value.

10. All outputs unloaded. All inputs CMOS levels (> (V+ - 0.6 V) or < (V- + 0.6 V)).

11. CS must be inactive (logic high) during sleep to meet this power specification.

DIGITAL CHARACTERISTICS

= 25° C; V

= 5 V

5%; V- = 0 V) (See Notes 1 and 12.)

Notes: 12. All measurements performed under static conditions.

13. V

is 0.5 (V+ - V-) + 0.6 V + V-.

14. The CS signal provides the sink current path for the SDO pin when CS is low. The external drive logic

to CS, therefore, must be able to handle the logic-low current drive levels for all devices attached to
SDO. The voltage specified for SDO is relative to CS

Low

. See Section 2.3.1, "Digital Logic Levels" and

Figure 11 for more details.

Parameter

Min

Typ

Max

Unit

Voltage Reference Input
Range

{(VREF) - (V-)}

(Note 8) 0.250

2.5

(V+) - (V-)

Input Capacitance

CVF current

Power Supplies
Supply Voltages

{(V+) - (V-)}

4.75

5.25

DC Power Supply Currents

(Note 9)

V+

CS5510

CS5511

CS5512
CS5513

V-

CS5510

CS5511

CS5512
CS5513

-
-
-
-
-
-
-
-

275
290
360
385
275
290
360
385

360
380
470
500
360
380
470
500

ľA
ľA
ľA
ľA
ľA
ľA
ľA
ľA

Power Consumption

(Note 10)

CS5510

CS5511

CS5512
CS5513

Sleep

(Note 11)

-
-
-
-
-

1.4
1.5
1.8
1.9

1.9
2.0
2.5
2.7

mW
mW
mW
mW

ľW

Power Supply Rejection

dc Positive Supply
dc Negative Supply

-
-

85
85

-
-

dB
dB

Parameter

Symbol

Min

Typ

Max

Unit

High-Level Input Voltage:

CS and SCLK

V+ - 0.45

Low-Level Input Voltage:

(Note 13)

SCLK

Low

-
-

V
V

Input Current:

(Note 14)

1.0

High-Level Output Voltage:

SDO, I

source

= 5.0mA

(V+) - 0.6

Low-Level Output Voltage:

(Note 14) SDO, I

sink

= 1.0mA

(

Low

) + 0.6

Input Leakage Current

SCLK

ą0.015

ą10

ľA

3-State Leakage Current

SCLK

ą10

ľA

CS5510/11/12/13

DS337F3

DYNAMIC CHARACTERISTICS

ABSOLUTE MAXIMUM RATINGS

(V- = 0 V) (See Note 15.)

Notes: 15. All voltages with respect to V-.

16. V+ and V- must satisfy 0.0V

{(V+) - (V-)}

+6.0 V.

17. Applies to all pins including continuous overvoltage conditions at the analog input (AIN) pins.
18. Transient current of up to 100 mA will not cause SCR latch-up. Maximum input current for a power

supply pin is ą50 mA.

19. Total power dissipation, including all input currents and output currents.

WARNING: Operation at or beyond these limits may result in permanent damage to the device.

Normal operation is not guaranteed at these extremes.

Parameter

Symbol

Ratio

Units

Modulator Sampling Frequency

CS5510/12

CS5511/13

SCLK/4

osc

Hz
Hz

Output Word Rate

CS5510/12

CS5511/13

OWR
OWR

SCLK/612

osc

/612

Sps
Sps

Filter Settling Time to 1/2 LSB (Full Scale Step)

4/OWR

Parameter

Symbol

Min

Typ

Max

Unit

DC Power Supplies

(Note 16)

Positive

Negative

V+

V-

-0.3
-6.0

-
-

+6.0
+0.3

V
V

Input Current, Any Pin Except Supplies

(Notes 17 and 18)

ą10

Output Current

OUT

ą25

Package Power Dissipation

(Note 19)

PDN

400

Analog Input Voltage

AIN pins

INA

(V-)+(-0.3)

(V+)+0.3

Digital Input Voltage

IND

(

V-

)+(-0.3)

(V+)+0.3

Ambient Operating Temperature

-40

+85

°C

Storage Temperature

stg

-65

+150

°C

CS5510/11/12/13

DS337F3

SWITCHING CHARACTERISTICS - CS5510/12

= 25° C; V+ = 5 V ą5%; V- = 0 V; Input Levels: Logic 0 = 0 V, Logic 1 = V+; C

= 50 pF)

Notes: 20. Device parameters are specified with 32.768 kHz clock; however, clocks up to 130 kHz (CS5510) or

200 kHz (CS5512) can be used for increased throughput. Higher clock rates will result in degraded
linearity specifications, as shown in Figures 14 and 15.

21. Specified using 10% and 90% points on waveform of interest. Output loaded with 50 pF.
22. On the CS5510/12, the serial clock input (SCLK) provides the master clock to operate the converter as

well as the serial data clock used to read conversion data. If SCLK is held high (logic 1) for t

SLP

or longer,

the CS5510/12 enters sleep. To exit from sleep mode, SCLK must be held low (logic 0) for t

WAKE

longer.

Parameter

Symbol

Min

Typ

Max

Unit

Master Clock Timing
Master Clock Frequency (CS5510)

(Note 20) SCLK

32.768

130

kHz

Master Clock Frequency (CS5512)

(Note 20) SCLK

32.768

200

kHz

Master Clock Duty Cycle

Rise Times

(Note 21)

CSB

SCLK

SDO

rise

-
-
-

-
-

1.0

ľs
ľs
ns

Fall Times

(Note 21)

CSB

SCLK

SDO

fall

-
-
-

-
-

1.0

ľs
ľs
ns

Serial Port Timing
Serial Clock Frequency (CS5510)

(Note 22) SCLK

32.768

130

kHz

Serial Clock Frequency (CS5512)

(Note 22) SCLK

32.768

200

kHz

SCLK High to Enter Sleep

(Note 22)

SLP

200

2000

ľs

SCLK Low to Exit Sleep

(Note 22) t

WAKE

ľs

Serial Clock

Pulse Width High

Pulse Width Low

2
2

-
-

60
60

ľs
ľs

SDO Read Timing

to Data Valid

150

SCLK Falling to New Data Bit

150

Rising to SDO Hi-Z

150

Falling to SCLK Rising

200

CS5510/11/12/13

DS337F3

SWITCHING CHARACTERISTICS - CS5511/13

= 25° C; V+ = 5 V ą5%; V- = 0 V; Input Levels: Logic 0 = 0 V, Logic 1 = V+; C

= 50 pF)

Notes: 23. The internal oscillator in the CS5511/13 provides the master clock for performing conversions. Data is

retrieved from the serial port using the SCLK input pin.

24. The minimum SCLK rate for the CS5511/13 assumes that SCLK is logic 0 when idle. When data is being

read from the ADC, SCLK must be burst at a minimum rate of 10 kHz and with a minimum of a 10
percent duty cycle. Rates slower than this can potentially put the ADC into sleep as the sleep mode is
entered after SCLK is logic 1 for t

SLP

time.

25. On the CS5511/13, the serial clock (SCLK) is used to transfer data from the CS5511/13. If SCLK is held

high (logic 1) for t

SLP

or longer, the CS5511/13 enters sleep mode. To exit from sleep mode, SCLK must

be held low (logic 0) for t

WAKE

or longer.

26. Specified using 10% and 90% points on waveform of interest. Output loaded with 50 pF.

Parameter

Symbol

Min

Typ

Max

Unit

Internal Oscillator Timing
Internal Oscillator Frequency

(Note 23)

osc

100

kHz

Internal Oscillator Drift Over Temperature

-0.02

%/°C

Serial Port Timing
Serial Clock Frequency

(Note 24) SCLK

MHz

SCLK High to Enter Sleep

(Notes 24 and 25)

SLP

200

2000

ľs

SCLK Low to Exit Sleep

(Notes 24 and 25) t

WAKE

ľs

Rise Times

(Note 26)

CSB

SCLK

SDO

rise

-
-
-

-
-

1.0

ľs
ľs
ns

Fall Times

(Note 26)

CSB

SCLK

SDO

fall

-
-
-

-
-

1.0

ľs
ľs
ns

Serial Clock

Pulse Width High

Pulse Width Low

200
200

-
-

ns
ns

SDO Read Timing

to Data Valid

150

SCLK Falling to New Data Bit

150

Rising to SDO Hi-Z

150

Falling to SCLK Rising

200

CS5510/11/12/13

DS337F3

2. GENERAL DESCRIPTION

The CS5510/11/12/13 are low-cost, easy-to-use,

analog-to-digital converters (ADCs) which use
charge balance techniques to achieve 16-bit
(CS5510/11) and 20-bit (CS5512/13) perfor-
mance. The ADCs are available in a space-effi-
cient, 8-pin, SOIC package and are optimized for
measuring signals in weigh scale, process control,
and other industrial applications.

To accommodate these applications, the ADCs in-
clude a fourth-order

modulator and a digital fil-

ter. When configured with an external master clock
of 32.768 kHz, the filter in the CS5510/12 provides
better than 80 dB of simultaneous 50 and 60 Hz
line rejection, and outputs conversion words at
53.5 Sps. The CS5511/13 include an on-chip oscil-
lator which eliminates the need for an external
clock source.

The CS5510/11/12/13 ADCs are designed to oper-
ate from a single +5 V supply or a variety dual-sup-
ply configurations and are optimized to digitize
bipolar signals in industrial applications.

To achieve low cost, the CS5510/11/12/13 family
of converters have no on-chip calibration features.
The CS5510/11/12/13 offer very low offset drift,
low gain drift, and excellent linearity.

2.1

Analog Input

The CS5510/11/12/13 provides a differential input
span of approximately ą(0.80 ą 0.08) times the dif-

ferential voltage reference (VREF - V-). This trans-
lates to typically ą4.0 V fully differential when the
reference voltage between VREF and V- is 5 V,
and typically ą2.0 V fully differential at 2.5 V.

Note:

When a smaller reference voltage is used,
the resulting code widths are smaller. Since
the output codes exhibit more changing
codes for a fixed amount of noise, the
converter appears noisier.

2.1.1

Analog Input Model

Figure 3 illustrates the input model for the AIN
pins. The model includes a coarse/fine charge
buffer which reduces the dynamic current de-
mands from the signal source. The buffer is de-
signed to accommodate rail-to-rail (common-mode
plus signal) input voltages. Typical CVF (sampling)
current is about 10 nA. Application Note 30,

"Switched-capacitor A/D Input Structures"

, details

various input architectures.

2.2

Voltage Reference Input

The voltage between the VREF and V- pins of the
converter determines the voltage reference for the
converter. This voltage can be as low as 250 mV,
or as great as (V+) - (V-). The VREF pin can be
connected directly to the V+ pin. This will establish
a voltage reference equal to (V+) - (V-) for the con-
verter. The effective resolution of the part (noise-
free bits for a single sample with no averaging) will
vary with VREF. Figure 4 shows how the VREF
voltage affects the noise-free resolution of the

AIN

Coarse

Fine

f = 32.768 kHz

2 5 mV

f V

12 p F

Figure 3. Input models for AIN+ and AIN- pins.

CS5510/11/12/13

DS337F3

CS5512/13. The CS5510/11 follow the same
curve, but are limited to 16 bits of resolution. Note
that the reference voltage should not be estab-
lished prior to having the supply voltages on the V+
and V- pins.

2.2.1

Voltage Reference Input Model

Figure 5 illustrates the input model for the VREF
pin. It includes a coarse/fine charge buffer which
reduces the dynamic current demand of the exter-

nal reference. Typical CVF (sampling) current is
about 6 nA (See Figure 5).

The nominal input span of the converter is defined
to be a bipolar span equal to ą(VREF - V-)*(0.80
ą0.08).

2.3

Power Supply Arrangements

The CS5510/11/12/13 are designed to operate
from single or dual supplies. Figure 6 illustrates the
CS5510/11/12/13 connected with a single +5 V
supply to measure differential inputs relative to a
common mode of 2.5 V. Figure 7 illustrates the
CS5510/11/12/13 connected with ą2.5 V analog
supplies to measure ground-referenced, bipolar
signals. It is not necessary that the dual supples on
the ADCs be balanced, however, they must sum to
five volts. Figure 8 illustrates the ADCs configured
with V+ = +3.3 V and V- = -1.7 V, accommodating
a +3.3 V digital supply.

2.3.1

Digital Logic Levels

The many power supply configurations available in
the CS5510/11/12/13 allow for a wide range of dig-
ital logic levels. The logic-high input and output lev-
els are determined by the V+ pin. The logic-low
output on SDO is referenced to and driven by the
current logic-low voltage on CS. Since the
CS5510/11/12/13 do not include a dedicated

0.5

1.5

2.5

3.5

4.5

VREF (V)

Effective Bits

Figure 4. CS5512/13 Measured Noise-Free Bits vs.

VREF.

VREF

7 p F

2 5 mV

o s

f V

f = 32.768 kHz

Coarse

Fine

Figure 5. Input model for VREF pin.

CS5510/11/12/13

DS337F3

ground pin, CS

Low

defines the logic-low level for

the digital interface. Figures 9 and 10 illustrate the
threshold levels of the CS5510/11/12/13 serial in-
terface (CS, SCLK, and SDO).

To accommodate opto-isolators, the SCLK input is
designed with a Schmitt-trigger to allow an opto-
isolator with slower rise and fall times to directly
drive the pin. Additionally, SDO is capable of sink-
ing up to 1 mA or sourcing up to 5 mA to directly
drive an opto-isolator LED. SDO will have less than
a 600 mV loss in the drive voltage when sinking or
sourcing its current. As shown in Figure 11, the CS
signal provides the sink current path for the SDO
pin when its voltage is low (i.e. the voltage speci-
fied for SDO is relative to CS

Low

.).

2.4

Clock Generator

The CS5510/12 and CS5511/13 provide distinct
modes for generating the master clock for the
ADCs. The CS5510/12 uses the SCLK input pin as
its operating clock. The CS5511/13 has an on-chip
oscillator that provides its master clock. The SCLK
pin on the CS5511/13 is used only to read data and
to put the part into sleep mode.

2.4.1

External Clock Source for
CS5510/12

The user must provide an external (CMOS com-
patible) clock to the CS5510/12. The clock is input
to SCLK where it is then divided down to provide
the master clock for the ADC. The output word rate
(OWR) for the CS5510/12 is derived from the
SCLK, and is equal to SCLK/612. Figure 12 illus-
trates an external 32.768-kHz, CMOS-compatible
clock oscillator that a user might consider.

Another clock generation option is to use a micro-
controller. Some microcontrollers have dedicated
timer/counter circuitry which can generate a clock
signal on an output pin with no software overhead.
Such a microcontroller circuit is shown in
Figure 13.

Note that the CS5510 can operate with an exter-
nal, CMOS-compatible clock at frequencies up to
130 kHz, and the CS5512 can operate with an ex-
ternal clock of up to 200 kHz with a maximum
22 ns of jitter. Linearity performance is degraded
slightly with higher clock speeds, as shown in
Figures 14 and 15. The noise performance of the
parts, however, is not affected by higher clock
speeds.

2.4.2

Internal Oscillator for CS5511/13

The CS5511/13 includes an on-chip oscillator. This
oscillator provides the master clock for the
CS5511/13 and oscillates at 64 kHz ą32 kHz. The

Figure 9. CS and SCLK Digital Input Levels.

V+

V-

V = 0.5 (

- V-) + 0.6

V-

LOW

- 0.45V

V+

V +

V+

V-

V = V+ - 0.6V

V = CS

+ 0.6V

LOW

Figure 10. SDO Digital Output Levels.

V+

Output Drive Logic

5 mA

1 mA

SDO (from SDO
Control Logic)

CS (to CS
Control Logic)

Max Source

Max Sink

Figure 11. Serial Port Output Drive Logic.

CS5510/11/12/13

DS337F3

output word rate (OWR) for the CS5511/13 is de-
rived from the internal oscillator, and is equal to
f

osc

/612. Due to the part-to-part variances in the

oscillator frequency, the OWR of the CS5511/13
can vary between 53 Sps and 159 Sps.

2.5

Performing Conversions

After power and a clock source are established to
the CS5510/11/12/13, the ADCs begin performing
conversions. The three sections that follow explain
how to read conversion data from each ADC, and

decode the conversion word into the respective
flag and data bits. Keep in mind that in the
CS5510/12, SCLK provides the external clock
source for the converter. Data is clocked from the
CS5510/12 at the rate set by the external clock
source (typically 32.768 kHz). The CS5511/13 pro-
vides an on-chip oscillator for the master clock. In
the CS5511/13, SCLK is asynchronous to the on-
chip oscillator and can be clocked at a rate up to
2 MHz.

VD+ = 2.5 V to 5.25 V

To SCLK

Fairchild NC7SU04
or 1/6 74HCU04

22 pF

47 pF

32.768 kHz

49.9 K

10 M

Figure 12. External (CMOS Compatible) Clock

Counter/Timer

SCLK

SDO

CS5510/12

ľC

Figure 13. Using a Microcontroller as a Clock

0.0005

0.001

0.0015

0.002

0.0025

0.003

0.0035

0.004

110

130

SCLK (kHz)

ear

y Err

r
(

)

OWR = SCLK

612

Figure 14. Typical Linearity Error for CS5510.

0.0005

0.001

0.0015

0.002

0.0025

0.003

20 40 60 80 100 120 140 160 180 200

SCLK (kHz)

Line

arity

Error (%FS)

OWR = SCLK

612

Figure 15. Typical Linearity Error for CS5512.

CS5510/11/12/13

DS337F3

2.5.1

Reading Conversions -
CS5510/12

After power-up, the CS5510/12 will begin convert-
ing once a clock source is applied to the SCLK pin.
When a conversion has completed, and there is
new data in the output register, the SDO line will
fall to a logic-low level if CS is also at a logic-low
state (SDO will always be high-impedance when
CS is high). If CS is low at the end of the conver-
sion cycle, SDO will fall on the rising edge of an
SCLK. After SCLK falls, the next SCLK cycle (high,
then low) will begin clocking out the data. The first
data bit therefore, is 1-

SCLK cycles wide. Twen-

ty-four SCLK cycles (after the initial high-low tran-
sition) are needed to retrieve the conversion word
from the device (see Figures 16 and 17). The data
bits can be read on the rising edge of SCLK, and
the next data bit is output to SDO on the falling
edge of SCLK. Once the entire data word has been
read, SDO will return to a logic-high state until
there is a new conversion word available. If CS is
at a logic-high at the end of the conversion cycle,
the data will not be shifted out of the part until CS
is brought to a logic-low state during the next con-
version cycle. If a new conversion becomes avail-
able while the current data is being read, the data
register will not be updated, and the new conver-
sion word will be lost. The user need not read every
conversion. If the user chooses not to read a con-
version, CS should remain at a logic-high state for
the duration of the conversion cycle. Note that if
CS goes to a logic-high state during a read, the
current conversion data will be lost and replaced

by a new conversion word when the new conver-
sion data is available.

2.5.2

Reading Conversions -
CS5511/13

After power-up, the CS5511/13 begins converting
and updating the output register. When there is
new data in the output register (at the end of a con-
version cycle) the SDO line will fall to a logic-low
level if CS is also at a logic-low state (SDO will al-
ways be high-impedance when CS is high). Twen-
ty-four SCLK cycles are needed to retrieve the
conversion word from the device (see Figures 18
and 19). The data bits can be read on the rising
edge of SCLK, and the next data bit is output to
SDO on the falling edge of SCLK. Once the entire
data word has been read, SDO will return to a log-
ic-high state until there is a new conversion word
available. If new conversions become available
while the current data is being read, the data regis-
ter will not be updated, and the new conversions
will be lost. The user need not read every conver-
sion. If the user chooses not to read a conversion
after SDO falls, SDO will rise seventeen oscillator
clock cycles (of the internal oscillator) before the
next conversion word is available and then fall
again to signal that the conversion is complete.
Note that if a conversion word is not read before
the next conversion word is ready, or if CS goes to
a logic-high state during a read, the current conver-
sion data will be lost and replaced by a new con-
version word when the new conversion data is
available.

S D O

S C L K

D a ta T im e

2 4 S C L K s

M S B

L S B

C S

O F

O D

Figure 16. Data Word Timing for the CS5510.

CS5510/11/12/13

DS337F3

2.5.3

Output Coding

As shown in Tables 1 and 2, the CS5510/11/12/13
present output conversions as 24-bit conversion
words. The first bit of the conversion word indi-
cates that a conversion is done through SDO fall-
ing from a logic high to a logic low level. The first
and the fourth bits output will always be zero. The
second and third bits are error flags, representing
an overflow or oscillation condition. In the
CS5510/11, there are four more bits of zero, and
the remaining 16 bits are the conversion data, out-
put MSB first (Table 2). In the CS5512/13, the final

20 bits are the conversion data, which is output
MSB first (Table 1).

Bits D22-D21 are the two flag bits. The OF (Over-
range Flag) bit is set to a logic 1 any time the input
signal is more positive than positive full scale, or
more negative than negative full scale. It is cleared
back to logic 0 whenever a conversion word occurs
which is not overranged. The OD (Oscillation De-
tect) bit is set to a logic 1 any time that an oscillatory
condition is detected in the modulator. This does
not occur under normal operating conditions, but
may occur whenever the input to the converter is ex-

S D O

S C L K

D a ta T im e

2 4 S C L K s

M S B

L S B

C S

O F

O D

Figure 17. Data Word Timing for the CS5511.

S D O

S C L K

D a ta T im e

2 4 S C L K s

M S B

L S B

C S

O F

O D

Figure 18. Data Word Timing for the CS5512.

S D O

S C L K

D a ta T im e

2 4 S C L K s

M S B

L S B

C S

O F

O D

Figure 19. Data Word Timing for the CS5513.

CS5510/11/12/13

DS337F3

cessively overranged. If the OD bit is set, the con-
version data bits can be completely erroneous. The
OD flag bit will be cleared to logic 0 four output
words after the modulator becomes stable again.
The OD flag can occur independent of OF with a
spike on the input. Both flag bits should be tested
if any overrange condition occurs.

Table 3 illustrates the output coding for the
CS5510/11/12/13. Conversions are output as
two's complement values representing bipolar in-
put signals.

2.5.4

Digital Filter

The CS5510/11/12/13 have a modified Sinc

digi-

tal filter that provides CLK/612 Hz conversion rates

(CLK represents SCLK for the CS5510/12 and the
internal oscillator for the CS5511/13). The filters
are optimized to yield better than 80 dB rejection
between 47 Hz to 63 Hz (i.e. 80 dB minimum rejec-
tion for both 50 Hz and 60 Hz) when the master
clock is 32.768 kHz. The filter has a response as
shown in Figure 20. Table 4 shows the filter re-
sponse for frequencies from 38 Hz to 71 Hz. Note
that the response of the CS5511/13 will be similar,
but the frequencies scale with the on-chip oscilla-
tor's frequency, which can be from 32 kHz to
96 kHz (i.e. conversion rates can vary between
53 Sps to 159 Sps). Further note that after initial
power up, or after returning from sleep mode, the
filter requires four conversion cycles to produce a

D23

D22

D21

D20

D19

D18

D17

D16

D15

D14

D13

D12

MSB

D11

D10

LSB

Table 1. CS5512/13 Output Conversion Data Register Description (Flags + 20 bits).

D23

D22

D21

D20

D19

D18

D17

D16

D15

D14

D13

D12

MSB

D11

D10

LSB

Table 2. CS5510/11 Output Conversion Data Register Description (Flags + 16 bits).

Note: VFS in the table equals the voltage between AIN+ and AIN-. See text about error flags

under overrange conditions.

Table 3. CS5510/11/12/13 Output Coding.

Bipolar Input Voltage

Two's Complement (20-Bit)

Two's Complement (16-Bit)

>(VFS-1.5 LSB)

7FFFF

7FFF

VFS-1.5 LSB

7FFFF

-----

7FFFE

7FFF

-----

7FFE

-0.5 LSB

00000

-----

FFFFF

0000

-----

FFFF

-VFS+0.5 LSB

80001

-----

80000

8001

-----

8000

CS5510/11/12/13

DS337F3

valid conversion due to the modified Sinc

filter

characteristics.

2.5.5

Multiplexed Applications

The settling performance of the CS5510/11/12/13
in multiplexed applications is determined by the
Sinc

filter. To settle, a step input requires 4 full

conversion cycles after the analog input has
switched. In this case, the throughput is reduced
by a factor of four as the first three conversions af-
ter the step is applied will not be fully settled.

If the application does not require the maximum
throughput possible from the ADC, the multiplexer
can be switched at any time. In this case, the sys-
tem must wait for at least five conversion cycles for
a fully-settled result from the ADC.

If maximum throughput is required in a multiplexed
application, the multiplexer must be switched at the
correct time during the data collection process. For
maximum throughput with the CS5510/12, switch-
ing of a multiplexer should occur 595 SCLK cycles
after SDO falls. For maximum throughput with the
CS5511/13, switching of a multiplexer should oc-
cur on the rising edge of SDO during a conversion
in which the data word is not read. The conversion
data that is immediately available when SDO falls
again is valid, and represents the analog input from
the previous multiplexer setting. The next three
conversions from the part will be unsettled values,
and the fourth conversion will represent a fully-set-
tled result from the new multiplexer setting. The
multiplexer should be switched again at the appro-

-140

-120

-100

-80

-60

-40

-20

100

120

Frequency (Hz)

a
gni

t
u
d
e
(

d
B

)

47 Hz

63 Hz

CS5510/12
SCLK = 32.768 kHz

Figure 20. Digital Filter Response.

Frequency

(Hz)

Rejection

(dB)

Frequency

(Hz)

Rejection

(dB)

Frequency

(Hz)

Rejection

(dB)

Frequency

(Hz)

Rejection

(dB)

109

105

104

Table 4. Digital Filter Response at 32.768 kHz.

CS5510/11/12/13

DS337F3

priate time during the third conversion cycle to en-
sure the maximum possible throughput.

2.6

Digital Off-chip System
Calibration

The CS5510/11/12/13 exhibit excellent linearity
with low offset and gain drift, without the need for
calibration. If precision voltage measurements are
required by the system, however, software-based
offset and gain calibration can be performed by the
system.

To perform a software offset calibration, the "zero-
point" of the system should be established by ap-
plying an input to the system equal to zero. Then,
the user can obtain a conversion and store it in
memory as the system's zero point (ZP). This num-
ber can then be used as the zero point for any sub-
sequent conversion words. In the 20-bit devices
(CS5512 and CS5513), multiple conversions can
be averaged to arrive at a more accurate offset val-
ue. In the 16-bit devices (CS5510 and CS5511),
averaging may not be meaningful, because the
noise will be below the size of one LSB when using
nominal voltages for VREF (2.5 V).

A software gain calibration can be performed by
bringing the system to a known calibration Voltage
value (Vcal) and acquiring a conversion (note that
Vcal should be low enough to compensate for the
possible gain error of the ADC). Multiple conver-
sions can be averaged at this point to improve the
accuracy of the calibration. The code obtained
from this conversion is the real value (Cr) of the
calibration Voltage input, and will differ from the
ideal value. The ideal value for this conversion (Ci)

will be equivalent to: 0x7FFF*Vcal/(0.80*Vref) for
the CS5510/11, and 0x7FFFF*Vcal/(0.80*Vref) for
the CS5512/13. The gain error (GE) is equal to: (Cr
- ZP)/Ci. To correct for both offset and gain error in
subsequent conversions, subtract the offset error,
and then divide by the gain error.

2.7

Power Consumption, Sleep and
Reset

The CS5510/11/12/13 accommodates two power
modes:

normal

and

sleep

. The normal mode is the

default mode and is entered after power is estab-
lished to the ADC. In normal mode, the ADCs typ-
ically consumes 2.5 mW. Sleep is entered when
the user leaves SCLK high for at least 200

ľs. The

ADCs are guaranteed to be in sleep after SCLK is
high (logic 1) for 2 ms. The sleep mode reduces
the consumed power to less than 10

ľW when CS

is high (logic 1). If CS is low (logic 0) at this time,
the SDO drive logic will still be active, and the con-
sumed sleep power will be greater. To exit sleep
and return to normal mode, the user must return
SCLK low for at least 10

ľs. After a sleep is exited,

the ADCs reset all their internal logic, including
their digital filters, and begin performing conver-
sions. Since the filters are reset, the first three con-
version after returning to normal mode will not be
fully settled.

2.8

PCB Layout

The CS5510/11/12/13 should be placed entirely
over the analog ground. Place the analog-digital
plane split immediately adjacent to the digital pins
of the chip.

CS5510/11/12/13

DS337F3

3. PIN DESCRIPTIONS

Control Pins and Serial Data I/O

CS - Chip Select, Pin 4

CS is a dual function pin, which determines the state of SDO, as well as the digital logic-low output

level. When CS is low, SDO will be active. When high, the SDO pin will output a high-impedance state.

The logic-low level of SDO will match the active-low voltage on CS.

SDO - Serial Data Output, Pin 8

SDO is the serial data output. It will output a high-impedance state if CS = 1. The logic-low level of SDO

will match the active-low voltage on CS.

SCLK - Serial Clock Input, Pin 5

SCLK is the serial bit-clock which controls the shifting of data from the ADCs. This input goes through a

Schmitt trigger to allow for slow rise and fall time signals. If held high, the device will enter sleep mode.

In the CS5510/12, this input is also used as a master clock source which determines conversion speeds

and throughput. In the CS5511/13, SCLK is only used to read the conversion data and put the part in

sleep mode.

Measurement and Reference Inputs

AIN+, AIN- - Differential Analog Input, Pins 2, 3

Differential input pins into the device

VREF - Voltage Reference Input, Pin 1

Input Voltage which establishes the voltage reference, with respect to V-, for the on-chip modulator

Power Supply Connections

V+ - Positive Power, Pin 6

Positive supply voltage

V- - Negative Supply, Pin 7

Negative supply voltage

3
4

SDO

V-

V+

SCLK

AIN-

AIN+

VREF

Part Number CS5510

Document Outline