Preliminary Product Information

This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.

Cirrus Logic, Inc. 1999

Cirrus Logic, Inc.
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.crystal.com

CS4954
CS4955

NTSC/PAL Digital Video Encoder

Features

Six DACs providing simultaneous composite,
S-video, and RGB or Component YUV
outputs

Programmable DAC output currents for low
imped-ance (37.5

) and high impedance

(150

) loads.

Multi-standard support for NTSC-M, NTSC-
JAPAN, PAL (B, D, G, H, I, M, N,
Combination N)

ITU R.BT656 input mode supporting
EAV/SAV codes and CCIR601 Master/Slave
input modes

Programmable HSYNC and VSYNC timing

Multistandard Teletext (Europe, NABTS,
WST) support

VBI encoding support

Wide-Screen Signaling (WSS) support, EIA-J
CPX1204

NTSC closed caption encoder with interrupt

CS4955 supports Macrovision copy
protection Version 7

Host interface configurable
for parallel or I

compatible operation

On-chip voltage reference
generator

+3.3 V or +5 V operation,
CMOS, low-power modes,
tri-state DACs

Description

The CS4954/5 provides full conversion from digital video
formats YCbCr or YUV into NTSC and PAL Composite,
Y/C (S-video) and RGB, or YUV analog video. Input for-
mats can be 27 MHz 8-bit YUV, 8-bit YCbCr, or ITU
R.BT656 with support for EAV/SAV codes. Video output
can be formatted to be compatible with NTSC-M, NTSC-
J, PAL-B,D,G,H,I,M,N, and Combination N systems.
Closed Caption is supported in NTSC. Teletext is sup-
ported for NTSC and PAL.

Six 10-bit DACs provide two channels for an S-Video
output port, one or two composite video outputs, and
three RGB or YUV outputs. Two-times oversampling re-
duces the output filter requirements and guarantees no
DAC-related modulation components within the speci-
fied bandwidth of any of the supported video standards.

Parallel or high-speed I

C compatible control interfaces are

provided for flexibility in system design. The parallel interface
doubles as a general purpose I/O port when the CS4954/5 is
in I

C mode to help conserve valuable board area.

ORDERING INFORMATION

CS4954-CQ

48-pin TQFP

CS4955-CQ

48-pin TQFP

APR `99

DS278PP4

CLK

ISET

DGND

SCL

SDA

PDAT[7:0]

ADDR

XTAL_OUT

VD[7:0]

HSYNC

VSYNC

FIELD

INT

RESET

C Interface

Host

Parallel

Interface

Color Sub-carrier Synthesizer

Video Formatter

Control

Registers

Chroma Modulate

Chroma Amplifier

Output

Interpolate

LPF

Burst Insert

Chroma Interpolate

LPF

Luma Interpolate

Luma Amplifier

Sync Insert

U,V

Video Timing

Generator

TEST

Current

Reference

Voltage

Reference

VREF

DAC

CVBS

DAC

10-Bit

DAC

VAA

XTAL_IN

Teletext
Encoder

TTXRQ

TTXDAT

YCbCr to RBG

DAC

10-Bit

RGB

Color Space

Converter

CS4954 CS4955

DS278PP4

TABLE OF CONTENTS

CHARACTERISTICS AND SPECIFICATIONS ..................................................................5
AC & DC PARAMETRIC SPECIFICATIONS ......................................................................5
RECOMMENDED OPERATING CONDITIONS ..................................................................... 5
DC CHARACTERISTICS ....................................................................................................5
AC CHARACTERISTIC .......................................................................................................7
TIMING CHARACTERISTICS .............................................................................................8

ADDITIONAL CS4954/5 FEATURES ...............................................................................10

CS4954 INTRODUCTION .................................................................................................10

FUNCTIONAL DESCRIPTION .........................................................................................10
4.1.

Video Timing Generator .........................................................................................10

4.2.

Video Input Formatter .............................................................................................11

4.3.

Color Subcarrier Synthesizer ..................................................................................11

4.4.

Chroma Path ..........................................................................................................11

4.5.

Luma Path ..............................................................................................................12

4.6.

RGB Path and Component YUV Path ....................................................................12

4.7.

Digital to Analog Converters ...................................................................................12

4.8.

Voltage Reference ..................................................................................................13

4.9.

Current Reference ..................................................................................................13

4.10. Host Interface .........................................................................................................13
4.11. Closed Caption Services ........................................................................................13
4.12. Teletext Services ....................................................................................................14
4.13. Wide-Screen Signaling Support and CGMS ...........................................................14
4.14. VBI Encoding ..........................................................................................................14
4.15. Control Registers ....................................................................................................14
4.16. Testability ...............................................................................................................14

OPERATIONAL DESCRIPTION .......................................................................................14
5.1.

Reset Hierarchy ......................................................................................................14

5.2.

Video Timing ...........................................................................................................15
5.2.1. Slave Mode Input Interface ..........................................................................15
5.2.2. Master Mode Input Interface ........................................................................15
5.2.3. Vertical Timing .............................................................................................16
5.2.4. Horizontal Timing .........................................................................................16
5.2.5. NTSC Interlaced ..........................................................................................16
5.2.6. PAL Interlaced .............................................................................................16
5.2.7. Progressive Scan .........................................................................................17
5.2.8. NTSC Progressive Scan ..............................................................................17
5.2.9. PAL Progressive Scan .................................................................................18

5.3.

ITU-R.BT656 ..........................................................................................................18

5.4.

Digital Video Input Modes .......................................................................................21

5.5.

Multi-standard Output Format Modes .....................................................................21

5.6.

Subcarrier Generation ............................................................................................21

5.7.

Subcarrier Compensation .......................................................................................21

5.8.

Closed Caption Insertion ........................................................................................22

5.9.

Programmable H-sync and V-sync .........................................................................22

5.10. Wide Screen Signaling (WSS) and CGMS .............................................................23

Contacting Cirrus Logic Support

For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:
http://www.cirrus.com/corporate/contacts/

Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product infor-
mation describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information
contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of
any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights
of third parties. This document is the property of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets. No part of
this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or
otherwise) without the prior written consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or disk may be printed for use by the user. However, no
part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical,
photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture
or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing
in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trade-
marks and service marks can be found at http://www.cirrus.com.

CS4954 CS4955

DS278PP4

5.11. Teletext Support ..................................................................................................... 23
5.12. Color Bar Generator ............................................................................................... 25
5.13. VBI encoding .......................................................................................................... 25
5.14. Super White/Super Black support .......................................................................... 26
5.15. Interrupts ................................................................................................................ 26
5.16. General Purpose I/O Port ....................................................................................... 26

FILTER RESPONSES ...................................................................................................... 27

ANALOG .......................................................................................................................... 30
7.1.

Analog Timing ........................................................................................................ 30

7.2.

VREF ...................................................................................................................... 30

7.3.

ISET ....................................................................................................................... 30

7.4.

DACs ...................................................................................................................... 30
7.4.1. Luminance DAC .......................................................................................... 30
7.4.2. Chrominance DAC ...................................................................................... 30
7.4.3. CVBS DAC .................................................................................................. 31
7.4.4. Red DAC ..................................................................................................... 31
7.4.5. Green DAC .................................................................................................. 31
7.4.6. Blue DAC ..................................................................................................... 31

PROGRAMMING .............................................................................................................. 32
8.1.

Host Control Interface ............................................................................................ 32
8.1.1. I

C Interface ................................................................................................ 32

8.1.2. 8-bit Parallel Interface ................................................................................. 33

8.2.

Register Description ............................................................................................... 34
8.2.1. Control Registers ......................................................................................... 34

BOARD DESIGN AND LAYOUT CONSIDERATIONS .................................................... 50
9.1.

Power and Ground Planes ..................................................................................... 50

9.2.

Power Supply Decoupling ...................................................................................... 50

9.3.

Digital Interconnect ................................................................................................ 50

9.4.

Analog Interconnect ............................................................................................... 50

9.5.

Analog Output Protection ....................................................................................... 51

9.6.

ESD Protection ....................................................................................................... 51

9.7.

External DAC Output Filter ..................................................................................... 51

10. PIN DESCRIPTION ......................................................................................................... 53
11. PACKAGE DRAWING ...................................................................................................... 55

CS4954 CS4955

DS278PP4

TABLE OF FIGURES

Video Pixel Data and Control Port Timing .........................................................................7

C Host Port Timing ..........................................................................................................8

Reset Timing ......................................................................................................................9

ITU R.BT601 Input Slave Mode Horizontal Timing ..........................................................15

ITU R.BT601 Input Master Mode Horizontal Timing ........................................................15

Vertical Timing .................................................................................................................17

NTSC Video Interlaced Timing ........................................................................................18

PAL Video Interlaced Timing ...........................................................................................19

NTSC Video Non-Interlaced Progressive Scan Timing ...................................................20

10. PAL Video Non-Interlaced Progressive Scan Timing ......................................................20
11. CCIR656 Input Mode Timing ...........................................................................................21
12. Teletext Timing (Pulsation Mode) ....................................................................................24
13. Teletext Timing (Window Mode) ......................................................................................24
14. 1.3 Mhz Chrominance low-pass filter transfer characteristic ...........................................27
15. 1.3 Mhz Chrominance low-pass filter transfer characterstic (passband) .........................27
16. 650 kHz Chrominance low-pass filter transfer characteristic ...........................................27
17. 650 kHz Chrominance low-pass filter transfer characteristic (passband) ........................27
18. Chrominance output interpolation filter transfer characteristic (passband) ......................28
19. Luminance interpolation filter transfer characteristic .......................................................28
20. Luminance interpolation filter transfer characterstic (passband) .....................................28
21. Chrominance interpolation filter transfer characteristic for RGB datapath .......................28
22. Chroma Interpolator for RGB Datapath when rgb_bw=1 (Reduced Bandwidth) .............29
23. Chroma Interpolator for RGB Datapath when rgb_bw=1 (Reduced Bandwidth) .............29
24. Chroma Interpolator for RGB Datapath when rgb_bw=0 -3 dB .......................................29
25. Chroma Interpolator for RGB Datapath when rgb_bw=0 (Full Scale) ..............................29
26. I

C Protocol .....................................................................................................................32

27. 8-bit Parallel Host Port Timing: Read-Write/Write-Read Cycle ........................................33
28. 8-bit Parallel Host Port Timing: Address Read Cycle ......................................................33
29. 8-bit Parallel Host Port Timing: Address Write Cycle .......................................................34
30. External Low Pass Filter C

should be chosen so that C

= C

+ C

cable

.........................51

31. Typical Connection Diagram ............................................................................................52

CS4954 CS4955

DS278PP4

1. CHARACTERISTICS AND SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

AC & DC PARAMETRIC SPECIFICATIONS

(AGND,DGND = 0 V, all voltages with respect to 0 V)

WARNING: Operating beyond these limits can result in permanent damage to the device. Normal operation is not

guaranteed at these extremes.

RECOMMENDED OPERATING CONDITIONS

(AGND,DGND = 0 V, all voltages with respect to 0 V.)

Note:

Operation outside the ranges is not recommended.

DC CHARACTERISTICS

= 25° C; VAA, VDD = 5 V; GNDA, GNDD = 0 V.)

Parameter

Symbol

Min

Max

Units

Power Supply

VAA/VDD

-0.3

6.0

Input Current Per Pin (Except Supply Pins)

-10

Output Current Per Pin (Except Supply Pins)

-50

+50

Analog Input Voltage

-0.3

VAA + 0.3

Digital Input Voltage

-0.3

VDD + 0.3

Ambient Temperature Power Applied

-55

+ 125

°C

Storage Temperature

-65

+ 150

°C

Parameter

Symbol

Min

Typ

Max

Units

Power Supplies: Digital Analog

VAA/VDD

3.15
4.75

3.3
5.0

3.45
5.25

Operating Ambient Temperature

+ 25

+ 70

°C

Parameter

Symbol

Min

Typ Max Units

Digital Inputs

High level Input Voltage
V [7:0], PDAT [7:0], Hsync/Vsync/Field/CLKIN

VIH

2.2

VDD+0.3

High Level Input Voltage I

VIH

0.7 VDD

Low level Input Voltage All Inputs

-0.3

0.8

Input Leakage Current

-10

+10

Digital Outputs

High Level Output Voltage lo = -4 mA

VOH

2.4

VDD

Low level Output Voltage lo = 4 mA

VOL

0.4

Low Level Output Voltage SDA pin only, lo = 6mA

VOL

0.4

Output Leakage Current High -Z Digital Outputs

-10

+ 10

CS4954 CS4955

DS278PP4

DC CHARACTERISTICS

(Continued)

Notes: 1. Values are by characterization only

2. Output current levels with ISET = 4 K

, VREF = 1.232 V.

3. DACs are set to low impedance mode

4. DACs are set to high impedance mode

5. Times for black-to-white-level and white-to-black-level transitions.

6. Low-Z - 3 dacs on

7. High-Z - 6 dacs on

Parameter

Symbol

Min

Typ Max Units

Analog Outputs

Full Scale Output Current CVBS/Y/C/R/G/B

(Notes 1, 2, 3)

32.9

34.7

36.5

Full Scale Output Current CVBS/Y/C/R/G/B

(Notes 1, 2, 4)

8.22

8.68

9.13

LSB Current CVBS/Y/C/R/G/B

(Notes 1, 2, 3)

32.2

33.9

35.7

LSB Current CVBS/Y/C/R/G/B

(Notes 1, 2, 4)

8.04

8.48

8.92

DAC-to DAC Matching

(Note 1)

MAT

Output Compliance

(Note 1)

VOC

+ 1.4

Output Impedance

(Note 1)

ROUT

Output Capacitance

(Note 1)

COUT

DAC Output Delay

(Note 1)

ODEL

DAC Rise/Fall Time

(Note 1, 5)

TRF

2.5

Voltage Reference

Reference Voltage Output

VOV

1.170

1.232

1.294

Reference Input Current

(Note 1)

UVC

Power Supply

Supply Voltage

VAA, VDD

3.15
4.75

3.3
5.0

3.45
5.25

Digital Supply Current

IAA1

Analog Supply

Low-Z

(Note 6)

IAA2

100

Analog Supply

High-Z

(Note 7)

IAA3

Power Supply Rejection Ratio

PSRR

0.02

0.05

%/%

Static Performance

DAC Resolution

(Note 1)

Bits

Differential Non-Linearity

(Note 1)

DNL

-1

+ 0.5

+ 1

LSB

Integral Non-Linearity

(Note 1)

INL

- 2

+ 1

+ 2

LSB

Dynamic Performance

Differential Gain

(Note 1)

Differential Phase

(Note 1)

+ 0. 5

+ 2

Hue Accuracy

(Note 1)

Signal to Noise Ratio

SNR

Saturation Accuracy

(Note 1)

SAT

CS4954 CS4955

DS278PP4

ADDITIONAL CS4954/5 FEATURES

Five programmable DAC output combinations,
including YUV and second composite

Optional progressive scan @ MPEG2 field rates

Stable color subcarrier for MPEG2 systems

General purpose input and output pins

Individual DAC power-down capability

On-chip color bar generator

Supports RS170A and ITU R.BT601 compos-
ite output timing

HSYNC and VSYNC output in ITU R.BT656
mode

Teletext encoding selectable on two composite
and S-video signals

Programmable saturation, SCH Phase, hue,
brightness and contrast

Device power-down capability

Super White and Super Black support

CS4954 INTRODUCTION

The CS4954/5 is a complete multi-standard digital
video encoder implemented in current CMOS tech-
nology. The device can operate at 5 V as well as at
3.3 V. ITU R.BT601- or ITU R.BT656-compliant
digital video input is converted into NTSC-M,
NTSC-J, PAL-B, PAL-D, PAL-G, PAL-H, PAL-I,
PAL-M, PAL-N, or PAL-N Argentina-compatible
analog video. The CS4954/5 is designed to con-
nect, without glue logic, to MPEG1 and MPEG2
digital video decoders.

Two 10-bit DAC outputs provide high quality S-
Video analog output while another 10-bit DAC si-
multaneously generates composite analog video. In
addition, there are three more DACs to provide si-
multaneous analog RGB or analog YUV outputs.
The CS4954/5 will accept 8-bit YCbCr or 8-bit
YUV input data.

The CS4954/5 is completely configured and con-
trolled via an 8-bit host interface port or an I

compatible serial interface. This host port provides
access and control of all CS4954/5 options and fea-
tures, such as closed caption insertion, interrupts,
etc.

In order to lower overall system costs, the
CS4954/5 provides an internal voltage reference
that eliminates the requirement for an external, dis-
crete, three-pin voltage reference.

In ISO MPEG-2 system configurations, the
CS4954/5 can be augmented with a common color-
burst crystal to provide a stable color subcarrier
given an unstable 27 MHz clock input. The use of
the crystal is optional, but the facility to connect
one is provided for MPEG-2 environments in
which the system clock frequency variability is too
wide for accurate color sub-carrier generation.

FUNCTIONAL DESCRIPTION

In the following subsections, the functions of the
CS4954/5 will be described. The descriptions refer
to the device elements shown in the block diagram
on the cover page.

4.1.

Video Timing Generator

All timing generation is accomplished via a
27 MHz input applied to the CLK pin. The
CS4954/5 can also accept a signal from an optional
color burst crystal on the XTAL_IN &
XTAL_OUT pins. See the section, Color Subcarri-
er Synthesizer, for further details.

The Video Timing Generator is responsible for or-
chestrating most of the other modules in the device.
It operates in harmony with external sync input
timing, or it can provide external sync timing out-
puts. It automatically disables color burst on appro-
priate scan lines and automatically generates
serration and equalization pulses on appropriate
scan lines.

CS4954 CS4955

DS278PP4

The CS4954/5 is designed to function as a video
timing master or video timing slave. In both Master
and Slave Modes, all timing is sampled and assert-
ed with the rising edge of the CLK pin.

In most cases, the CS4954/5 will serve as the video
timing master. HSYNC, VSYNC, and FIELD are
configured as outputs in Master Mode. HSYNC or
FIELD can also be defined as a composite blanking
output signal in Master Mode. In Master Mode, the
timing of HSYNC, VSYNC, FIELD and Compos-
ite Blank (CB) signals is programmable. Exact hor-
izontal and vertical display timing is addressed in
the Operational Description section.

In Slave Mode, HSYNC and VSYNC are typically
configured as input pins and are used to initialize
independent vertical and horizontal timing genera-
tors upon their respective falling edges. HSYNC
and VSYNC timing must conform to the ITU-
R BT.601 specifications.

The CS4954/5 also provides a ITU R.BT656 Slave
Mode in which the video input stream contains
EAV and SAV codes. In this case, proper HSYNC
and VSYNC timing are extracted automatically
without any inputs other than the V [7:0]. ITU
R.BT656 input data is sampled with the leading
edge of CLK.

In addition, it is also possible to output HSYNC
and VSYNC signals during CCIR-656 Slave
Mode.

4.2.

Video Input Formatter

The Video Input Formatter translates YCbCr input
data into YUV information, when necessary, and
splits the luma and chroma information for filter-
ing, scaling, and modulation.

4.3.

Color Subcarrier Synthesizer

The subcarrier synthesizer is a digital frequency
synthesizer that produces the appropriate subcarri-
er frequency for NTSC or PAL. The CS4954/5
generates the color burst frequency based on the

CLK input (27 MHz). Color burst accuracy and
stability are limited by the accuracy of the 27 MHz
input. If the frequency varies, then the color burst
frequency will also vary accordingly.

For environments in which the CLK input varies or
jitters unacceptably, a local crystal frequency refer-
ence can be used on the XTAL_IN and
XTAL_OUT pins. In this instance, the input CLK is
continuously compared with the external crystal ref-
erence input and the internal timing of the CS4954/5
is automatically adjusted so that the color burst fre-
quency remains within tolerance.

Controls are provided for phase adjustment of the
burst to permit color adjustment and phase com-
pensation. Chroma hue control is provided by the
CS4954/5 via a 10-bit Hue Control Register
(HUE_LSB and H_MSB). Burst amplitude control
is also made available to the host via the 8-bit burst
amplitude register (SC_AMP).

4.4.

Chroma Path

The Video Input Formatter delivers 4:2:2 YUV
outputs into separate chroma and luma data paths.
The chroma path will be discussed here.

The chroma output of the Video Input Formatter is
directed to a chroma low-pass 19-tap FIR filter.
The filter bandwidth is selected (or the filter can be
bypassed) via the CONTROL_1 Register. The
passband of the filter is either 650 KHz or 1.3 MHz
and the passband ripple is less than or equal to
0.05 dB. The stopband for the 1.3 MHz selection
begins at 3 MHz with an attenuation of greater than
35 dB. The stopband for the 650 KHz selection be-
gins around 1.1 MHz with an attenuation of greater
than 20 dB.

The output of the chroma low-pass filter is connect-
ed to the chroma interpolation filter in which up-
sampling from 4:2:2 to 4:4:4 is accomplished.
Following the interpolation filter, the U and V
chroma signals pass through two independent vari-
able gain amplifiers in which the chroma amplitude

CS4954 CS4955

DS278PP4

can be varied via the U_AMP and V_AMP 8-bit
host addressable registers.

The U and V chroma signals are fed to a quadrature
modulator in which they are combined with the
output from the subcarrier synthesizer to produce
the proper modulated chrominance signal.

The chroma then is interpolated by a factor of two
in order to operate the output DACs at twice the
pixel rate. The interpolated filters enable running
the DACs at twice the pixel rate and this helps re-
duce the sinx/x roll-off for higher frequencies and
reduces the complexity of the external analog low
pass filters.

4.5.

Luma Path

Along with the chroma output path, the CS4954/5
Video Input Formatter initiates a parallel luma data
path by directing the luma data to a digital delay
line. The delay line is built as a digital FIFO in
which the depth of the FIFO replicates the clock
period delay associated with the more complex
chroma path. Brightness adjustment is also provid-
ed via the 8-bit BRIGHTNESS_OFFSET Register.

Following the luma delay, the data is passed
through an interpolation filter that has a program-
mable bandwidth, followed by a variable gain am-
plifier in which the luma DC values are modifiable
via the Y_AMP Register.

The output of the luma amplifier connects to the
sync insertion block. Sync insertion is accom-
plished by multiplexing, into the luma data path,
the different sync DC values at the appropriate
times. The digital sync generator takes horizontal
sync and vertical sync timing signals and generates
the appropriate composite sync timing (including
vertical equalization and serration pulses), blank-
ing information, and burst flag. The sync edge rates
conform to RS-170A or ITU R.BT601 and ITU
R.BT470 specifications.

It is also possible to delay the luminance signal,
with respect to the chrominance signal, by up to

three pixel clocks. This variable delay is useful to
offset different propagation delays of the luma
baseband and modulated chroma signals. This ad-
justable luma delay is available only on the
CVBS_1 output.

4.6.

RGB Path and Component YUV Path

The RGB datapath has the same latency as the luma
and chroma path. Therefore all six simultaneous
analog outputs are synchronized. The 4:2:2 YCbCr
data is first interpolated to 4:4:4 and then interpo-
lated to 27 MHz. The color space conversion is per-
formed at 27 MHz. The coefficients for the color
space conversion conform to the ITU R.BT601
specifications.

After color space conversion, the amplitude of each
component can be independently adjusted via the
R_AMP, G_AMP, and B_AMP 8-bit host address-
able registers. A synchronization signal can be add-
ed to either one, two or all of the RGB signals. The
synchronization signal conforms to NTSC or PAL
specifications.

Some applications (e.g., projection TVs) require
analog component YUV signals. The chip provides
a programmable mode that outputs component
YUV data. Sync can be added to the luminance sig-
nal. Independent gain adjustment of the three com-
ponents is provided as well.

4.7.

Digital to Analog Converters

The CS4954/5 provides six discrete 27 MHz DACs
for analog video. The default configuration is one
10-bit DAC for S-video chrominance, one 10-bit
DAC for S-Video luminance, one 10-bit DAC for
composite output, and three 10-bit DACs for RGB
outputs. All six DACs are designed for driving ei-
ther low-impedance loads (double terminated
75

) or high-impedance loads (double terminated

300

). There are five different DAC configura-

tions to choose from (see Table 1, below).

The DACs can be put into tri-state mode via host-
addressable control register bits. Each of the six

CS4954 CS4955

DS278PP4

DACs has its own associated DAC enable bit. In
the Disable Mode, the 10-bit DACs source (or sink)
zero current.

When running the DACs with a low-impedance
load, a minimum of three DACs must be powered
down. When running the DACs with a high-imped-
ance load, all the DACs can be enabled simulta-
neously.

For lower power standby scenarios, the CS4954/5
also provides power shut-off control for the DACs.
Each DAC has an associated DAC shut-off bit.

4.8.

Voltage Reference

The CS4954/5 is equipped with an on-board volt-
age reference generator (1.232 V) that is used by
the DACs. The internal reference voltage is accu-
rate enough to guarantee a maximum of 3% overall
gain error on the analog outputs. However, it is
possible to override the internal reference voltage
by applying an external voltage source to the VREF
pin.

4.9.

Current Reference

The DAC output current-per-bit is derived in the
current reference block. The current step is speci-
fied by the size of resistor placed between the ISET
current reference pin and electrical ground.

A 4 k

resistor needs to be connected between

ISET pin and GNDA. The DAC output currents are
optimized to either drive a doubly terminated load
of 75

(low impedence mode) or a double termi-

nated load of 300

(high impedence mode). The 2

output current modes are software selectable
through a register bit.

4.10. Host Interface

The CS4954/5 provides a parallel 8-bit data inter-
face for overall configuration and control. The host
interface uses active-low read and write strobes,
along with an active-low address enable signal, to
provide microprocessor-compatible read and write
cycles. Indirect host addressing to the CS4954/5 in-
ternal registers is accomplished via an internal ad-
dress register that is uniquely accessible via bus
write cycles in which the host address enable signal
is asserted.

The CS4954/5 also provides an I

C-compatible se-

rial interface for device configuration and control.
This port can operate in standard (100Kb/sec) or
fast (400 Kb/sec) modes. When in I

C mode, the

parallel data interface pins, PDAT [7:0], can be
used as a general purpose I/O port controlled by the
I

C interface.

4.11. Closed Caption Services

The CS4954/5 supports the generation of NTSC
Closed Caption services. Line 21 and Line 284 cap-
tioning can be generated and enabled independent-
ly via a set of control registers. When enabled,
clock run-in, start bit, and data bytes are automati-
cally inserted at the appropriate video lines. A con-
venient interrupt protocol simplifies the software
interface between the host processor and the
CS4954/5.

DAC

Pin #

Mode 1

Mode 2

Mode 3

Mode 4

Mode 5

CVBS_2

CVBS

CVBS_1

Cr (V)

CVBS_2

Cb (U)

Table 1. DAC configuration Modes

CS4954 CS4955

DS278PP4

4.12. Teletext Services

The CS4954/5 encodes the most common teletext
formats, such as European Teletext, World Stan-
dard Teletext (PAL and NTSC), and North Ameri-
can Teletext (NABTS).

Teletext data can be inserted in any of the TV lines
(blanking lines as well as active lines). In addition
the blanking lines can be individually allocated for
Teletext instantiation.

The input timing for teletext data is user program-
mable. See the section Teletext Services for further
details.

Teletext data can be independently inserted on ei-
ther one or all of the CVBS_1, CVBS_2, or S-video
signals.

4.13. Wide-Screen Signaling Support and

CGMS

Insertion of wide-screen signal encoding for PAL
and NTSC standards is supported and CGMS
(Copy Generation Management System) for NTSC
in Japan. Wide-screen signals are inserted in lines
23 and 336 for PAL, and lines 20 and 283 for
NTSC.

4.14. VBI Encoding

This chip supports the transmission of control sig-
nals in the vertical blanking time interval according
to SMPTE RP 188 recommendations. VBI encoded
data can be independently inserted into either or all
of CVBS_1, CVBS_2 or S-video signals.

4.15. Control Registers

The control and configuration of the CS4954/5 is
accomplished primarily through the control regis-
ter block. All of the control registers are uniquely
addressable via the internal address register. The
control register bits are initialized during device
RESET.

See the Programming section of this data sheet for
the individual register bit allocations, bit operation-
al descriptions, and initialization states.

4.16. Testability

The digital circuits are completely scanned by an
internal scan chain, thus providing close to 100%
fault coverage.

OPERATIONAL DESCRIPTION

5.1.

Reset Hierarchy

The CS4954/5 is equipped with an active low asyn-
chronous reset input pin, RESET. RESET is used to
initialize the internal registers and the internal state
machines for subsequent default operation. See the
electrical and timing specification section of this
data sheet for specific CS4954/5 device RESET
and power-on signal timing requirements and re-
strictions.

While the RESET pin is held low, the host interface
in the CS4954/5 is disabled and will not respond to
host-initiated bus cycles. All outputs are valid after
a time period following RESET pin low.

A device RESET initializes the CS4954/5 internal
registers to their default values as described by Ta-
ble 9, Control Registers. In the default state, the
CS4954/5 video DACs are disabled and the device
is internally configured to provide blue field video
data to the DACs (any input data present on the
V [7:0] pins is ignored at this time). Otherwise, the
CS4954/5 registers are configured for NTSC-M
ITU R.BT601 output operation. At a minimum, the
DAC Registers (0x04 and 0x05) must be written (to
enable the DACs) and the IN_MODE bit of the
CONTROL_0 Register (0x01) must be set (to en-
able ITU R.BT601 data input on V [7:0]) for the
CS4954/5 to become operational after RESET.

CS4954 CS4955

DS278PP4

5.2.

Video Timing

5.2.1. Slave Mode Input Interface

In Slave Mode, the CS4954/5 receives signals on
VSYNC and HSYNC as inputs. Slave Mode is the
default following RESET and is changed to Master
Mode via a control register bit (CONTROL_0 [4]).
The CS4954/5 is limited to ITU R.BT601 horizon-
tal and vertical input timing. All clocking in the
CS4954/5 is generated from the CLK pin. In Slave
Mode, the Sync Generator uses externally provided
horizontal and vertical sync signals to synchronize
the internal timing of the CS4954/5. Video data that
is sent to the CS4954/5 must be synchronized to the
horizontal and vertical sync signals. Figure 4 illus-
trates horizontal timing for ITU R.BT601 input in
Slave Mode. Note that the CS4954/5 expects to re-
ceive the first active pixel data on clock cycle 245
(NTSC) when CONTROL_2 Register (0x02) bit

SYNC_DLY = 0. When SYNC_DLY = 1, it expects
the first active pixel data on clock cycle 246 (NTSC).

5.2.2. Master Mode Input Interface

The CS4954/5 defaults to Slave Mode following
RESET high but can be switched into Master Mode
via the MSTR bit in the CONTROL_0 Register
(0x00). In Master Mode, the CS4954/5 uses the
VSYNC, HSYNC and FIELD device pins as out-
puts to schedule the proper external delivery of dig-
ital video into the V [7:0] pins. Figure 5 illustrates
horizontal timing for the CCIR601 input in Master
Mode.

The timing of the HSYNC output is selectable in
the PROG_HS Registers (0x0D, 0x0E). HSYNC
can be delayed by one full line cycle. The timing of
the VSYNC output is also selectable in the

CLK

1706

active pixel

#720

HSYNC (input)

V[7:0]

(SYNC_DLY=0)

1705

1704

1703

1728

128

129

264

265

266

267

268

1686

1685

1684

1683

1716

128

129

244

245

246

247

248

horizontal blanking

active pixel

· · ·

NTSC 27MHz Clock Count

PAL 27MHz Clock Count

1702

1682

active pixel

#720

V[7:0]

(SYNC_DLY=1)

horizontal blanking

active pixel

#719

Figure 4. ITU R.BT601 Input Slave Mode Horizontal Timing

CLK

1706

active pixel

#720

HSYNC (output)

V[7:0]

1705

1704

1703

1728

128

129

264

265

266

267

268

1686

1685

1684

1683

1716

128

129

244

245

246

247

248

horizontal blanking

active pixel

· · ·

NTSC 27MHz Clock Count

PAL 27MHz Clock Count

CB (output)

1702

1682

Figure 5. ITU R.BT601 Input Master Mode Horizontal Timing

CS4954 CS4955

DS278PP4

PROG_VS Register (0x0D). VSYNC can be de-
layed by thirteen lines or advanced by eighteen lines.

5.2.3. Vertical Timing

The CS4954/5 can be configured to operate in any
of four different timing modes: PAL, which is 625
vertical lines, 25 frames per second interlaced;
NTSC, which is 525 vertical lines, 30 frames per
second interlaced; and either PAL or NTSC in Pro-
gressive Scan, in which the display is non-inter-
laced. These modes are selected in the
CONTROL_0 Register (0x00).

The CS4954/5 conforms to standard digital decom-
pression dimensions and does not process digital
input data for the active analog video half lines as
they are typically in the over/underscan region of
televisions. 240 active lines total per field are pro-
cessed for NTSC, and 288 active lines total per
field are processed for PAL. Frame vertical dimen-
sions are 480 lines for NTSC and 576 lines for
PAL. Table 2 specifies active line numbers for both
NTSC and PAL. Refer to Figure 6 for HSYNC,
VSYNC and FIELD signal timing.

5.2.4. Horizontal Timing

HSYNC is used to synchronize the horizontal-in-
put-to-output timing in order to provide proper hor-
izontal alignment. HSYNC defaults to an input pin
following RESET but switches to an output in Mas-
ter Mode (CONTROL_0 [4] = 1). Horizontal tim-
ing is referenced to HSYNC transitioning low. For
active video lines, digital video input is to be ap-
plied to the V [7:0] inputs for 244 (NTSC) or for
264 (PAL) CLK periods following the leading

(falling) edge of HSYNC if the PROG_HS Regis-
ters are set to default values.

5.2.5. NTSC Interlaced

The CS4954/5 supports NTSC-M, NTSC-J and
PAL-M modes where there are 525 total lines per
frame and two fixed 262.5-line fields per frame and
30 total frames occurring per second. NTSC inter-
laced vertical timing is illustrated in Figure 7. Each
field consists of one line for closed caption, 240 ac-
tive lines of video, plus 21.5 lines of blanking.

VSYNC field one transitions low at the beginning
of line four and will remain low for three lines or
2574 pixel cycles (858 × 3). The CS4954/5 exclu-
sively reserves line 21 of field one for closed cap-
tion insertion. Digital video input is expected to be
delivered to the CS4954/5 V [7:0] pins for 240
lines beginning on active video lines 22 and con-
tinuing through line 261. VSYNC field two transi-
tions low in the middle of line 266 and stays low for
three line-times and transitions high in the middle
of line 269. The CS4954/5 exclusively reserves line
284 of field two for closed caption insertion. Video
input on the V [7:0] pins is expected between lines
285 through line 525.

5.2.6. PAL Interlaced

The CS4954/5 supports PAL modes B, D, G, H, I,
N, and Combination N, in which there are 625 total
lines per frame, two fixed 312.5 line fields per
frame, and 25 total frames per second. Figure 8 il-
lustrates PAL interlaced vertical timing. Each field
consists of 287 active lines of video plus 25.5 lines
of blanking.

VSYNC will transition low to begin field one and
will remain low for 2.5 lines or 2160 pixel cycles
(864 × 2.5). Digital video input is expected to be
delivered to the CS4954/5 V [7:0] pins for 287
lines beginning on active video line 24 and continu-
ing through line 310.

Field two begins with VSYNC transitioning low
after 312.5 lines from the beginning of field one.

Mode

Field

Active Lines

NTSC

1, 3;

2, 4

22-261;

285-524

PAL

1, 3, 5, 7;

2, 4, 6, 8

23-310;

336-623

NTSC Progressive-Scan

22-261

PAL Progressive-Scan

23-310

Table 2. Vertical Timing

CS4954 CS4955

DS278PP4

VSYNC stays low for 2.5 line-times and transitions
high with the beginning of line 315. Video input on
the V [7:0] pins is expected between line 336
through line 622.

5.2.7. Progressive Scan

The CS4954/5 supports a progessive scan mode in
which the video output is non-interlaced. This is
accomplished by displaying only the odd video
field for NTSC or PAL. To preserve precise
MPEG-2 frame rates of 30 and 25 per second, the
CS4954/5 displays the same odd field repetitively
but alternately varies the field times. This mode is
in contrast to other digital video encoders, which

commonly support progressive scan by repetitively
displaying a 262 line field (524/525 lines for
NTSC). The common method is flawed: over time,
the output display rate will overrun a system-clock-
locked MPEG-2 decompressor and display a field
twice every 8.75 seconds.

5.2.8. NTSC Progressive Scan

VSYNC will transition low at line four to begin
field one and will remain low for three lines or
2574 pixel cycles (858 × 3). NTSC interlaced tim-
ing is illustrated in Figure 9. In this mode, the
CS4954/5 expects digital video input at the V [7:0]

NTSC Vertical Timing (odd field)

Line

HSYNC

VSYNC

FIELD

NTSC Vertical Timing (even field)

PAL Vertical Timing (odd field)

PAL Vertical Timing (even field)

264

265

266

267

268

269

270

271

265

311

312

313

314

315

316

317

318

Line

HSYNC

VSYNC

FIELD

Line

HSYNC

VSYNC

FIELD

Line

HSYNC

VSYNC

FIELD

Figure 6. Vertical Timing

CS4954 CS4955

DS278PP4

pins for 240 lines beginning on active video line 22
and continuing through line 261.

Field two begins with VSYNC transitioning low at
line 266. VSYNC stays low for 3 line cycles and
transitions high during the end of line 268. Video
input on the V [7:0] pins is expected between line
284 and line 522. Field two is 263 lines; field one
is 262 lines.

5.2.9. PAL Progressive Scan

VSYNC will transition low at the beginning of the
odd field and will remain low for 2.5 lines or 2160
pixel cycles (864 × 2.5). PAL non-interlaced tim-
ing is illustrated in Figure 10. In this mode, the
CS4954/5 expects digital video input on the V [7:0]
pins for 288 lines, beginning on active video line 23
and continuing through line 309.

The second begins with VSYNC transitioning low
after 312 lines from the beginning of the first field.
VSYNC stays low for 2.5 line-times and transitions

high during the middle of line 315. Video input on
the V [7:0] pins is expected between line 335
through line 622. Field two is 313 lines; field one is
312 lines.

5.3.

ITU-R.BT656

The CS4954/5 supports an additional ITU-
R.BT656 slave mode feature that is selectable
through the ITU-R.BT656 bit of the CONTROL_0
Register. The ITU-R.BT656 slave feature is unique
because the horizontal and vertical timing and dig-
ital video are combined into a single 8-bit 27 MHz
input. With ITU-R.BT656 there are no horizontal
and vertical input or output strobes, only 8-bit
27 MHz active CbYCrY data, with start- and end-
of-video codes implemented using reserved 00 and
FF code sequences within the video feed. As with
all modes, V [7:0] are sampled with the rising edge
of CLK. The CS4954/5 expects the digital ITU-
R.BT656 stream to be error-free. The FIELD out-

523

524

525

VSYNC Drops

Analog
Field 1

261

262

263

Analog
Field 2

285

284

272

271

270

269

268

267

266

265

264

523

524

525

VSYNC Drops

Analog
Field 3

261

262

263

Analog
Field 4

285

284

272

271

270

269

268

267

266

265

264

Burst begins with positive half-cycle

Burst begins with negative half-cycle

Figure 7. NTSC Video Interlaced Timing

CS4954 CS4955

DS278PP4

5.4.

Digital Video Input Modes

The CS4954/5 provides two different digital video
input modes that are selectable through the
IN_MODE bit in the CONTROL_0 Register.

In Mode 0 and upon RESET, the CS4954/5 de-
faults to output a solid color (one of a possible of
256 colors). The background color is selected by
writing the BKG_COLOR Register (0x08). The
colorspace of the register is RGB 3:3:2 and is unaf-
fected by gamma correction. The default color fol-
lowing RESET is blue.

In Mode 1 the CS4954/5 supports a single 8-bit
27 MHz CbYCrY source as input on the V [7:0]
pins. Input video timing can be ITU-R.BT601 mas-
ter or slave and ITU-R.BT656.

5.5.

Multi-standard Output Format
Modes

The CS4954/5 supports a wide range of output for-
mats compatible with worldwide broadcast stan-
dards. These formats include NTSC-M, NTSC-J,
PAL-B/D/G/H/I, PAL-M, PAL-N, and PAL Com-
bination N (PAL-Nc) which is the broadcast stan-
dard used in Argentina. After RESET, the CS4954/5
defaults to NTSC-M operation with ITU R.BT 601
analog timing. NTSC-J can also be supported in the
Japanese format by turning off the 7.5 IRE pedestal
through the PED bit in the CONTROL_1 Register
(0x01).

Output formats are configured by writing control
registers with the values shown in Table 3.

5.6.

Subcarrier Generation

The CS4954/5 automatically synthesizes NTSC
and PAL color subcarrier clocks using the CLK fre-
quency and four control registers
(SC_SYNTH0/1/2/3). The NTSC subcarrier syn-
thesizer is reset every four fields (every eight fields
for PAL).

The SC_SYNTH0/1/2/3 registers used together
provide a 32-bit value that defaults to NTSC
(43E0F83Eh) following RESET. Table 4 shows the
32-bit value required for each of the different
broadcast formats.

5.7.

Subcarrier Compensation

Since the subcarrier is synthesized from CLK the
subcarrier frequency error will track the clock fre-
quency error. If the input clock has a tolerance of
200 ppm then the resulting subcarrier will also
have a tolerance of 200 ppm. Per the NTSC speci-
fication, the final subcarrier tolerance is ±10 Hz

Cr Y

FF 00 00 XY 80 10 80 10

80 10 80 10 80 10

80 10 80 10 FF 00 00 XY Cb Y

Cr Cb Y Cr

1440 Clocks

Active Video

SAV Code

Composite

Video

Ancilliary Data

268 Clocks (NTSC)
280 Clocks (PAL)

Horizontal Blanking

EAV Code

4 Clocks

Active Video

V[7:0]

ITU R.BT656

4 Clocks

Figure 11. CCIR656 Input Mode Timing

DATA

System

Fsubcarrier

Value (hex)

NTSC-M, NTSC-J

3.5795455 MHz

43E0F83E

PAL-B, D, G, H, I, N 4.43361875 MHz 54131596

PAL-N (Argentina)

3.582056 MHz

43ED288D

PAL-M

3.579611 MHz

43CDDFC7

Table 3.

CS4954 CS4955

DS278PP4

which is approximately 3 ppm. Care must be taken
in selecting a suitable clock source.

In MPEG-2 system environments the clock is actu-
ally recovered from the data stream. In these cases
the recovered clock can be 27 MHz

50 ppm or

±1350 Hz. It varies per television, but in many cas-
es given an MPEG-2 system clock of 27 MHz,
±1350 Hz, the resultant color subcarrier produced
will be outside of the television's ability to com-
pensate and the chrominance information will not
be displayed (resulting in a black-and-white picture
only).

The CS4954/5 is designed to provide automatic
compensation for an excessively inaccurate
MPEG-2 system clock. Sub-carrier compensation
is enabled through the XTAL bit of the
CONTROL_2 Register. When enabled the
CS4954/5 will utilize a common quartz color burst
crystal (3.579545 MHz ± 50 ppm for NTSC) at-
tached to the XTAL_IN and XTAL_OUT pins to
automatically compare and compensate the color
subcarrier synthesis process.

5.8.

Closed Caption Insertion

The CS4954/5 is capable of NTSC Closed Caption
insertion on lines 21 and 284 independently.
Closed captioning is enabled for either one or both
lines via the CC_EN [1:0] Register bits and the

data to be inserted is also written into the four
Closed Caption Data registers. The CS4954/5,
when enabled, automatically generates the seven
cycles of clock run-in (32 times the line rate), start
bit insertion (001), and finally insertion of the two
data bytes per line. Data low at the video outputs
corresponds to 0 IRE and data high corresponds to
50 IRE.

There are two independent 8-bit registers per line
(CC_21_1 & CC_21_2 for line 21 and CC_284_1
& CC_284_2 for line 284). Interrupts are also pro-
vided to simplify the handshake between the driver
software and the device. Typically the host would
write all 4 bytes to be inserted into the registers and
then enable closed caption insertion and interrupts.
As the closed caption interrupts occur the host soft-
ware would respond by writing the next two bytes
to be inserted to the correct control registers and
then clear the interrupt and wait for the next field.

5.9.

Programmable H-sync and V-sync

It is possible in master mode to change the H-sync
and V-sync times based on register settings. Pro-
grammable H-sync and V-sync timings are helpful
in several digital video systems, where latencies of
the control signals are present. The user can then
program H-sync and V-sync timing according to
their system requirements. The default values are
244, and 264 for NTSC and PAL respectively.

Address

Register

NTSC-M

ITU

R.BT601

NTSC-J

ITU

R.BT601

NTSC-M

RS170A

PAL-

B,D,G,H,I

PAL-M

PAL-N

Comb.

(Argent)

0×00

CONTROL_0

01h

21h

41h

61h

A1h

81h

0×01

CONTROL_1

12h

10h

16h

30h

12h

30h

0×04

CONTROL_4

07h

0×05

CONTROL_5

78h

0×10

SC_AMP

1Ch

15h

0×11

SC_SYNTH0

3Eh

96h

C7h

96h

8Ch

0×12

SC_SYNTH1

F8h

15h

DFh

15h

28h

0×13

SC_SYNTH2

E0h

13h

CDh

13h

EDh

0×14

SC_SYNTH3

43h

54h

43h

54h

43h

Table 4. Multi-standard Format Register Configurations

CS4954 CS4955

DS278PP4

H-sync can be delayed by a full line, in 74 nsec in-
tervals.

V-sync can be shifted in both directions in time.
The default values are 18 and 23 for NTSC and
PAL respectively. Since the V-sync register is 5
bits wide (Sync Register 0), the V-sync pulse can
be shifted by 31 lines in total.

V-sync can preceed by a maximum of 18 lines
(NTSC) or 23 lines (PAL) respectively from its de-
fault location, and V-sync can follow by a maxi-
mum of 13 lines (NTSC) or 8 lines (PAL) from its
default location.

5.10. Wide Screen Signaling (WSS) and

CGMS

Wide screen signaling support is provided for
NTSC and for PAL standards. Wide screen signal-
ing is currently used in most countries with 625 line
systems as well as in Japan for EDTV-II applica-
tions. For complete description of WSS standard,
please refer to ITU-R BT.1119 (625 line system)
and to EIAJ CPX1204 for the Japanese 525 line
system.

The wide screen signal is transferred in a blanking
line of each video field (NTSC: lines 20 and 283,
PAL: lines 23 and 336). Wide screen signaling is
enabled by setting WW_23 to "1". Some countries
with PAL standard don't use line 336 for wide
screen signaling (they use only line 23), therefore
we provide another enable bit (WSS_22) for that
particular line.

There are 3 registers dedicated to contain the trans-
mitted WSS bits (WSS_REG_0, WSS_REG_1,
WSS_REG_2). The data insertion into the appro-
priate lines are performed automatically by this de-
vice. The run-in and start code bits do not have to
be loaded into this device, it automatically inserts
the correct code at the beginning of transfer.

5.11. Teletext Support

This chip supports several teletext standards, like
European teletext, NABTS (North American tele-
text), and WST (World Standard Teletext) for
NTSC and PAL.

All these teletext standards are defined in the ITU-
R BT.653-2 document. The European teletext is
defined as "teletext system B" for 625/50 Hz TV
systems. NABTS teletext is defined as "teletext
system C" for 525/60 Hz TV systems. WST for
PAL is defined as "teletext system D" for
624/50 Hz TV systems and WST for NTSC is de-
fined as "teletext system D" for 525/60 Hz TV
systems.

This chip provides independant teletext encoding
into composite 1, composite 2 and s-video signals.
The teletext encoding into these various signals is
software programmable.

In teletext pulsation mode, (TTX_WINDOW=0),
register 0×31 bit 3, the pin TTXDAT receives a
teletext bitstream sampled at the 27 Mhz clock. At
each rising edge of the TTXRQ output signal a sin-
gle teletext bit has to be provided after a program-
mable input delay at the TTXDAT input pin.

Phase variant interpolation is achieved on this bit-
stream in the internal teletext encoder, providing
sufficient small phase jitter on the ouput text lines.

TTXRQ provides a fully programmable request
signal to the teletext source, indicating the insertion
period of the bitstream at indepenantly selectable
lines for both TV fields. The internal insertion win-
dow for text is set to either 360, 296 or 288 teletext
bits, depending on the selected teletext standard.
The clock run-in is included in this window.

Teletext in enabled by setting the TTX_EN bit to
"1". The TTX_WST bit in conjunction with the
TV_FORMAT register select one of the 4 possible
teletext encoding possibilities.

The teletext timing is shown in the Figure 12.
TTXHS and TTXHD are user programmable and

CS4954 CS4955

DS278PP4

therefore allow the user to have full control over to
when sending teletext data to this device.

The time t

is the time needed to interpolate tele-

text input data and inserting it into the CVBS and
Y output signals, such that it appears between
t

TTX

= 9.8

s and t

TTX

= 12

s after the leading

edge of the horizontal synchronization pulse. t

changes with the TV standard and the selected
teletext standard. Please refer to ITU-R BT.653-2
for more detailed information.

The time t

is the pipeline delay time introduced

by the source that is gated by TTXRQ in order to
deliver teletext data. This delay is programmable
through the register TTXHD. For every active
HIGH transition at output pin TTXRQ, a new tele-
text bit must be provided by the source. The time
between the beginning of the first TTXRQ pulse
and the leading edge of H-sync is programmable
through the TTXHS register.

Since the beginning of the pulses representing the
TTXRQ signal and the delay between the rising
edge of TTXRQ and valid teletext input data are
fully programmable, the TTXDAT data is always
inserted at the correct position after the leading
edge of the outgoing horizontal synchronization
pulse.

The time t

TTXWin

is the internally used insertion

window for TTX data; it has a constant length
depending on the selected teletext standard which
allows insertion of 360 TTX bits (6.9375
Mbit/sec) (European teletext) or 296 TTX bits

(5.6427875 Mbit/sec) (WST PAL) or 288 TTX bits
(5.727272 Mbit/sec) (NABTS) or 296 TTX bits
(5.727272 Mbit/sec) (WST NTSC) respectively.

Using the appropriate programming, all suitable
lines of the odd field (TTXOVS through TTX-
OVE) plus all suitable lines of the even field
(TTXEVS through TTXEVE) can be used for tele-
text insertion. In addition it is possible to selec-
tively disable the teletext insertion on single lines.
This can be programmed by setting the
TTX_LINE_DIS1, TTX_LINE_DIS2 and
TTX_LINE_DIS3 registers appropriately.

Note that the TTXDAT signal must be synchro-
nized with the 27 Mhz clock. The pulse width of
the TTXRQ signal varies between three and four
27 Mhz clock cycles. The variation is necessary in
order to maintain the strict timing requirements of
the teletext standard.

Table 5 shows how to program the TTXHS register
for teletext instantiation into the analog signals for
the various supported TV formats. TTXHS is the
time between the leading edge of the HSYNC sig-
nal and the rising edge of the first TTXRQ signal
and consists of multiples of 27 Mhz clock cycles

Note that with increasing values of TTXHS the
time t

TTX

increases as well. The time t

accounts

for the internal pipeline delay due to processing,
synchronization and instantiation of the teletext
data. The time t

is dependant on the TTXHD

Figure 12. Teletext Timing (Pulsation Mode)

Figure 13. Teletext Timing (Window Mode)

CVBS/Y

TTXRQ

TTXDAT

textbit #: 1

TTX

TTXWin

CVBS/Y

TTXRQ

TTXDAT

textbit #: 1

TTX

TTXWin

CS4954 CS4955

DS278PP4

Note that the teletext databits are shaped according
to the ITU R.BT653-2 specifications.

If register 0×31 bit 3 is set, (TTX_WINDOW=1)
the teletext is in windows mode, the request pulses
become a window where the bit provided on the
TTXDAT pin are valid (see Figure 13).

Alternately to the pulsation mode (where the num-
ber of request pulses are determined by the teletext
standard chosen), the length of the window must be
programmed by the user independently of the tele-
text standard used. The length of the window is
programmed through register 0×29 TTXHS (start
of window) and register 0×2A (TTXHD) and 0×31
(end of window). The end-of-window register is a
11 bit value.

In teletext window mode, the TTXHS value can be
selected using the values in Table 5. Although
these values may need to be adjusted to match your
system delay, use the following equation to com-
pute the TTXHD value:

TTXHS + 1402 = TTXHD (for Europe)

TTXHS + 1151 = TTXHD (for WST)

TTXHS + 1122 = TTXHD (for NABTS)

5.12. Color Bar Generator

The CS4954/5 is equipped with a color bar genera-
tor that is enabled through the CBAR bit of the

CONTROL_1 Register. The color bar generator
works in master or Slave Mode and has no effect on
the video input/output timing. If the CS4954/5 is
configured for Slave Mode color bars, proper video
timing must be present on the HSYNC and
VSYNC pins for the color bars to be displayed.
Given proper Slave Mode input timing or Master
Mode, the color bar generator will override the vid-
eo input pixel data.

The output of the color bar generator is instantiated
after the chroma interpolation filter and before the
luma delay line. The generated color bar numbers
are for 100% amplitude, 100% saturation NTSC
EIA color bars or 100% amplitude, 100% satura-
tion PAL EBU color bars. For PAL color bars, the
CS4954/5 generates NTSC color bar values, which
are very close to standard PAL values. The exact
luma and chroma values are listed in Table 6. .

5.13. VBI encoding

VBI (Vertical Blanking Interval) encoding is per-
formed according to SMPTE RP 188 recommenda-
tions. In NTSC mode lines 10 - 20 and lines 272 -

283 are used for the transmission of ancillary data.

In PAL mode lines 6 - 22 and lines 318 -335 are
used. The VBI encoding mode can be set through
the CONTROL_3 register.

All digital input data is passed through the chip
when this mode is enabled. It is therefore the re-
sponsibility of the user to ensure appropriate ampli-

TV standard

Teletext

standard

TTXHS

(register

value)

TTX

NTSC-M

NABTS

161

10.5

NTSC-M

WST-NTSC

142

9.8

PAL-B

Europe TTX

204

12.0

PAL-B

WST-PAL

163

10.5

PAL-M

NABTS

161

10.5

PAL-M

WST-NTSC

142

9.8

PAL-N (non Arg.)

Europe TTX

204

12.0

PAL-N (non Arg.)

WST-PAL

163

10.5

PAL-N (Arg.)

Europe TTX

204

12.0

PAL-N (Arg.)

WST-PAL

163

10.5

Table 5. Teletext timing parameters

Color

White

+ 167

Yellow

- 84

+ 14

+ 156

Cyan

+ 28

- 84

+ 138

Green

- 56

- 70

+ 127

Magenta

+ 56

+ 70

+ 110

Red

- 28

+ 84

+ 99

Blue

+ 84

- 14

+ 81

Black

+ 70

Table 6. Internal Color Bar Values (8-bit values, Cb/Cr

are in twos complement format)

CS4954 CS4955

DS278PP4

tude levels. Table 7 shows the relationship of the
digital input signal and the analog output voltage.

Each LSB corresponds to a step of 5 mV in the out-
put voltage.

5.14. Super White/Super Black support

The ITU-R BT.601 recommendation limits the al-
lowed range for the digital video data between
0×10 - 0×EB for luma and between 0×10 - 0×F0 for
the chrominance values. This chip will clip any
digital input value which is out of this range to con-
form to the ITU-R BT.601 specifications.

However for some applications it is useful to allow
a wider input range. By setting the CLIP_OFF bit
(CONTROL_6 register) the allowed input range is
extended between 0×01 - 0×FE for both luma and
chrominance values.

Note that 0×00 and 0×FF values are never allowed,
since they are reserved for synchronization infor-
mation.

5.15. Interrupts

In order to better support precise video mode
switches and to establish a software/hardware
handshake with the closed caption insertion block
the CS4954/5 is equipped with an interrupt pin
named INT. The INT pin is active high. There are
three interrupt sources: VSYNC, Line 21, and Line
284. Each interrupt can be individually disabled
with the INT_EN Register. Each interrupt is also
cleared via writing a one to the corresponding
INT_CLR Register bits. The three individual inter-
rupts are OR-ed together to generate an interrupt

signal which is presented on the INT output pin. If
an interrupt has occurred, it cannot be eliminated
with a disable, it must be cleared.

5.16. General Purpose I/O Port

The CS4954/5 has a GPIO port and register that is
available when the device is configured for I

host interface operation. In I

C host interface

mode, the PDAT [7:0] pins are unused by the host
interface and they can operate as input or output
pins for the GPIO_DATA_REG Register (0×0A).
The CS4954/5 also contains the
GPIO_CTRL_REG Register (0×09) which is used
to configure the GPIO pins for input or output op-
eration.

The GPIO port PDAT [7:0] pins are configured for
input operation when the corresponding
GPIO_CTRL_REG [7:0] bits are set to 0. In GPIO
input mode, the CS4954/5 will latch the data on the
PDAT [7:0] pins into the corresponding bit loca-
tions of GPIO_DATA_REG when it detects regis-
ter address 0×0A through the I

C interface. A

detection of address 0×0A can happen in two ways.
The first and most common way this will happen is
when address 0×0A is written to the CS4954/5 via
its I

C interface. The second method for detecting

address 0×0A is implemented by accessing register
address 0×09 through I

C. In I

C host interface op-

eration, the CS4954/5 register address pointer will
auto-increment to address 0×0A after an address
0×09 access.

The GPIO port PDAT [7:0] pins are configured for
output operation when the corresponding
GPIO_CTRL_REG [7:0] bits are set. In GPIO out-
put mode, the CS4954/5 will output the data in
GPIO_DATA_REG [7:0] bit locations onto the
corresponding PDAT [7:0] pins when it detects a
register address 0×0A through the I

C interface.

Digital Input

Analog Output Voltage

286 mV

300 mV

1000 mV

Table 7. VBI Encoding Signal Amplitudes

CS4954 CS4955

DS278PP4

ANALOG

7.1.

Analog Timing

All CS4954/5 analog timing and sequencing is de-
rived from 27 MHz clock input. The analog outputs
are controlled internally by the video timing genera-
tor in conjunction with master and slave timing. The
video output signals perform accordingly for NTSC
and PAL specifications.

Being that the CS4954/5 is almost entirely a digital
circuit, great care has been taken to guarantee ana-
log timing and slew rate performance as specified
in the NTSC and PAL analog specifications. Refer-
ence the Analog Parameters section of this data
sheet for exact performance parameters.

7.2.

VREF

The CS4954/5 can operate with or without the aid
of an external voltage reference. The CS4954/5 is
designed with an internal voltage reference genera-
tor that provides a VREFOUT signal at the VREF
pin. The internal voltage reference is utilized by not
making a connection to the VREF pin. The VREF
pin can also be connected to an external precision
1.232 volt reference, which then overrides the in-
ternal reference.

7.3.

ISET

All six of the CS4954/5 digital to analog converter
DACs are output current normalized with a com-
mon ISET device pin. The DAC output current per
bit is determined by the size of the resistor connect-
ed between ISET and electrical ground. Typically a
4 K

, 1% metal film resistor should be used. The

ISET resistance can be changed by the user to ac-
commodate varying video output attenuation via
post filters and also to suit individual preferred per-
formance.

In conjunction with the ISET value, the user can
also independently vary the chroma, luma and col-
orburst amplitude levels via host addressable con-
trol register bits that are used to control internal

digital amplifiers. The DAC output levels are de-
fined by the following operations:

VREF/RISET = IREF

(e.g., 1.232 V/4K

= 308

)

CVBS/Y/C/R/G/B outputs in low impedance mode:

VOUT (max) = IREF*(16/145)*1023*37.5

= 1.304V

CVBS/Y/C/R/G/B outputs in high impedance mode:

VOUT (max) = IREF*(4/145)*1023*150

= 1.304 V

7.4.

DACs

The CS4954/5 is equipped with six independent,
video-grade, current-output, digital-to-analog con-
verters (DACs). They are 10-bit DACs operating at
a 27 MHz two-times-oversampling rate. All six
DACs are disabled and default to a low power
mode upon RESET. Each DAC can be individually
powered down and disabled. The output-current-
per-bit of all six DACs is determined by the size of
the resistor connected between the ISET pin and
electrical ground.

7.4.1. Luminance DAC

The Y pin is driven from a 10-bit 27 MHz current
output DAC that internally receives the Y, or lumi-
nance portion, of the video signal (black and white
only). Y is designed to drive proper video levels
into a 37.5

load. Reference the detailed electrical

section of this data sheet for the exact Y digital to
analog AC and DC performance data. A EN_L en-
able control bit in the Control Register 5 (0×05) is
provided to enable or disable the luminance DAC.
For a complete disable and lower power operation
the luminance DAC can be totally shut down via
the SVIDLUM_PD control bit in the Control Regis-
ter 4 (0×04). In this mode, turn-on through the con-
trol register will not be instantaneous.

7.4.2. Chrominance DAC

The C pin is driven from a 10-bit 27 MHz current
output DAC that internally receives the C or

CS4954 CS4955

DS278PP4

chrominance portion of the video signal (color
only). C is designed to drive proper video levels
into a 37.5

load. Reference the detailed electrical

section of this data sheet for the exact C digital to
analog AC and DC performance data. A EN_C en-
able control register bit in the Control Register 1
(0×05) is provided to enable or disable the chromi-
nance DAC. For a complete disable and lower
power operation the chrominance DAC can be to-
tally shut down via the SVIDCHR_PD register bit
in the Control Register 4 (0×04). In this mode turn-
on through the control register will not be instanta-
neous.

7.4.3. CVBS DAC

The CVBS pin is driven from a 10-bit 27 MHz cur-
rent output DAC that internally receives a com-
bined luma and chroma signal to provide
composite video output. CVBS is designed to drive
proper composite video levels into a 37.5

load.

Reference the detailed electrical section of this data
sheet for the exact CVBS digital to analog AC and
DC performance data. The EN_COM enable con-
trol register bit, in Control Register 1 (0×05), is
provided to enable or disable the output pin. When
disabled, there is no current flow from the output.
For a complete disable and lower power operation,
the CVBS37 DAC can be totally shut down via the
COMDAC_PD control register bit in Control
Register 4 (0×04). In this mode turn-on through the
control register will not be instantaneous.

7.4.4. Red DAC

The Red pin is driven from a 10-bit 27 MHz current
output DAC that internally receives a combined
luma and chroma signal to provide composite vid-
eo output. Red is designed to drive proper compos-
ite video levels into a 37.5

load. Reference the

detailed electrical section of this data sheet for the
exact red digital to analog AC and DC performance
data. The EN_R enable control register bit, in Con-
trol Register 1 (0×05), is provided to enable or dis-
able the output pin. When disabled, there is no

current flow from the output. For a complete dis-
able and lower power operation, the red DAC can
be totally shut down via the R_PD control register
bit in Control Register 4 (0×04). In this mode turn-
on through the control register will not be instanta-
neous.

7.4.5. Green DAC

The green pin is driven from a 10-bit 27 MHz cur-
rent output DAC that internally receives a com-
bined luma and chroma signal to provide
composite video output. Green is designed to drive
proper composite video levels into a 37.5

load.

Reference the detailed electrical section of this data
sheet for the exact green digital to analog AC and
DC performance data. The EN_G enable control
register bit, in Control Register 1 (0×05), is provid-
ed to enable or disable the output pin. When dis-
abled, there is no current flow from the output. For
a complete disable and lower power operation, the
green DAC can be totally shut down via the G_PD
control register bit in Control Register 4 (0×04). In
this mode turn-on through the control register will
not be instantaneous.

7.4.6. Blue DAC

The blue pin is driven from a 10-bit 27 MHz cur-
rent output DAC that internally receives a com-
bined luma and chroma signal to provide
composite video output. Blue is designed to drive
proper composite video levels into a 37.5

load.

Reference the detailed electrical section of this data
sheet for the exact blue digital to analog AC and
DC performance data. The EN_B enable control
register bit, in Control Register 5 (0×05), is provid-
ed to enable or disable the output pin. When dis-
abled, there is no current flow from the output. For
a complete disable and lower power operation, the
blue DAC can be totally shut down via the B_PD
control register bit in Control Register 4 (0×04). In
this mode turn-on through the control register will
not be instantaneous.

CS4954 CS4955

DS278PP4

If some of the 6 DACs are not used, it is strongly
recommended to power them down (see
CONTROL_4 register) in order to reduce the pow-
er dissipation.

Depending on the external resistor connected to the
ISET pin the output drive of the DACs can be
changed. There are two modes in which the DACs
should either be operated in. An external resistor of
4 k

must be connected to the ISET pin.

The first mode is the high impedance mode
(LOW_IMP bit set to 0). The DAC outputs will
then drive a double terminated load of 300

and

will output a video signal which conforms to the
analog video specifications for NTSC and PAL.
External buffers will be needed if the DAC output
load differs from 300

The second mode is the low impedence mode
(LOW_IMP but set to 1). The DAC output will
then drive a double terminated load of 75

and

will output a video signal which conforms to the
analog video specifications for NTSC and PAL. No
external buffers are necessary, the ouputs can di-
rectly drive a television input.

Note that for power dissipation purposes it is not
always possible to have all the 6 DACs active at the
same time. Table 8 shows the maximum allowed
active DACs depending on the power supply and
low/high impedance modes. If less than 6 DACs
are allowed to be active the other ones must be
power down (see CONTROL_4 register).

PROGRAMMING

8.1.

Host Control Interface

The CS4954/5 host control interface can be config-
ured for I

C or 8-bit parallel operation. The

CS4954/5 will default to I

C operation when the

RD and WR pins are both tied low at power up. The
RD and WR pins are active for 8-bit parallel oper-
ation only.

8.1.1. I

C Interface

The CS4954/5 provides an I

C interface for access-

ing the internal control and status registers. Exter-
nal pins are a bidirectional data pin (SDA) and a
serial input clock (SCL). The protocol follows the
I

C specifications. A complete data transfer is

shown in Figure 26. Note that this I

C interface will

work in Slave Mode only - it is not a bus master.

SDA and SCL are connected via an external pull-
up resistor to a positive supply voltage. When the
bus is free, both lines are high. The output stages of
devices connected to the bus must have an open-
drain or open-collector in order to perform the
wired-AND function. Data on the I

C bus can be

Nominal Power

supply

Low/High

Impedance

mode

maximum # of

active DACs

3.3V

Low Impedance

3.3V

High Impedance

5.0V

Low Impedance

5.0V

High Impedance

Table 8. Maximum DAC Numbers

SDA

SCL

Start

Address

1-7

R/W

ACK

1-7

Data

1-7

ACK

Data ACK

Stop

Note: I

C transfers data always with MSB first, LSB last

Figure 26. I

C Protocol

CS4954 CS4955

DS278PP4

transferred at a rate of up to 400 Kbits/sec in fast
mode. The number of interfaces to the bus is solely
dependent on the limiting bus capacitance of 400
pF. When 8-bit parallel interface operation is being
used, SDA and SCL can be tied directly to ground.

The I

C bus address for the CS4954/5 is program-

mable via the I2C_ADR Register (0×0F). When
I

C interface operation is being used, RD and WR

must be tied to ground. PDAT [7:0] are available to
be used for GPIO operation in I

C host interface

mode. For 3.3 V operation it is necessary to have
the appropriate level shifting for I

C signals.

8.1.2. 8-bit Parallel Interface

The CS4954/5 is equipped with a full 8-bit parallel
microprocessor write and read control port. Along
with the PDAT [7:0] pins, the control port interface
is comprised of host read (RD) and host write (WR)

active low strobes and host address enable
(ADDR), which, when low, enables unique address
register accesses. The control port is used to access
internal registers which configure the CS4954/5 for
various modes of operation. The internal registers
are uniquely addressed via an address register. The
address register is accessed during a host write cy-
cle with the WR and ADDR pins set low. Host
write cycles with ADDR set high will write the 8-
bits on the PDAT [7:0] pins into the register cur-
rently selected by the address register. Likewise
read cycles occur with RD set low and ADDR set
high will return the register contents selected by the
address register. Reference the detailed electrical
timing parameter section of this data sheet for exact
host parallel interface timing characteristics and
specifications.

rec

Figure 27. 8-bit Parallel Host Port Timing: Read-Write/Write-Read Cycle

ADDR

PDAT[7:0]

rpw

rah

rda

rdh

Figure 28. 8-bit Parallel Host Port Timing: Address Read Cycle

CS4954 CS4955

DS278PP4

Control Register 0

Address

CONTROL_0

Read/Write

Default Value = 01h

Control Register 1

Address

CONTROL_1

Read/Write

Default Value = 02h

Bit Number

Bit Name

TV_FMT

MSTR

CCIR656

PROG

IN_MODE

CBCR_UV

Default

Bit

Mnemonic

Function

7:5

TV_FMT

selects the TV display format

000:

NTSC-M CCIR601 timing (default)

001:

NTSC-M RS170A timing

010:

PAL-B, D, G, H, I

011:

PAL-M

100:

PAL-N (Argentina)

101:

PAL-N (non Argentina)

110-111:

reserved

MSTR

1 = Master Mode, 0 = Slave Mode

CCIR656

video input is in ITU R.BT656 format (0 = off, 1 = on)

PROG

Progressive scanning enable (enable = 1)

IN_MODE

Input select (0 = solid background, 1 = use V [7:0] data)

CBCR_UV

enable YCbCr to YUV conversion (1 = enable, 0 = disable)

Bit Number

Bit Name

LUM DEL

CH BW

LPF_ON

RGB_BW

FLD

PED

CBCRSEL

Default

Bit

Mnemonic

Function

7:6

LUM DEL

luma delay on the composite1 output

00:

no delay (default)

01:

1 pixel clock delay

10:

2 pixel clock delay

11:

3 pixel clock delay

CH BW

chroma lpf bandwidth (0 = 650 kHz, 1 = 1.3 Mhz)

LPF ON

chroma lpf on/off (0 = off, 1 = on)

RGB_BW

0 = Full bandwidth on RGB, 1 = BW reduced to 2.5 MHz (3 dB point) (default 0)

FLD_POL

Polarity of Field (0: odd field = 0,1: odd field = 1)

PED

Pedestal offset (0: 0 IRE, 1: 7.5 IRE)

CBCRSEL

CbCr select (0 = chroma undelayed, 1 = chroma delayed by one clock)

CS4954 CS4955

DS278PP4

Control Register 3

Address

CONTROL_3

Read/Write

Default Value = 00h

Control Register 4

Address

CONTROL_4

Read/Write

Default Value = 3Fh

Bit Number

Bit Name

RESERVED

FD THR C1 FD THR C2 FD THR SV FD THR EN

CBAR

Default

Bit

Mnemonic

Function

7:5

reserved

FD THR C1

feedthrough enabled for composite 1 output (0 = off, 1 = on)

FD THR C2

feedthrough enabled for composite 2 output (0 = off, 1 = on)

FD THR SV

feedthrough enabled for s-video (on luma signal) (0 = off, 1 = on)

FD THR_EN

Enable (1 = enable) input to feed through during inactive lines

CBAR

internal color bar generator (0 = off, 1 = on)

Bit Number

Bit Name

CB_H_SEL

CB_FLD_SEL

COMDAC_PD SVIDLUM_PD SVIDCHR_PD

R_PD

G_PD

B_PD

Default

Bit

Mnemonic

Function

CB_H_SEL

Composite Blank / HSYNC output select (1 = CB select, 0 = HSYNC select)

CB_FLD_SEL

Composite Blank / FIELD output select (1 = CB select, 0 = HSYNC select)

COMDAC_PD

power down composite DAC

0: power up, 1: power down

SVIDLUM_PD

power down luma s-video DAC

0: power up, 1: power down

SVIDCHR_PD

power down chroma s-video DAC

0: power up, 1: power down

R_PD

power down red rgb video DAC

0: power up, 1: power down

G_PD

power down green rgb video DAC

0: power up, 1: power down

B_PD

power down blue rgb video DAC

0: power up, 1: power down

CS4954 CS4955

DS278PP4

Control Register 5

Address

CONTROL_5

Read/Write

Default Value = 00h

Control Register 6

Address

CONTROL_6

Read/Write

Default Value = 00h

Bit Number

Bit Name

RSVD

LOW IMP

EN COM

EN L

EN C

EN R

EN G

EN B

Default

Bit

Mnemonic

Function

reserved

LOW IMP

selects between high output impedance (0) or low output impedance (1) mode of DACs

EN COM

enable DAC for composite output 0: tri-state, 1: enable

EN L

enable s-video DAC for luma output 0: tri-state, 1: enable

EN C

enable s-video DAC for chroma output 0: tri-state, 1: enable

EN_R

enable rgb video DAC for red output 0: tri-state, 1: enable

EN_G

enable rgb video DAC for green output 0: tri-state, 1: enable

EN_B

enable rgb video DAC for blue output 0: tri-state, 1: enable

Bit Number

Bit Name

656 SYNC

OUT

CLIP OFF

TTXEN

COM2

TTXEN

COM1

TTXEN

SVID

BSYNC DIS GSYNC DIS RSYNC DIS

Default

Bit

Mnemonic

Function

656 SYNC OUT

Enable (=1) output of hsync and vsync in the ITU R.BT656 mode

CLIP OFF

Clipping input signals disable (0: clipping active 1: no clipping)

TTXEN COM2

Enable teletext at the composit2 output (0: disable teletext, 1 : enable teletext)

TTXEN COM1

Enable teletext at the composit1 output ( 0: disable teletext, 1 : enable teletext)

TTXEN SVID

Enable teletext at the s-video output ( 0: disable teletext, 1: enable teletext)

BSYNC DIS

Disable syncs in the blue or v output (0: enable syncs, 1: disable syncs)

GSYNC DIS

Disable syncs in the green or u output ( 0: enable syncs, 1: disable syncs)

RSYNC DIS

Disable syncs in the red or y output (0: enable syncs, 1: disable syncs)

CS4954 CS4955

DS278PP4

ide Screen Signalling Register 1

Address

WSS_REG_1

Read/Write

Default Value = 00h

Wide Screen Signalling Register 2

Address

WSS_REG_2

Read/Write

Default Value = 00h

ilter Register 0

Address

CB_AMP

Read/Write

Default Value = 80h

Bit Number

Bit Name

WSS_15

WSS_14

WSS_13

WSS_12

WSS_11

WSS_10

WSS_9

WSS_8

Default

Bit

Mnemonic

Function

WSS_15

PAL: group 2, bit 7, NTSC: bit 16

WSS_14

PAL: group 2, bit 6, NTSC: bit 15

WSS_13

PAL: group 2, bit 5, NTSC: bit 14

WSS_12

PAL: group 2, bit 4, NTSC: bit 13

WSS_11

PAL: group 1, bit 3, NTSC: bit 12

WSS_10

PAL: group 1, bit 2, NTSC: bit 11

WSS_9

PAL: group 1, bit 1, NTSC: bit 10

WSS_8

PAL: group 1, bit 0, NTSC: bit 9

Bit Number

Bit Name

WSS_7

WSS_6

WSS_5

WSS_4

WSS_3

WSS_2

WSS_1

WSS_0

Default

Bit

Mnemonic

Function

WSS_7

PAL: don't care, NTSC: bit 8

WSS_6

PAL: don't care, NTSC: bit 7

WSS_5

PAL: don't care, NTSC: bit 6

WSS_4

PAL: don't care, NTSC: bit 5

WSS_3

PAL: don't care, NTSC: bit 4

WSS_2

PAL: don't care, NTSC: bit 3

WSS_1

PAL: don't care, NTSC: bit 2

WSS_0

PAL: don't care, NTSC: bit 1

Bit Number

Bit Name

U_AMP

Default

Bit

Mnemonic

Function

7:0

U_AMP

U(Cb) amplitude coefficient

CS4954 CS4955

DS278PP4

Teletext Register 6

Address

TTX_DIS1

Read/Write

Default Value = 00h

eletext Register 7

Address

TTX_DIS2

Read/Write

Default Value = 00h

eletext Register 8

Address

TTX_DIS3

Read/Write

Default Value = 00h

Bit Number

Bit Name

TTX_LINE_DIS1

Default

Bit

Mnemonic

Function

7:0

TTX_LINE_DIS1

Teletext disable bits corresponding to the lines 5-12 respectively, (11111111=all
eight lines are disabled),

(MSB is for line 5, LSB is for line 12)

Bit Number

Bit Name

TTX_LINE_DIS2

Default

Bit

Mnemonic

Function

7:0

TTX_LINE_DIS2

Teletext disable bits corresponding to the lines 13-20 respectively, (11111111=all
eight lines are disablled,

(MSB is for line 13, LSB is for line 20)

Bit Number

Bit Name

TTXHD

RESERVED TTX_WINDOW

TTX_LINE_DIS3

Default

Bit

Mnemonic

Function

7:5

TTXHD

If TTX_WINDOW = 0 these 3 bits are unused.
If TTX_WINDOW = 1 these 3 bits are the MSBs of the register 0×2A; they are used
to specify the length of the teletext insertion window

Reserved

TTX_WINDOW

Selects between TTXRQ (= 0) pulsation or TTXRQ (= 1) Window mode

2:0

TTX_LINE_DIS3

Teletext disable bits corresponding to the lines 13-20 respectively, (111=all three
lines are disabled),

(MSB is for line 21, LSB is for line 23)

CS4954 CS4955

DS278PP4

Interrupt Register 0

Address

INT_EN

Read/Write

Default Value = 00h

Interrupt Register 1

Address

INT_CLR

Read/Write

Default Value = 00h

Status Register 0

Address

STATUS_0

Read Only

Default Value = 00h

Status Register 1

Address

STATUS_1

Read only

Default Value = 04h

Bit Number

Bit Name

RESERVED

INT_21_EN

INT_284_EN

INT_V_EN

Default

Bit

Mnemonic

Function

7:3

reserved

INT_21_EN

interrupt enable for closed caption line 21

INT_284_EN

interrupt enable for closed caption line 284

INT_V_EN

interrupt enable for new video field

Bit Number

Bit Name

RESERVED

CLR_INT_21

CLR_INT_284

CLR_INT_V

Default

Bit

Mnemonic

Function

7:3

reserved

CLR_INT_21

clear interrupt for closed caption line 21 (INT 21)

CLR_INT_284

clear interrupt for closed caption line 284 (INT_284)

CLR_INT_V

clear interrupt for new video field (INT_V)

Bit Number

2:0

Bit Name

INT_21

INT_284

INT_V

FLD

Default

Bit

Mnemonic

Function

INT_21

Interrupt flag for line 21 (closed caption) complete

INT_284

Interrupt flag for line 284 (closed caption) complete

INT_V

Interrupt flag for video field change

2:0

FLD_ST

Field Status bits(001 = field 1,000 = field 8)

Bit Number

Bit Name

DEVICE_ID

Default

Bit

Mnemonic

Function

7:0

DEVICE_ID

Device identification: CS4954: 0000 0100, CS4955: 0000 0101

CS4954 CS4955

DS278PP4

BOARD DESIGN AND LAYOUT
CONSIDERATIONS

The printed circuit layout should be optimized for
lowest noise on the CS4954/5 placed as close to the
output connectors as possible. All analog supply
traces should be as short as possible to minimize in-
ductive ringing.

A well designed power distribution network is es-
sential in eliminating digital switching noise. The
ground planes must provide a low-impedance re-
turn path for the digital circuits. A PC board with a
minimun of four layers is recommended. The
ground layer should be used as a shield to isolate
noise from the analog traces. The top layer (1)
should be reserved for analog traces but digital
traces can share this layer if the digital signals have
low edge rates and switch little current or if they are
separated from the analog traces by a signigicant
distance (dependent on their frequency content and
current). The second layer should then be the
ground plane followed by the analog power plane
on layer three and the digital signal layer on layer
four.

9.1.

Power and Ground Planes

The power and ground planes need isolation gaps
of at least 0.05

to minimize digital switching noise

effects on the analog signals and components. A
split analog/digital ground plane should be con-
nected at one point as close as possible to the
CS4954/5.

9.2.

Power Supply Decoupling

Start by reducing power supply ripple and wiring
harness inductance by placing a large (33-100 uF)
capacitor as close to the power entry point as pos-
sible. Use separate power planes or traces for the
digital and analog sections even if they use the
same supply. If necessary, further isolate the digital
and analog power supplies by using ferrite beads on
each supply branch followed by a low ESR capac-
itor.

Place all decoupling caps as close as possible the
the device as possible. Surface mount capacitors
generally have lower inductance than radial lead or
axial lead components. Surface mount caps should
be place on the component side of the PCB to min-
imize inductance caused by board vias. Any vias,
especially to ground, should be as large as possible
to reduce their inductive effects.

9.3.

Digital Interconnect

The digital inputs and outputs of the CS4954/5
should be isolated from the analog outputs as much
as possible. Use separate signal layers whenever
possible and do not route digital signals over the
analog power and ground planes.

Noise from the digital section is related to the digi-
tal edge rates used. Ringing, overshoot, under-
shoot, and ground bounce are all related to edge
rate. Use lower speed logic such as HCMOS for the
host port interface to reduce switching noise. For
the video input ports, higher speed logic is re-
quired, but use the slowest practical edge rate to re-
duce noise. To reduce noise, it is important to
match the source impedance, line impedance, and
load impedance as much as possible. Generally, if
the line length is greater than one fourth the signal
edge rate, line termination is necessary. Ringing
can also be reduced by damping the line with a se-
ries resistor (22-150

). Under extreme cases, it

may be advisable to use microstrip techniques to
further reduce radiated switching noise if very fast
edge rates (<2ns) are used. If microstrip techniques
are used, split the analog and digital ground planes
and use proper RF decoupling techniques.

9.4.

Analog Interconnect

The CS4954/5 should be located as close as possi-
ble the output connectors to minimize noise pickup
and reflections due to impedance mismatch. All un-
used analog outputs should be placed in shutdown.
This reduces the total power that the CS4954/5 re-
quires, and eliminates the impedance mismatch

CS4954 CS4955

DS278PP4

Pin Name

Pin Number

Type

Description

V [7:0]

8, 7, 6, 5, 4, 3, 2, 1

Digital video data inputs

CLK

27 MHz input clock

PADDR

Address enable line

XTAL_IN

subcarrier crystal input

XTAL_OUT

OUT

subcarrier crystal output

HSYNC/CB

I/O

Active low horizontal sync, or composite blank signal

VSYNC

I/O

Active low vertical sync.

FIELD/CB

OUT

Video field ID. Selectable polarity or composite blank

Host parallel port read strobe, active low

Host parallel port write strobe, active low

PDAT [7:0]

19, 20, 21, 22, 23, 24, 25, 26

I/O

Host parallel port/ general purpose I/O

SDA

I/O

C data

SCL

C clock input

CVBS

CURRENT

Composite video output

CURRENT

Luminance analog output

CURRENT

Chrominance analog output

CURRENT

Red analog output

CURRENT

Green analog output

CURRENT

Blue analog output

VREF

I/O

Internal voltage reference output or external refer-
ence input

ISET

CURRENT

DAC current set

TTXDAT

Teletext data input

TTXRQ

OUT

Teletext request output

INT

OUT

Interrupt output, active high

RESET

Active low master RESET

TEST

TEST pin. Ground for normal operation

VAA

36, 41, 46

+ 5 V or + 3.3 V supply (must be same as VDD)

GNDD

Ground

VDD

+5 V or 3.3 V supply (must be same as VAA)

GNDA

35, 42, 45

Ground

Table 10. Device Pin Description

Part Number CS4955

Document Outline