MAXIMUM RATINGS (TA=25°C)
SYMBOL
UNITS
Drain-Source Voltage
VDS
60
V
Drain-Gate Voltage
VDG
60
V
Gate-Source Voltage
VGS
40
V
Continuous Drain Current
ID
280
mA
Continuous Source Current (Body Diode)
IS
280
mA
Maximum Pulsed Drain Current
IDM
1.5
A
Maximum Pulsed Source Current
ISM
1.5
A
Power Dissipation
PD
350
mW (Note 1)
Power Dissipation
PD
300
mW (Note 2)
Power Dissipation
PD
150
mW (Note 3)
Operating and Storage
Junction Temperature
TJ,Tstg
-65 to +150
°C
Thermal Resistance
JA
357
°C/W
ELECTRICAL CHARACTERISTICS PER TRANSISTOR (TA=25°C unless otherwise noted)
SYMBOL
TEST CONDITIONS
MIN
MAX
UNITS
IGSSF
VGS=20V, VDS=0V
100
nA
IGSSR
VGS=20V, VDS=0V
100
nA
IDSS
VDS=60V, VGS=0V
1.0
µA
IDSS
VDS=60V, VGS=0V, Tj=125°C
500
µA
ID(ON)
VGS=10V, VDS 2VDS(ON)
500
mA
BVDSS
VGS=0V, ID=10µA
60
V
VGS(th)
VDS=VGS, ID=250µA
1.0
2.5
V
VDS(ON)
VGS=10V, ID=500mA
1.0
V
VDS(ON)
VGS=5.0V, ID=50mA
0.15
V
rDS(ON)
VGS=10V, ID=500mA
2.0
rDS(ON)
VGS=10V, ID=500mA, Tj=125°C
3.5
rDS(ON)
VGS=5.0V, ID=50mA
3.0
rDS(ON)
VGS=5.0V, ID=50mA, Tj=125°C
5.0
gFS
VDS 2VDS(ON), ID=200mA
80
mmhos
CMLDM7002A
CMLDM7002AJ
SURFACE MOUNT PICOmini
TM
DUAL N-CHANNEL
ENHANCEMENT-MODE
SILICON MOSFET
SOT-563 CASE
Central
Semiconductor Corp.
TM
R3 (19-December 2003)
DESCRIPTION:
The CENTRAL SEMICONDUCTOR CMLDM7002A
and CMLDM7002AJ are special dual versions of the
2N7002 Enhancement-mode N-Channel Field Effect
Transistor, manufactured by the N-Channel DMOS
Process, designed for high speed pulsed amplifier and
driver applications. The CMLDM7002A utilizes the USA
pinout configuration, while the CMLDM7002AJ utilizes the
Japanese pinout configuration. These special Dual
Transistor devices offer low rDS(ON) and low VDS (ON).
MARKING CODE: CMLDM7002A:
L02
CMLDM7002AJ: 02J
Notes: (1) Ceramic or aluminum core PC Board with copper mounting pad area of 4.0 mm
2
(2) FR-4 Epoxy PC Board with copper mounting pad area of 4.0 mm
2
(3) FR-4 Epoxy PC Board with copper mounting pad area of 1.4 mm
2
A
B
C
H
G
F
D
E
E
R0
1
2
3
6
5
4
Central
Semiconductor Corp.
TM
SOT-563 CASE - MECHANICAL OUTLINE
CMLDM7002A
CMLDM7002AJ
SURFACE MOUNT PICOmini
TM
DUAL N-CHANNEL
ENHANCEMENT-MODE
SILICON MOSFET
R3 (19-December 2003)
LEAD CODE:
1) GATE Q1
2) SOURCE Q1
3) DRAIN Q2
4) GATE Q2
5) SOURCE Q2
6) DRAIN Q1
MARKING CODE: L02
LEAD CODE:
1) SOURCE Q1
2) GATE Q1
3) DRAIN Q2
4) SOURCE Q2
5) GATE Q2
6) DRAIN Q1
MARKING CODE: 02J
CMLDM7002A
(USA Pinout)
CMLDM7002AJ
(Japanese Pinout)
ELECTRICAL CHARACTERISTICS PER TRANSISTOR - Continued (TA=25°C unless otherwise noted)
SYMBOL
TEST CONDITIONS
MIN
MAX
UNITS
Crss
VDS=25V, VGS=0, f=1.0MHz
5.0
pF
Ciss
VDS=25V, VGS=0, f=1.0MHz
50
pF
Coss
VDS=25V, VGS=0, f=1.0MHz
25
pF
ton
VDD=30V, VGS=10V, ID=200mA,
20
ns
toff
RG=25, RL=150
20
ns
VSD
VGS=0V, IS=400mA
1.2
V
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