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Part Number BS62LV1025

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R0201-BS62LV1025
Revision 2.2
April 2001
1
Very Low Power/Voltage CMOS SRAM
128K X 8 bit
· Vcc operation voltage : 4.5V ~ 5.5V
· Very low power consumption :
Vcc = 5.0V C-grade : 35mA (Max.) operating current
I- grade : 40mA (Max.) operating current
0.4uA (Typ.) CMOS standby current
· High speed access time :
-55 55ns (Max.) at Vcc = 5.0V
-70 70ns (Max.) at Vcc = 5.0V
· Automatic power down when chip is deselected
· Three state outputs and TTL compatible
· Fully static operation
· Data retention supply voltage as low as 1.5V
· Easy expansion with CE2, CE1, and OE options
The BS62LV1025 is a high performance, very low power CMOS
Static Random Access Memory organized as 131,072 words by 8 bits
and operates from a wide range of 4.5V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current of
0.4uA and maximum access time of 55ns in 5V operation.
Easy memory expansion is provided by an active LOW chip
enable (CE1), an active HIGH chip enable (CE2), and active LOW
output enable (OE) and three-state output drivers.
The BS62LV1025 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS62LV1025 is available in DICE form, JEDEC standard 32 pin
450mil Plastic SOP, 300mil Plastic SOJ, 600mil Plastic DIP,
8mmx13.4mm STSOP and 8mmx20mm TSOP.
DESCRIPTION
FEATURES
BLOCK DIAGRAM
PRODUCT FAMILY
PIN CONFIGURATIONS
Brilliance Semiconductor Inc
. reserves the right to modify document contents without notice.
BS62LV1025
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
GND
DQ2
DQ1
DQ0
A0
A1
A2
A3
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
VCC
A15
CE2
WE
A13
A8
A9
A11
OE
A10
CE1
DQ7
DQ6
DQ5
DQ4
DQ3
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
·
BS62LV1025SC
BS62LV1025SI
BS62LV1025PC
BS62LV1025PI
BS62LV1025JC
BS62LV1025JI
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
·
BS62LV1025TC
BS62LV1025STC
BS62LV1025TI
BS62LV1025STI
A11
A9
A8
A13
WE
CE2
A15
VCC
NC
A16
A14
A12
A7
A6
A5
A4
A7
Address
Input
Buffer
Row
Decoder
Memory Array
1024 x 1024
Column I/O
Sense Amp
Write Driver
Column Decoder
Data
Buffer
Output
Address Input Buffer
A3 A2 A1 A0 A10
Data
Buffer
Input
Control
Gnd
Vdd
OE
WE
CE1
DQ5
DQ4
A14
A8
A13
A12
8
8
8
8
DQ7
DQ6
DQ3
DQ2
DQ1
DQ0
A9
A11
A6
14
128
1024
1024
20
A16
A15
A4
A5
CE2
BSI
POWER DISSIPATION
SPEED
(ns)
STANDBY
(I
CCSB1
, Max)
Operating
(I
CC
, Max)
PRODUCT
FAMILY
OPERATING
TEMPERATURE
Vcc
RANGE
Vcc= 5.0V
Vcc=5.0V
Vcc=5.0V
PKG TYPE
BS62LV1025SC
SOP-32
BS62LV1025TC
TSOP-32
BS62LV1025STC
STSOP-32
BS62LV1025PC
PDIP-32
BS62LV1025JC
SOJ-32
BS62LV1025DC
+0
O
C to +70
O
C
4.5V ~ 5.5V
55 / 70
3.0uA
35mA
DICE
BS62LV1025SI
SOP-32
BS62LV1025TI
TSOP-32
BS62LV1025STI
STSOP-32
BS62LV1025PI
PDIP-32
BS62LV1025JI
SOJ-32
BS62LV1025DI
-40
O
C to +85
O
C
4.5V ~ 5.5V
55 / 70
5.0uA
40mA
DICE
R0201-BS62LV1025
Revision 2.2
April 2001
2
BSI
BS62LV1025
C
IN
Input
Capacitance
V
IN
=0V
6
pF
C
DQ
Input/Output
Capacitance
V
I/O
=0V
8
pF
ABSOLUTE MAXIMUM RATINGS
(1)
OPERATING RANGE
CAPACITANCE
(1)
(TA = 25
o
C, f = 1.0 MHz)
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
reliability.
1. This parameter is guaranteed and not tested.
SYMBOL
PARAMETER
RATING
UNITS
V
TERM
Terminal Voltage with
Respect to GND
-0.5 to
Vcc+0.5
V
T
BIAS
Temperature Under Bias
C
-40 to +125
O
T
STG
Storage Temperature
C
-60 to +150
O
P
T
Power Dissipation
1.0
W
I
OUT
DC Output Current
mA
20
RANGE
AMBIENT
TEMPERATURE
Vcc
Commercial
0
O
C to +70
O
C
4.5V ~ 5.5V
Industrial
-40
O
C to +85
O
C
4.5V ~ 5.5V
TRUTH TABLE
PIN DESCRIPTIONS
Name
Function
A0-A16 Address Input
These 17 address inputs select one of the 131,072 x 8-bit words in the RAM
CE1 Chip Enable 1 Input
CE2 Chip Enable 2 Input
CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active when
data read from or write to the device. If either chip enable is not active, the device is
deselected and is in a standby power mode. The DQ pins will be in the high
impedance state when the device is deselected.
WE Write Enable Input
The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
OE Output Enable Input
The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impedance state when OE is inactive.
DQ0-DQ7 Data Input/Output
These 8 bi-directional ports are used to read data from or write data into the RAM.
Ports
Vcc
Power Supply
Gnd
Ground
MODE
WE
CE1
CE2
OE
I/O OPERATION
Vcc CURRENT
X
H
X
X
Not selected
(Power Down)
X
X
L
X
High Z
I
CCSB
, I
CCSB1
Output Disabled
H
L
H
H
High Z
I
CC
Read
H
L
H
L
D
OUT
I
CC
Write
L
L
H
X
D
IN
I
CC
SYMBOL
PARAMETER
CONDITIONS
MAX.
UNIT
R0201-BS62LV1025
Revision 2.2
April 2001
3
BSI
BS62LV1025
PARAMETER
NAME
PARAMETER
TEST CONDITIONS
MIN. TYP. MAX.
(1)
UNITS
V
IL
Guaranteed Input Low
Voltage
(2)
Vcc=5.0V
-0.5
--
0.8
V
V
IH
Guaranteed Input High
Voltage
(2)
Vcc=5.0V
2.2
--
Vcc+0.2
V
I
IL
Input Leakage Current
Vcc = Max, V
IN
= 0V to Vcc
--
--
1
uA
I
OL
Output Leakage Current
Vcc = Max, CE1= V
IH
, CE2= V
IL,
or
OE = V
IH
, V
I/O
= 0V to Vcc
--
--
1
uA
V
OL
Output Low Voltage
Vcc = Max, I
OL
= 2mA
Vcc=5.0V
--
--
0.4
V
V
OH
Output High Voltage
Vcc = Min, I
OH
= -1mA
Vcc=5.0V
2.4
--
--
V
I
CC
Operating Power Supply
Current
CE1 = V
IL
, or CE2 = V
IH
,
I
DQ
= 0mA, F = Fmax
(3)
Vcc=5.0V
--
--
35
mA
I
CCSB
Standby Current-TTL
CE1 = V
IH
, or CE2 = V
IL
,
I
DQ
= 0mA, F = Fmax
(3)
Vcc=5.0V
--
--
2
mA
I
CCSB1
Standby Current-CMOS
CE1 Vcc-0.2V, CE2 0.2V,
V
IN
Vcc-0.2V or V
IN
0.2V
Vcc=5.0V
--
0.4
3
uA
1. Typical characteristics are at TA = 25
o
C.
2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.
3. Fmax = 1/t
RC
.
DATA RETENTION CHARACTERISTICS
( TA = 0
o
C to + 70
o
C )
1. Vcc = 1.5V, T
A
= + 25
O
C
2. t
RC
= Read Cycle Time
DC ELECTRICAL CHARACTERISTICS
( TA = 0
o
C to + 70
o
C )
LOW V
CC
DATA RETENTION WAVEFORM (1)
( CE1 Controlled )
CE1
Data Retention Mode
Vcc
t
CDR
Vcc
t
R
V
IH
V
IH
Vcc
V
DR
1.5V
CE Vcc - 0.2V
LOW V
CC
DATA RETENTION WAVEFORM (2)
( CE2 Controlled )
SYMBOL
PARAMETER
TEST CONDITIONS
MIN. TYP.
(1)
MAX.
UNITS
V
DR
Vcc for Data Retention
CE1
Vcc - 0.2V, CE2
0.2V,
V
IN
Vcc - 0.2V or V
IN
0.2V
1.5
--
--
V
I
CCDR
Data Retention Current
CE1
Vcc - 0.2V, CE2
0.2V,
V
IN
Vcc - 0.2V or V
IN
0.2V
--
0.02
0.3
uA
t
CDR
Chip Deselect to Data
Retention Time
0
--
--
ns
t
R
Operation Recovery Time
See Retention Waveform
T
RC
(2)
--
--
ns
CE2
Data Retention Mode
Vcc
t
CDR
Vcc
t
R
V
IL
V
IL
Vcc
V
DR
1.5V
CE2
0.2V
R0201-BS62LV1025
Revision 2.2
April 2001
4
Input Pulse Levels
Vcc/0V
Input Rise and Fall Times
Input and Output
Timing Reference Level
5ns
0.5Vcc
AC ELECTRICAL CHARACTERISTICS
( TA = 0
o
C to + 70
o
C, Vcc = 5.0V )
READ CYCLE
AC TEST CONDITIONS
AC TEST LOADS AND WAVEFORMS
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
MUST BE
STEADY
MAY CHANGE
FROM H TO L
DON T CAR
ANY CHANG
PERMITTED
E:
CHANGE :
E
STATE
DOES NOT
APPLY
MUST BE
STEADY
WILL BE
CHANGE
FROM H TO L
UNKNOWN
CENTER
LINE IS HIGH
IMPEDANCE
"OFF "STATE
MAY CHANGE
FROM L TO H
WILL BE
CHANGE
FROM L TO H
,
BSI
BS62LV1025
667
THEVENIN EQUIVALENT
ALL INPUT PULSES
10%
90%
Vcc
GND
5ns
90%
10%
1.73V
OUTPUT
FIGURE 2
5.0V
OUTPUT
INCLUDING
JIG AND
SCOPE
1928
1020
5PF
FIGURE 1B
5.0V
OUTPUT
INCLUDING
JIG AND
SCOPE
1928
100PF
FIGURE 1A
1020
JEDEC
PARAMETER
NAME
NAME
DESCRIPTION
BS62LV1025 - 55
MIN. TYP. MAX.
BS62LV1025-70
MIN. TYP. MAX.
UNIT
t
AVAX
t
RC
Read Cycle Time
55
--
--
70
--
--
ns
t
AVQV
t
AA
Address Access Time
--
--
55
--
--
70
ns
t
E1LQV
t
ACS1
Chip Select Access Time
(CE1)
--
--
55
--
--
70
ns
t
E2HOV
t
ACS2
Chip Select Access Time
(CE2)
--
--
55
--
--
70
ns
t
GLQV
t
OE
Output Enable to Output Valid
--
--
30
--
--
40
ns
t
E1LQX
t
CLZ1
Chip Select to Output Low Z
(CE1)
10
--
--
10
--
--
ns
t
E2HOX
t
CLZ2
Chip Select to Output Low Z
(CE2)
10
--
--
10
--
--
ns
t
GLQX
t
OLZ
Output Enable to Output in Low Z
10
--
--
10
--
--
ns
t
E1HQZ
t
CHZ1
Chip Deselect to Output in High Z
(CE1)
0
--
35
0
--
40
ns
t
E2HQZ
t
CHZ2
Chip Deselect to Output in High Z
(CE2)
0
--
35
0
--
40
ns
t
GHQZ
t
OHZ
Output Disable to Output in High Z
0
--
30
0
--
35
ns
t
AXOX
t
OH
Output Disable to Output Address Change
10
--
--
10
--
--
ns
PARAMETER
R0201-BS62LV1025
Revision 2.2
April 2001
5
NOTES:
1. WE is high in read Cycle.
2. Device is continuously selected when CE1 = V
IL
and CE2= V
IH.
3. Address valid prior to or coincident with CE1 transition low and/or CE2 transition high.
4. OE = V
IL
.
5. Transition is measured 500mV from steady state with C
L
= 5pF as shown in Figure 1B.
The parameter is guaranteed but not 100% tested.
±
BSI
BS62LV1025
READ CYCLE3
(1,4)
READ CYCLE2
(1,3,4)
SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE1
(1,2,4)
t
RC
t
OH
t
AA
D
OUT
ADDRESS
t
OH
t
CLZ
(5)
D
OUT
CE2
CE1
(5)
t
ACS2
t
ACS1
t
OH
t
RC
t
OE
t
CLZ2
t
CHZ2
(2,5)
D
OUT
CE2
CE1
OE
ADDRESS
(5)
t
CLZ1
(5)
t
ACS1
t
ACS2
t
CHZ1
(1,5)
t
OHZ
(5)
t
OLZ
t
AA
t
CHZ1,
t
CHZ2