Revision 2.2
April 2001

R0201-BS616UV1610

Ultra Low Power/Voltage CMOS SRAM

1M X 16 bit

· Ultra low operation voltage : 1.8 ~ 2.3V
· Ultra low power consumption :

Vcc = 2.0V C-grade: 25mA (Max.) operating current

I-grade : 30mA (Max.) operating current
1.2uA (Typ.) CMOS standby current

· High speed access time :

-70 70ns (Max.) at Vcc=2V
-10 100ns (Max.) at Vcc=2V

· Automatic power down when chip is deselected
· Three state outputs and TTL compatible
· Fully static operation
· Data retention supply voltage as low as 1.5V
· Easy expansion with CE2,CE1 and OE options
· I/O Configuration x8/x16 selectable by LB and UB pin

DESCRIPTION

FEATURES

BLOCK DIAGRAM

PRODUCT FAMILY

PIN CONFIGURATIONS

Brilliance Semiconductor Inc

. reserves the right to modify document contents without notice.

BS616UV1610

The BS616UV1610 is a high performance, ultra low power CMOS Static
Random Access Memory organized as 1,048,576 words by 16 bits and
operates from a wide range of 1.8V to 2.3V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current
of 1.2uA and maximum access time of 70/100ns in 2V operation.
Easy memory expansion is provided by an active LOW chip enable(CE1),
active HIGH chip enable (CE2), active LOW output enable(OE) and
three-state output drivers.
The BS616UV1610 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS616UV1610 is available in 48-pin BGA package.

POWER DISSIPATION

SPEED

(ns)

STANDBY

CCSB1

, Max)

Operating

, Max)

Vcc

RANGE

Vcc=2V

PKG TYPE

BS616UV1610BC

BGA

0810

BS616UV1610FC

C to +70

1.8 ~ 2.3V

30uA

BGA

0912

70 / 100

25mA

BS616UV1610BI

BGA

0810

BS616UV1610FI

C to +85

C 1.8 ~ 2.3V

70 / 100

40uA

30mA

BGA

0912

CE2

CE1

D10

VSS

VCC

D12

A16

VSS

A15

A13

A18

D11

A17

D14

D13

A14

D15

A10

A11

A19

VSS

Row

Decoder

Memory Array

2048 x 8192

Column I/O

Write Driver

Sense Amp

Column Decoder

Data

Buffer

Output

A9 A8 A7

Data

Input

Buffer

Control

Gnd

Vcc

A15

CE1

D15

A13

A14

512

8192

2048

A17
A16

A10

A12

A11

Address

Input

Buffer

Address Input Buffer

.
.
.
.

A18

CE2

A19

48-Ball CSP top View

BSI

PRODUCT FAMILY

OPERATING

TEMPERATURE

Revision 2.2
April 2001

R0201-BS616UV1610

TRUTH TABLE

PIN DESCRIPTIONS

BSI

BS616UV1610

Name

Function

A0-A19 Address Input

These 20 address inputs select one of the 1,048,576 x 16-bit words in the RAM.

CE1 Chip Enable 1 Input
CE2 Chip Enable 2 Input

CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active when
data read from or write to the device. If either chip enable is not active, the device is
deselected and is in a standby power mode. The DQ pins will be in the high
impedance state when the device is deselected.

WE Write Enable Input

The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.

OE Output Enable Input

The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impedance state when OE is inactive.

LB and UB Data Byte Control Input

Lower byte and upper byte data input/output control pins.

D0 - D15 Data Input/Output Ports

These 16 bi-directional ports are used to read data from or write data into the RAM.

Vcc

Power Supply

Gnd

Ground

MODE

CE1

CE2

D0~D7

D8~D15

Vcc CURRENT

High Z

CCSB

, I

CCSB1

Not selected

(Power Down)

High Z

CCSB

, I

CCSB1

Output Disabled

High Z

Dout

High Z

Dout

Read

Dout

High Z

Din

Write

Din

Input
Capacitance

=0V

Input/Output
Capacitance

I/O

=0V

RANGE

AMBIENT

TEMPERATURE

Vcc

Commercial

C to +70

1.8V ~ 2.3V

Industrial

-40

C to +85

1.8V ~ 2.3V

ABSOLUTE MAXIMUM RATINGS

(1)

OPERATING RANGE

CAPACITANCE

(1)

(TA = 25

C, f = 1.0 MHz)

1. Stresses greater than those listed under ABSOLUTE MAXIMUM

RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.

1. This parameter is guaranteed and not tested.

SYMBOL

PARAMETER

RATING

UNITS

TERM

Terminal Voltage with
Respect to GND

-0.5 to

Vcc+0.5

BIAS

Temperature Under Bias

-40 to +125

STG

Storage Temperature

-60 to +150

Power Dissipation

1.0

OUT

DC Output Current

SYMBOL

PARAMETER

CONDITIONS

MAX.

UNIT

Revision 2.2
April 2001

R0201-BS616UV1610

SYMBOL

PARAMETER

TEST CONDITIONS

MIN. TYP.

(1)

MAX.

UNITS

Vcc for Data Retention

CE1

Vcc - 0.2V or CE2 0.2V

Vcc - 0.2V or V

0.2V

1.5

CCDR

Data Retention Current

CE1

Vcc - 0.2V or CE2 0.2V

Vcc - 0.2V or V

0.2V

0.8

CDR

Chip Deselect to Data
Retention Time

Operation Recovery Time

See Retention Waveform

(2)

1. Typical characteristics are at TA = 25

2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.
3. Fmax = 1/t

DATA RETENTION CHARACTERISTICS

( TA = 0 to + 70

C )

1. Vcc = 1.5V, T

= + 25

2. t

= Read Cycle Time

DC ELECTRICAL CHARACTERISTICS

( TA = 0 to + 70

C )

BSI

BS616UV1610

LOW V

DATA RETENTION WAVEFORM (1)

( CE1 Controlled )

CE1

Data Retention Mode

Vcc

CDR

Vcc

Vcc

1.5V

CE1 Vcc - 0.2V

LOW V

DATA RETENTION WAVEFORM (2)

( CE2 Controlled )

CE2

Data Retention Mode

Vcc

CDR

Vcc

Vcc

1.5V

CE2

0.2V

PARAMETER

NAME

PARAMETER

TEST CONDITIONS

MIN. TYP.

(1)

MAX.

UNITS

Guaranteed Input Low
Voltage

(2)

Vcc=2V

-0.5

0.6

Guaranteed Input High
Voltage

(2)

Vcc=2V

1.4

Vcc+0.2

Input Leakage Current

= 0V to Vcc

Vcc = Max, V

Output Leakage Current

Vcc = Max, CE1 = V
OE = V , V = 0V to

, or CE2 = V

, or

I/O

Vcc

Output Low Voltage

= 1mA

Vcc = Max, I

Vcc=2V

0.4

Output High Voltage

= -0.5mA

Vcc = Min, I

Vcc=2V

1.6

Operating Power Supply
Current

CE2 =

Vcc=2V

Vcc= max, CE1 = V

, I

= 0mA, F =

and

Fmax

(3)

CCSB

Standby Current-TTL

Vcc= max, CE1 = V

or CE2 =

, I

= 0mA

Vcc=2V

0.8

CCSB1

Standby Current-

Vcc-0.2V, or

0.2V, V

Vcc - 0.2V

0.2V

Vcc=2V

CMOS

CE2
or V

Vcc= max,CE1

1.2

Revision 2.2
April 2001

R0201-BS616UV1610

Input Pulse Levels
Input Rise and Fall Times
Input and Output
Timing Reference Level

Vcc/0V
5ns

0.5Vcc

AC ELECTRICAL CHARACTERISTICS

( TA = 0 to + 70

C, Vcc=2V)

READ CYCLE

AC TEST CONDITIONS

AC TEST LOADS AND WAVEFORMS

KEY TO SWITCHING WAVEFORMS

WAVEFORM

INPUTS

OUTPUTS

MUST BE
STEADY

MAY CHANGE
FROM H TO L

DON T CAR
ANY CHANG
PERMITTED

CHANGE :

STATE

DOES NOT
APPLY

MUST BE
STEADY

WILL BE
CHANGE
FROM H TO L

UNKNOWN

CENTER
LINE IS HIGH
IMPEDANCE
"OFF "STATE

MAY CHANGE
FROM L TO H

WILL BE
CHANGE
FROM L TO H

BSI

BS616UV1610

JEDEC

PARAMETER

NAME

PARAMETER

NAME

DESCRIPTION

BS616UV1610-70

MIN. TYP. MAX.

BS616UV1610-100
MIN. TYP. MAX.

UNIT

AVAX

Read Cycle Time

100

AVQV

Address Access Time

100

ELQV

ACS1

Chip Select Access Time

(CE1)

100

ELQV

ACS2

Chip Select Access Time

(CE2)

100

Data Byte Control Access Time

(LB,UB)

GLQV

Output Enable to Output Valid

ELQX

CLZ

Chip Select to Output Low Z

(CE2,CE1)

Data Byte Control to Output Low Z

(LB,UB)

GLQX

OLZ

Output Enable to Output in Low Z

EHQZ

CHZ

Chip Deselect to Output in High Z

(CE2,CE1)

BDO

Data Byte Control to Output High Z

(LB,UB)

GHQZ

OHZ

Output Disable to Output in High Z

AXOX

Output Disable to Address Change

800

THEVENIN EQUIVALENT

ALL INPUT PULSES

10%

90%

Vcc

GND

5ns

90%

10%

1.2V

OUTPUT

FIGURE 2

OUTPUT

INCLUDING
JIG AND
SCOPE

1333

2000

5PF

FIGURE 1B

OUTPUT

INCLUDING
JIG AND
SCOPE

1333

100PF

FIGURE 1A

2000

Revision 2.2
April 2001

R0201-BS616UV1610

BSI

BS616UV1610

SWITCHING WAVEFORMS (READ CYCLE)

READ CYCLE1

(1,2,4)

OUT

ADDRESS

NOTES:
1. WE is high in read Cycle.
2. Device is continuously selected when CE1 = V

and CE2 = V

IH.

3. Address valid prior to or coincident with CE transition low.
4. OE = V

5. Transition is measured 500mV from steady state with C

= 5pF as shown in Figure 1B.

The parameter is guaranteed but not 100% tested.

READ CYCLE2

(1,3,4)

CLZ

CHZ

(5)

OUT

CE1

(5)

ACS1

CE2

ACS2

READ CYCLE3

(1,4)

OUT

LB,UB

CE1

ADDRESS

CLZ

(5)

ACS1

CHZ

(1,5)

OHZ

(5)

OLZ

BDO

CE2

ACS2

Revision 2.2
April 2001

R0201-BS616UV1610

AC ELECTRICAL CHARACTERISTICS

( TA = 0 to + 70

C, Vcc=2V)

WRITE CYCLE

SWITCHING WAVEFORMS (WRITE CYCLE)

BSI

BS616UV1610

JEDEC

PARAMETER

NAME

PARAMETER

NAME

DESCRIPTION

BS616UV1610-70

MIN. TYP. MAX.

BS616UV1610-10

MIN. TYP. MAX.

UNIT

AVAX

Write Cycle Time

100

E1LWH

Chip Select to End of Write

100

AVWL

Address Setup Time

AVWH

Address Valid to End of Write

100

WLWH

Write Pulse Width

WHAX

WR1

Write recovery Time

(CE2,CE1,WE)

Date Byte Control to End of Write

(LB,U )

WLQZ

WHZ

Write to Output in High Z

DVWH

Data to Write Time Overlap

WHDX

Data Hold from Write Time

GHQZ

OHZ

Output Disable to Output in High Z

WHOX

End of Write to Output Active

WRITE CYCLE1

(1)

(3)

(11)

(2)

OHZ

(4,10)

(3)

OUT

CE1

ADDRESS

(5)

CE2

(5)

LB,UB

Revision 2.2
April 2001

R0201-BS616UV1610

BSI

BS616UV1610

NOTES:
1. WE must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE2, CE1 and WE low. All signals

must be active to initiate a write and any one signal can terminate a write by going inactive.
The data input setup and hold timing should be referenced to the second transition edge of
the signal that terminates the write.

3. T

is measured from the earlier of CE2 going low, or CE1 or WE going high at the end of write cycle.

4. During this period, DQ pins are in the output state so that the input signals of opposite phase

to the outputs must not be applied.

5. If the CE2 high transition or CE1 low transition occurs simultaneously with the WE low transitions or after the WE

transition, output remain in a high impedance state.

6. OE is continuously low (OE = V

7. D

OUT

is the same phase of write data of this write cycle.

8. D

OUT

is the read data of next address.

9. If CE2 is high or CE1 is low during this period, DQ pins are in the output state. Then the data input signals of

opposite phase to the outputs must not be applied to them.

10. Transition is measured 500mV from steady state with C

= 5pF as shown in Figure 1B.

The parameter is guaranteed but not 100% tested.

11. T

is measured from the later of CE2 going high or CE1 going low to the end of write.

WRITE CYCLE2

(1,6)

(11)

(2)

WHZ

(4,10)

(3)

OUT

CE1

ADDRESS

(7)

(8)

(8,9)

CE2

LB,UB

(5)

Revision 2.2
April 2001

BS616UV1610

BSI

R0201-BS616UV1610

PACKAGE
B :BGA - 48 PIN(8x10mm)
F :BGA - 48 PIN(9x12mm)

ORDERING INFORMATION

BS616UV1610

X X -- Y Y

GRADE
C: +0

C ~ +70

I: -40

C ~ +85

SPEED
70: 70ns
10: 100ns

PACKAGE DIMENSIONS

48 mini-BGA (8 x 10mm)

.
1

3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS.

1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS.
2: PIN#1 DOT MARKING BY LASER OR PAD PRINT.

N E

NOTES:

10.0

8.0

3.75

5.25

0.75

SIDE VIEW

D 0.1

1.4 M

x
.

0.25

0.05

SOLDER BALL

0.35

0.05

VIEW A

Part Number BS616UV1610