Revision 1.1
Jan. 2004

A4
A3
A2
A1
A0

DQ0
DQ1
DQ2
DQ3

VCC

GND

DQ4
DQ5
DQ6
DQ7

A17
A16
A15
A14
A13

A5
A6
A7
OE
UB
LB
DQ15
DQ14
DQ13
DQ12
GND
VCC
DQ11
DQ10
DQ9
DQ8
NC
A8
A9
A10
A11
A12

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23

BS616LV4016EC
BS616LV4016EI

R0201-BS616LV4016

POWER DISSIPATION

SPEED

(

ns )

STANDBY

( I

CCSB1

, Max )

( I

, Max )

PRODUCT FAMILY

OPERATING

TEMPERATURE

Vcc

RANGE

3.0V

PKG

TYPE

BS616LV4016DC

DICE

BS616LV4016EC

TSOP2-44

BS616LV4016AC

BGA-48-0608

C to +70

2.4V

~ 3.6V

55 / 70

6.0uA

25mA

BS616LV4016DI

DICE

BS616LV4016EI

TSOP2-44

BS616LV4016AI

BGA-48-0608

-40

C to +85

2.4V

~ 3.6V

55 / 70

8.0uA

27mA

Very Low Power/Voltage CMOS SRAM
256K X 16 bit

· Wide Vcc operation voltage :

2.4V

~ 3.6V

· Very low power consumption :

Vcc = 3.0V C-grade: 25mA (@55ns) operating current

I -grade: 27mA (@55ns) operating current

C-grade: 17mA (@70ns) operating current

I -grade: 18mA (@70ns) operating current

0.45uA (Typ.)

CMOS standby current

· High speed access time :

-55 55ns (Max.) at Vcc = 2.7~3.6V / 85

-70 70ns (Max.) at Vcc = 2.4~3.6V / 85

· Automatic power down when chip is deselected
· Three state outputs and TTL compatible
· Fully static operation
· Data retention supply voltage as low as

1.5V

The BS616LV4016 is a high performance, very low power CMOS Static
Random Access Memory organized as 262,144 words by 16 bits and
operates from a wide range of

2.4V

to 3.6V supply voltage.

Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current of

0.45uA

3.0V/25

and maximum access time of

55ns

2.7V/85

Easy memory expansion is provided by an active LOW chip enable (CE)
,active LOW output enable(OE) and three-state output drivers.
The BS616LV4016 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS616LV4016 is available in DICE form , JEDEC standard 44-pin
TSOP Type II package and 48-ball BGA package.

DESCRIPTION

FEATURES

Row

Decoder

Memory Array

2048 x 2048

Column I/O

Write Driver

Sense Amp

Column Decoder

Data

Buffer

Output

A9 A8 A7

Data

Buffer

Input

Control

Gnd

Vcc

DQ15

DQ0

A13

A14

A15

128

2048

BLOCK DIAGRAM

2048

A17
A16

A10

A12

A11

Address

Input

Buffer

Address Input Buffer

.
.
.
.

PRODUCT FAMILY

PIN CONFIGURATIONS

Brilliance Semiconductor, Inc

. reserves the right to modify document contents without notice.

BS616LV4016

BSI

Operating

· Easy expansion with CE and OE options
· I/O Configuration x8/x16 selectable by LB and UB pin

Vcc =

17mA

18mA

55ns

70ns

55ns:

2.7~3.6V

70ns:

2.4~3.6V

Revision 1.1
Jan. 2004

R0201-BS616LV4016

Name

Function

A0-A17 Address Input

These 18 address inputs select one of the 262,144 x 16-bit words in the RAM.

CE Chip Enable Input

CE is active LOW. Chip enables must be active when data read from or write to the
device. if chip enable is not active, the device is deselected and is in a standby power
mode. The DQ pins will be in the high impedance state when the device is deselected.

WE Write Enable Input

The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.

OE Output Enable Input

The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impedance state when OE is inactive.

LB and UB Data Byte Control Input

Lower byte and upper byte data input/output control pins.

DQ0 - DQ15 Data Input/Output
Ports

These 16 bi-directional ports are used to read data from or write data into the RAM.

Vcc

Power Supply

Gnd

Ground

TRUTH TABLE

PIN DESCRIPTIONS

BSI

BS616LV4016

MODE

D0~D7

D8~D15

Vcc CURRENT

High Z

CCSB

, I

CCSB1

Not selected

(Power Down)

High Z

CCSB

, I

CCSB1

Output Disabled

High Z

Dout

High Z

Dout

Read

Dout

High Z

Din

Write

Din

High Z

Revision 1.1
Jan. 2004

Input
Capacitance

=0V

Input/Output
Capacitance

I/O

=0V

RANGE

AMBIENT

TEMPERATURE

Vcc

Commercial

C to +70

2.4V

~ 3.6V

Industrial

-40

C to +85

2.4V

~ 3.6V

1. Typical characteristics are at TA = 25

2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.
3. Fmax = 1/t

4. I

SB1_max.

is 6uA @Vcc=3.0V during 0

C~70

5. Icc

_Max.

is 25mA(@55ns) / 17mA(@70ns) at Vcc=3.0V/ 0~70

ABSOLUTE MAXIMUM RATINGS

(1)

OPERATING RANGE

CAPACITANCE

(1)

(TA = 25

C, f = 1.0 MHz)

1. Stresses greater than those listed under ABSOLUTE MAXIMUM

RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
reliability.

1. This parameter is guaranteed and not 100% tested.

DC ELECTRICAL CHARACTERISTICS

( TA = -40 to + 85

C )

SYMBOL

PARAMETER

RATING

UNITS

TERM

Terminal Voltage with
Respect to GND

-0.5 to

Vcc+0.5

BIAS

Temperature Under Bias

-40 to +85

STG

Storage Temperature

-60 to +150

Power Dissipation

1.0 W

OUT

DC Output Current

BSI

BS616LV4016

PARAMETER

NAME

PARAMETER

TEST CONDITIONS

MIN. TYP.

(1)

MAX.

UNITS

Guaranteed Input Low
Voltage

(2)

-0.3

Guaranteed Input High

Voltage

(2)

Vcc+0.3

Input Leakage Current

Vcc = Max, V

= 0V to Vcc

Output Leakage Current

Vcc = Max, CE = V

, or OE = V

I/O

= 0V to Vcc

Output Low Voltage

Output High Voltage

Operating Power

Supply Current

CE=V

= 0mA,

F=Fmax

(3)

CCSB

Standby Current-TTL

CE = V

, I

= 0mA

CCSB1

Standby Current-CMOS

CE Vcc-0.2V,

Vcc - 0.2V or V

0.2V

SYMBOL

PARAMETER

CONDITIONS

MAX.

UNIT

R0201-BS616LV4016

0.45

Vcc=3.0V

2.0

Vcc

=3.0V

Vcc=3.0V

0.8

2.4

1.0

0.4

Vcc = Max, I

= 2.0mA

Vcc = Min, I

= -1.0mA

(4)

70ns

55ns

(5)

Revision 1.1
Jan. 2004

BSI

BS616LV4016

SYMBOL

PARAMETER

TEST CONDITIONS

MIN. TYP.

(1)

MAX.

UNITS

Vcc for Data Retention

CE Vcc - 0.2V
V

Vcc - 0.2V or V

0.2V

1.5

CCDR

Data Retention Current

CE Vcc - 0.2V
V

Vcc - 0.2V or V

0.2V

0.15

1.7

CDR

Chip Deselect to Data
Retention Time

Operation Recovery Time

See Retention Waveform

(2)

DATA RETENTION CHARACTERISTICS

( TA = -40 to + 85

C )

1. Vcc =

1.5V

, T

= + 25

2. t

= Read Cycle Time

3. I

(Max.) is 1.2uA at T

=70

R0201-BS616LV4016

LOW V

DATA RETENTION WAVEFORM

( CE Controlled )

Data Retention Mode

Vcc

CDR

Vcc

Vcc

1.5V

CE Vcc - 0.2V

(3)

Revision 1.1
Jan. 2004

R0201-BS616LV4016

AC ELECTRICAL CHARACTERISTICS

( TA = -40 to + 85

C )

READ CYCLE

AC TEST CONDITIONS

(Test Load and Input/Output Reference)

KEY TO SWITCHING WAVEFORMS

WAVEFORM

INPUTS

OUTPUTS

MUST BE
STEADY

MAY CHANGE
FROM H TO L

DON T CARE:
ANY CHANGE
PERMITTED

DOES NOT
APPLY

MUST BE
STEADY

WILL BE
CHANGE
FROM H TO L

CHANGE :
STATE
UNKNOWN

CENTER
LINE IS HIGH
IMPEDANCE
"OFF "STATE

MAY CHANGE
FROM L TO H

WILL BE
CHANGE
FROM L TO H

BSI

BS616LV4016

Input Pulse Levels

Vcc / 0V

Input Rise and Fall Times

1V/ns

Input and Output
Timing Reference Level

0.5Vcc

Output Load

= 30pF+1TTL

= 100pF+1TTL

JEDEC

PARAMETER

NAME

PARAMETER

NAME

DESCRIPTION

CYCLE TIME : 55ns

(Vcc = 2.7~3.6V)

(Vcc = 2.4~3.6V)

UNIT

AVAX

Read Cycle Time

AVQV

Address Access Time

ELQV

ACS

Chip Select Access Time

Data Byte Control Access Time

(LB,UB)

GLQV

Output Enable to Output Valid

E1LQX

CLZ

Chip Select to Output Low Z

Data Byte Control to Output Low Z

(LB,UB)

GLQX

OLZ

Output Enable to Output in Low Z

EHQZ

CHZ

Chip Deselect to Output in High Z

BDO

Data Byte Control to Output High Z

(LB,UB)

GHQZ

OHZ

Output Disable to Output in High Z

AXOX

Data Hold from Address Change

(1)

NOTE :

MIN. TYP. MAX.

1. t

is 30ns/35ns (@speed=55ns/70ns) with address toggle. ; t

is 55ns/70ns (@speed=55ns/70ns) without address toggle.

CYCLE TIME : 70ns

Revision 1.1
Jan. 2004

R0201-BS616LV4016

BSI

BS616LV4016

NOTES:
1. WE is high in read Cycle.
2. Device is continuously selected when CE = V

3. Address valid prior to or coincident with CE transition low.
4. OE = V

5. The parameter is guaranteed but not 100% tested.

READ CYCLE3

(1,4)

OUT

LB,UB

ADDRESS

CLZ

ACS

CHZ

(1,5)

OHZ

OLZ

READ CYCLE2

(1,3,4)

CLZ

CHZ

OUT

LB,UB

ACS

BDO

(5)

SWITCHING WAVEFORMS (READ CYCLE)

READ CYCLE1

(1,2,4)

OUT

ADDRESS

Revision 1.1
Jan. 2004

R0201-BS616LV4016

BSI

BS616LV4016

SWITCHING WAVEFORMS (WRITE CYCLE)

WRITE CYCLE1

(1)

(3)

(10)

(2)

OHZ

(4,11)

(3)

OUT

LB,UB

ADDRESS

(5)

AC ELECTRICAL CHARACTERISTICS

( TA = -40 to + 85

C )

JEDEC

PARAMETER

NAME

PARAMETER

NAME

DESCRIPTION

CYCLE TIME : 55ns

(Vcc = 2.7~3.6V)

(Vcc = 2.4~3.6V)

UNIT

AVAX

Write Cycle Time

E1LWH

Chip Select to End of Write

AVWL

Address Setup Time

AVWH

Address Valid to End of Write

WLWH

Write Pulse Width

WHAX

Write recovery Time

(CE,WE)

Date Byte Control to End of Write

(LB,UB)

WLQZ

WHZ

Write to Output in High Z

DVWH

Data to Write Time Overlap

WHDX

Data Hold from Write Time

GHQZ

OHZ

Output Disable to Output in High Z

WHOX

End of Write to Output Active

WRITE CYCLE

1. t

is 25ns/30ns (@speed=55ns/70ns) with address toggle. ; t

is 55ns/70ns (@speed=55ns/70ns) without address toggle.

(1)

NOTE :

MIN. TYP. MAX.

CYCLE TIME : 70ns

Revision 1.1
Jan. 2004

R0201-BS616LV4016

WRITE CYCLE2

(1,6)

BSI

BS616LV4016

(10)

(2)

WHZ

(4,11)

(3)

OUT

ADDRESS

(5)

(7)

(8)

(8,9)

LB,UB

NOTES:
1. WE must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE and WE low. All signals

must be active to initiate a write and any one signal can terminate a write by going inactive.
The data input setup and hold timing should be referenced to the second transition edge of
the signal that terminates the write.

3. T

is measured from the earlier of CE or WE going high at the end of write cycle.

4. During this period, DQ pins are in the output state so that the input signals of opposite phase

to the outputs must not be applied.

5. If the CE low transition occurs simultaneously with the WE low transitions or after the WE

transition, output remain in a high impedance state.

6. OE is continuously low (OE = V

7. D

OUT

is the same phase of write data of this write cycle.

8. D

OUT

is the read data of next address.

9. If CE is low during this period, DQ pins are in the output state. Then the data input signals of

opposite phase to the outputs must not be applied to them.

10. T

is measured from the later of CE going low to the end of write.

11. The parameter is guaranteed but not 100% tested.

Revision 1.1
Jan. 2004

R0201-BS616LV4016

ORDERING INFORMATION

BSI

BS616LV4016

PACKAGE DIMENSIONS

TSOP2-44

Note:
BSI (Brilliance Semiconductor Inc.) assumes no responsibility for the application or use of any product or circuit described herein. BSI does not authorize its products
for use as critical components in any application in which the failure of the BSI product may be expected to result in significant injury or death, including life-support
systems and critical medical instruments.

BS616LV4016 X X

Y Y

GRADE
C: +0

C ~ +70

I: -40

C ~ +85

SPEED
55: 55ns
70: 70ns
PKG MATERIAL
-: Normal
G: Green
P: Pb free

PACKAGE
E: TSOP2-44
A: BGA-48-0608
D: DICE

Part Number BS616LV4016