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Features
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High-density, High-performance, Electrically-erasable Complex
Programmable Logic Device
3.0 to 3.6V Operating Range
64 Macrocells
5 Product Terms per Macrocell, Expandable up to 40 per Macrocell
44, 68, 84, 100 Pins
15 ns Maximum Pin-to-pin Delay
Registered Operation up to 77 MHz
Enhanced Routing Resources
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In-System Programmability (ISP) via JTAG
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Flexible Logic Macrocell
D/T/Latch Configurable Flip-flops
Global and Individual Register Control Signals
Global and Individual Output Enable
Programmable Output Slew Rate
Programmable Output Open-collector Option
Maximum Logic Utilization by Burying a Register with a COM Output
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Advanced Power Management Features
Automatic 5 µA Standby for "L" Version
Pin-controlled 100 µA Standby Mode (Typical)
Programmable Pin-keeper Circuits on Inputs and I/Os
Reduced-power Feature per Macrocell
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Available in Commercial and Industrial Temperature Ranges
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Available in 44-, 68-, and 84-lead PLCC; 44- and 100-lead TQFP; and 100-lead PQFP
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Advanced EE Technology
100% Tested
Completely Reprogrammable
10,000 Program/Erase Cycles
20 Year Data Retention
2000V ESD Protection
200 mA Latch-up Immunity
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JTAG Boundary-scan Testing to IEEE Std. 1149.1-1990 and 1149.1a-1993 Supported
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PCI-compliant
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Security Fuse Feature
Enhanced Features
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Improved Connectivity (Additional Feedback Routing, Alternate Input Routing)
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Output Enable Product Terms
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Transparent-latch Mode
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Combinatorial Output with Registered Feedback within Any Macrocell
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Three Global Clock Pins
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ITD (Input Transition Detection) Circuits on Global Clocks, Inputs and I/O
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Fast Registered Input from Product Term
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Programmable "Pin-keeper" Option
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V
CC
Power-up Reset Option
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Pull-up Option on JTAG Pins TMS and TDI
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Advanced Power Management Features
Edge-controlled Power-down "L"
Individual Macrocell Power Option
Disable ITD on Global Clocks, Inputs and I/O
Low-voltage,
Complex
Programmable
Logic Device
ATF1504ASV
ATF1504ASVL
Rev. 1409IPLD2/03
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ATF1504ASV(L)
1409IPLD2/03
Description
The ATF1504ASV(L) is a high-performance, high-density complex programmable logic
device (CPLD) that utilizes Atmel's proven electrically-erasable memory technology.
With 64 logic macrocells and up to 68 inputs, it easily integrates logic from several TTL,
SSI, MSI, LSI and classic PLDs. The ATF1504ASV(L)'s enhanced routing switch matri-
ces increase usable gate count and the odds of successful pin-locked design
modifications.
The ATF1504ASV(L) has up to 68 bi-directional I/O pins and four dedicated input pins,
depending on the type of device package selected. Each dedicated pin can also serve
as a global control signal, register clock, register reset or output enable. Each of these
control signals can be selected for use individually within each macrocell.
Each of the 64 macrocells generates a buried feedback that goes to the global bus.
Each input and I/O pin also feeds into the global bus. The switch matrix in each logic
block then selects 40 individual signals from the global bus. Each macrocell also gener-
ates a foldback logic term that goes to a regional bus. Cascade logic between
macrocells in the ATF1504ASV(L) allows fast, efficient generation of complex logic func-
tions. The ATF1504ASV(L) contains four such logic chains, each capable of creating
sum term logic with a fan-in of up to 40 product terms.
The ATF1504ASV(L) macrocell, shown in Figure 1, is flexible enough to support highly-
complex logic functions operating at high speed. The macrocell consists of five sections:
product terms and product term select multiplexer, OR/XOR/CASCADE logic, a flip-flop,
output select and enable, and logic array inputs.
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ATF1504ASV(L)
1409IPLD2/03
Block Diagram
Unused product terms are automatically disabled by the compiler to decrease power
consumption. A security fuse, when programmed, protects the contents of the
ATF1504ASV(L). Two bytes (16 bits) of User Signature are accessible to the user for
purposes such as storing project name, part number, revision or date. The User Signa-
ture is accessible regardless of the state of the security fuse.
The ATF1504ASV(L) device is an in-system programmable (ISP) device. It uses the
industry-standard 4-pin JTAG interface (IEEE Std. 1149.1), and is fully-compliant with
JTAG's Boundary-scan Description Language (BSDL). ISP allows the device to be pro-
grammed without removing it from the printed circuit board. In addition to simplifying the
manufacturing flow, ISP also allows design modifications to be made in the field via
software.
Product Terms and Select
Mux
Each ATF1504ASV(L) macrocell has five product terms. Each product term receives as
its inputs all signals from both the global bus and regional bus.
The product term select multiplexer (PTMUX) allocates the five product terms as
needed to the macrocell logic gates and control signals. The PTMUX programming is
determined by the design compiler, which selects the optimum macrocell configuration.
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