2648DATARM03/04
Features
·
Incorporates the ARM7TDMI
®
ARM
®
Thumb
®
Processor Core
High-performance 32-bit RISC Architecture
High-density 16-bit Instruction Set
Leader in MIPS/Watt
Embedded ICE (In-circuit Emulation)
·
256K Bytes of On-chip SRAM (2 Mbits)
32-bit Data Bus, Single-clock Cycle Access
·
256K Words 16-bit Flash Memory (4 Mbits)
Single Voltage Read/Write
Sector Erase Architecture
Low-power Operation
Data Polling, Toggle Bit and Ready/Busy End of Program Cycle Detection
Reset Input for Device Initialization
Factory-programmed AT91 Flash Uploader Software
·
Fully Programmable External Bus Interface (EBI)
Up to Eight Chip Selects, Maximum External Address Space of 64M Bytes
Software Programmable 8/16-bit External Data Bus
·
8-level Priority, Individually Maskable, Vectored Interrupt Controller
Four External Interrupts, Including a High-priority Low-latency Interrupt Request
·
32 Programmable I/O Lines
·
3-channel 16-bit Timer/Counter
Three External Clock Inputs, Two Multi-purpose I/O Pins per Channel
·
Two USARTs
Two Dedicated Peripheral Data Controller (PDC) Channels per USART
·
Programmable Watchdog Timer
·
Advanced Power-saving Features
CPU and Peripherals can be Deactivated Individually
·
Fully Static Operation:
0 Hz to 75 MHz Internal Frequency Range at VDDCORE = 1.65V, 85
°
C
·
2.7V to 3.6V I/O and Flash Operating Range, 1.65V to 1.95V Core Operating Range
·
-40
°
C to 85
°
C Temperature Range
·
Available in a 121-ball 10 x 10 x 1.2 mm BGA Package with 0.8 mm Ball Pitch
Description
The AT91FR4042 is a member of the Atmel AT91 16/32-bit Microcontroller family,
which is based on the ARM7TDMI processor core. The processor has a high-perfor-
mance 32-bit RISC architecture with a high-density 16-bit instruction set and very low
power consumption.
The AT91FR4042 ARM microcontroller features 2 Mbits of on-chip SRAM and 4 Mbits
of Flash memory in a single compact 121-ball BGA package. Its high level of integra-
tion and very small footprint make the device ideal for space-constrained applications.
The high-speed on-chip SRAM enables a performance of up to 63 MIPs and signifi-
cant power reduction over an external SRAM implementation.
The Flash memory may be programmed via the JTAG/ICE interface or the factory-pro-
grammed Flash Uploader using a single device supply, making the AT91FR4042
suitable for in-system programmable applications.
AT91 ARM
®
Thumb
®
Microcontrollers
AT91FR4042
3
AT91FR4042
2648DATARM03/04
Pin Description
Table 1. AT91FR4042 Pin Description
Module
Name
Function
Type
Active
Level
Comments
EBI
A0 - A23
Address Bus
Output
All
Valid after reset
D0 - D15
Data Bus
I/O
NCS0 - NCS3
External Chip Select
Output
Low
Used to select external devices
CS4 - CS7
External Chip Select
Output
High
A23 - A20 after reset
NWR0
Lower Byte 0 Write Signal
Output
Low
Used in Byte Write option
NWR1
Upper Byte 1 Write Signal
Output
Low
Used in Byte Write option
NRD
Read Signal
Output
Low
Used in Byte Write option
NWE
Write Enable
Output
Low
Used in Byte Select option
NOE
Output Enable
Output
Low
Used in Byte Select option
NUB
Upper Byte Select
Output
Low
Used in Byte Select option
NLB
Lower Byte Select
Output
Low
Used in Byte Select option
NWAIT
Wait Input
Input
Low
BMS
Boot Mode Select
Input
Sampled during reset; must be driven low
during reset for Flash to be used as boot
memory
AIC
FIQ
Fast Interrupt Request
Input
PIO-controlled after reset
IRQ0 - IRQ2
External Interrupt Request
Input
PIO-controlled after reset
Timer
TCLK0 - TCLK2
Timer External Clock
Input
PIO-controlled after reset
TIOA0 - TIOA2
Multi-purpose Timer I/O Pin A
I/O
PIO-controlled after reset
TIOB0 - TIOB2
Multi-purpose Timer I/O Pin B
I/O
PIO-controlled after reset
USART
SCK0 - SCK1
External Serial Clock
I/O
PIO-controlled after reset
TXD0 - TXD1
Transmit Data Output
Output
PIO-controlled after reset
RXD0 - RXD1
Receive Data Input
Input
PIO-controlled after reset
PIO
P0 - P31
Parallel IO Line
I/O
WD
NWDOVF
Watchdog Overflow
Output
Low
Open drain
Clock
MCKI
Master Clock Input
Input
Schmidt trigger
MCKO
Master Clock Output
Output
Reset
NRST
Hardware Reset Input
Input
Low
Schmidt trigger
NTRI
Tri-state Mode Select
Input
Low
Sampled during reset
ICE
TMS
Test Mode Select
Input
Schmidt trigger, internal pull-up
TDI
Test Data Input
Input
Schmidt trigger, internal pull-up
TDO
Test Data Output
Output
TCK
Test Clock
Input
Schmidt trigger, internal pull-up
4
AT91FR4042
2648DATARM03/04
Flash
Memory
NCSF
Flash Memory Select
Input
Low
Enables Flash Memory when pulled low
NBUSY
Flash Memory Busy Output
Output
Low
Flash RDY/BUSY signal; open-drain
NRSTF
Flash Memory Reset Input
Input
Low
Resets Flash to standard operating mode
Power
VDDIO
Power
Power
All V
DDIO,
V
DDCORE
and all GND pins
MUST be connected to their respective
supplies by the shortest route
VDDCORE
Power
Power
GND
Ground
Ground
VPP
Power
Power
See AT49BV/LV4096A
4-megabit (256 K x 16/512 K x 8) Single 2.7
Volt Flash Memory Datasheet
Table 1. AT91FR4042 Pin Description (Continued)
Module
Name
Function
Type
Active
Level
Comments
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