VSOP Top View

Type 1

10 x 14 mm

GND

A10

A11

A12

A13

A14

VCC

I/O0

I/O1

I/O2

I/O3

I/O4

I/O5

I/O6

I/07

GND

I/O8

I/O9

I/O10

I/O11

I/O12

I/O13

I/O14

I/O15

10 x 14 mm

PLCC Top View

I/O12

I/O11

I/O10

I/O9

I/O8

GND

I/O7

I/O6

I/O5

I/O4

A13

A12

A11

A10

GND

I/O3

I/O2

I/O1

I/O0

I/O13

I/O14

I/O15

VCC

A14

Features

�

Single Voltage Operation

� 5V Read
� 5V Reprogramming

�

Fast Read Access Time - 55 ns

�

Internal Program Control and Timer

�

8K Word Boot Block With Lockout

�

Fast Erase Cycle Time - 10 seconds

�

Word-By-Word Programming - 10 �s/Word Typical

�

Hardware Data Protection

�

DATA Polling For End Of Program Detection

�

Small 10 x 14 VSOP Package

�

Typical 10,000 Write Cycles

Description

The AT49F516 is a 5-volt only in-system programmable and erasable Flash Memory.
It's 512K of memory is organized as 32,768 words by 16 bits. Manufactured with
Atmel's advanced nonvolatile CMOS technology, the devices offer access times to 55
ns with power dissipation of just 275 mW over the commercial temperature range.
When the device is deselected, the CMOS standby current is less than 100 �A.

Rev. 1089B�10/98

512K (32K x 16)
5-volt Only
Flash Memory

AT49F516
Preliminary

Pin Configurations

Pin Name

Function

A0 - A14

Addresses

Chip Enable

Output Enable

Write Enable

I/O0 - I/O15

Data Inputs/Outputs

No Connect

(continued)

AT49F516

To allow for simple in-system reprogrammability, the
AT49F516 does not require high input voltages for pro-
gramming. Five-volt-only commands determine the read
and programming operation of the device. Reading data
out of the device is similar to reading from an EPROM.
Reprogramming the AT49F516 is performed by erasing a
block of data (entire chip or main memory block) and then
programming on a word by word basis. The typical word
programming time is a fast 10

�

s. The end of a program

cycle can be optionally detected by the DATA polling fea-

ture. Once the end of a byte program cycle has been
detected, a new access for a read or program can begin.
The typical number of program and erase cycles is in
excess of 10,000 cycles.

The optional 8K words boot block section includes a repro-
gramming write lock out feature to provide data integrity.
The boot sector is designed to contain user secure code,
and when the feature is enabled, the boot sector is perma-
nently protected from being erased or reprogrammed.

Block Diagram

Device Operation

READ: The AT49F516 is accessed like an EPROM. When
CE and OE are low and WE is high, the data stored at the
memory location determined by the address pins is
asserted on the outputs. The outputs are put in the high
impedance state whenever CE or OE is high. This dual-line
control gives designers flexibility in preventing bus conten-
tion.

CHIP ERASE: When the boot block programming lockout
feature is not enabled, the boot block and the main memory
block will erase together from the same chip erase com-
mand (See command definitions table). If the boot block
lockout function has been enabled, data in the boot section
will not be erased. However, data in the main memory sec-
tion will be erased. After a chip erase, the device will return
to the read mode.

MAIN MEMORY ERASE: As an alternative to the chip
erase, a main memory block erase can be performed which
will erase all bytes not located in the boot block region to an
FFH. Data located in the boot region will not be changed
during a main memory block erase. The Main Memory
Erase command is a six bus cycle operation. The address
(5555H) is latched on the falling edge of the sixth cycle
while the 30H data input is latched on the rising edge of
WE. The main memory erase starts after the rising edge of
WE of the sixth cycle. Please see Main Memory Erase

cycle waveforms. The Main Memory Erase operation is
internally controlled; it will automatically time to completion.

WORD PROGRAMMING: Once the memory array is
erased, the device is programmed (to a logical "0") on a
word-by-word basis. Please note that a data "0" cannot be
programmed back to a "1"; only erase operations can con-
vert "0"s to "1"s. Programming is accomplished via the
internal device command register and is a 4 bus cycle
operation (please refer to the Command Definitions table).
The device will automatically generate the required internal
program pulses.

The program cycle has addresses latched on the falling
edge of WE or CE, whichever occurs last, and the data
latched on the rising edge of WE or CE, whichever occurs
first. Programming is completed after the specified t

cycle

time. The DATA polling feature may also be used to indicate
the end of a program cycle.

BOOT BLOCK PROGRAMMING LOCKOUT: The device
has one designated block that has a programming lockout
feature. This feature prevents programming of data in the
designated block once the feature has been enabled. The
size of the block is 8K words. This block, referred to as the
boot block, can contain secure code that is used to bring up
the system. Enabling the lockout feature will allow the boot
code to stay in the device while data in the rest of the

OE, CE, AND WE

LOGIC

Y DECODER

X DECODER

INPUT/OUTPUT

BUFFERS

DATA LATCH

Y-GATING

OPTIONAL BOOT

BLOCK (8K WORDS)

MAIN MEMORY

(24K WORDS)

ADDRESS

INPUTS

VCC

GND

DATA INPUTS/OUTPUTS

I/O15 - I/O0

1FFFH

0000H

2000H

7FFFH

AT49F516

device is updated. This feature does not have to be acti-
vated; the boot block's usage as a write protected region is
optional to the user. The address range of the boot block is
0000H to 1FFFH.

Once the feature is enabled, the data in the boot block can
no longer be erased or programmed. Data in the main
memory block can still be changed through the regular pro-
gramming method and can be erased using either the chip
erase or the main memory block erase command. To acti-
vate the lockout feature, a series of six program commands
to specific addresses with specific data must be performed.
Please refer to the Command Definitions table.

BOOT BLOCK LOCKOUT DETECTION: A software
method is available to determine if programming of the boot
block section is locked out. When the device is in the soft-
ware product identification mode (see Software Product
Identification Entry and Exit sections) a read from address
location 0002H will show if programming the boot block is
locked out. If the data on I/O0 is low, the boot block can be
programmed; if the data on I/O0 is high, the program lock-
out feature has been activated and the block cannot be
programmed. The software product identification exit code
should be used to return to standard operation.

PRODUCT IDENTIFICATION: The product identification
mode identifies the device and manufacturer as Atmel. It
may be accessed by hardware or software operation. The
hardware operation mode can be used by an external pro-

grammer to identify the correct programming algorithm for
the Atmel product.

For details, see Operating Modes (for hardware operation)
or Software Product Identification. The manufacturer and
device code is the same for both modes.

DATA POLLING: The AT49F516 features DATA polling to
indicate the end of a program or erase cycle. During a pro-
gram cycle an attempted read of the last byte loaded will
result in the complement of the loaded data on I/O7. Once
the program cycle has been completed, true data is valid
on all outputs and the next cycle may begin. DATA polling
may begin at any time during the program cycle.

TOGGLE BIT: In addition to DATA polling the AT49F516
provides another method for determining the end of a pro-
gram or erase cycle. During a program or erase operation,
successive attempts to read data from the device will result
in I/O6 toggling between one and zero. Once the program
cycle has completed, I/O6 will stop toggling and valid data
will be read. Examining the toggle bit may begin at any time
during a program cycle.

HARDWARE DATA PROTECTION: Hardware features
protect against inadvertent programs to the AT49F516 in
the following ways: (a) V

sense: if V

is below 3.8V (typ-

ical), the program function is inhibited. (b) Program inhibit:
holding any one of OE low, CE high or WE high inhibits
program cycles. (c) Noise filter: Pulses of less than 15 ns
(typical) on the WE or CE inputs will not initiate a program
cycle.

AT49F516

Notes:

1. The DATA FORMAT in each bus cycle is as follows: I/O15 - I/O8 (Don't Care); I/O7 - I/O0 (Hex).

2. The 8K word boot sector has the address range 00000H to 1FFFH.

3. Either one of the Product ID Exit commands can be used.

Command Definition (in Hex)

(1)

Command
Sequence

Bus
Cycles

1st Bus

Cycle

2nd Bus

Cycle

3rd Bus

Cycle

4th Bus

Cycle

5th Bus

Cycle

6th Bus

Cycle

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Read

Addr

OUT

Chip Erase

5555

2AAA

5555

2AAA

5555

Main Memory Erase

5555

2AAA

5555

2AAA

5555

Word Program

5555

2AAA

5555

Addr

Boot Block Lockout

(2)

5555

2AAA

5555

2AAA

5555

Product ID Entry

5555

2AAA

5555

Product ID Exit

(3)

5555

2AAA

5555

Product ID Exit

(3)

xxxx

Absolute Maximum Ratings*

Temperature Under Bias ................................ -55

�

C to +125

�

*NOTICE:

Stresses beyond those listed under "Absolute
Maximum Ratings" may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.

Storage Temperature ..................................... -65

�

C to +150

�

All Input Voltages
(including NC Pins)
with Respect to Ground ...................................-0.6V to +6.25V

All Output Voltages
with Respect to Ground .............................-0.6V to V

+ 0.6V

Voltage on OE
with Respect to Ground ...................................-0.6V to +13.5V

AT49F516

Notes:

1. X can be V

or V

2. Refer to AC Programming Waveforms.

3. V

= 12.0V

�

0.5V.

4. Manufacturer Code: 1FH, Device Code: 100001XX (binary).

5. See details under Software Product Identification Entry/Exit.

Note:

1. In the erase mode, I

is 90 mA.

DC and AC Operating Range

AT49F516-55

AT49F516-70

AT49F516-90

Operating
Temperature (Case)

Com.

0�C - 70�C

Ind.

-40�C - 85�C

Power Supply

�

10%

�

10%

�

10%

Operating Modes

Mode

I/O

Read

OUT

Program

(2)

Standby/Write Inhibit

(1)

High Z

Program Inhibit

Output Disable

High Z

Product Identification

Hardware

A1 - A14 = V

, A9 = V

(3)

, A0 = V

Manufacturer Code

(4)

A1 - A14 = V

, A9 = V

(3)

, A0 = V

Device Code

(4)

Software

(5)

A0 = V

, A1 - A14 = V

Manufacturer Code

(4)

A0 = V

, A1 - A14 = V

Device Code

(4)

DC Characteristics

Symbol

Parameter

Condition

Min

Max

Units

Input Load Current

= 0V to V

�

Output Leakage Current

I/O

= 0V to V

�

SB1

Standby Current CMOS

CE = V

- 0.3V to V

Com.

100

�

Ind.

300

�

SB2

Standby Current TTL

CE = 2.0V to V

(1)

Active Current

f = 5 MHz; I

OUT

= 0 mA

Input Low Voltage

0.8

Input High Voltage

2.0

Output Low Voltage

= 2.1 mA

0.45

OH1

Output High Voltage

= -400

�

2.4

OH2

Output High Voltage CMOS

= -100

�

A; V

= 4.5V

4.2

Part Number AT49F516