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AD120

Preliminary

3-Level / 258 Outputs TFT LCD Gate Driver

PRELIMINARY (August, 2001, Version 0.0)

AMIC Technology, Inc.

Document Title
3-Level / 258 Outputs TFT LCD Gate Driver

Revision History

Rev. No. History

Issue Date

Remark

0.0

Initial issue

August 10, 2001

Preliminary

Important Notice:
AMIC reserves the right to make changes to its products or to discontinue any integrated circuit product or
service without notice. AMIC integrated circuit products are not designed, intended, authorized, or warranted to
be suitable for use in life-support applications, devices or systems or other critical applications. Use of AMIC
products in such applications is understood to be fully at the risk of the customer.

AD120

Preliminary

3-Level / 258 Outputs TFT LCD Gate Driver

PRELIMINARY (August, 2001, Version 0.0)

AMIC Technology, Inc

Features

TFT LCD gate driver

3-level / 258 outputs

40V max. for each output

-15V min. for each output

2.7V~3.6V logic input/output level

Bi-directional data shift control

Output waveform control

TCP available

AD120 is a gate driver for TFT LCD panel. There are 258 outputs in the chip. Three-level output allows voltage correction for
better switching noise rejection. It can be used for XGA / SXGA panels.

Block Diagram

Shift Register

Decoder

Output

.........

ST1X

ST2X

.........

ST2

ST1

XOFF

XON

OGW

VOFF

VDD

VSS

OUT0 OUT1 OUT2

OUT255 OUT256 OUT257

R/L

AD120

PRELIMINARY (August, 2001, Version 0.0)

AMIC Technology, Inc

TCP Pinout

18
19
20
21
22

275

274

273

272

271

......................................................................

OUT254

OUT257

OUT253

OUT255
OUT256

OUT1

OUT4

OUT0

OUT2
OUT3

.......................................................................

VOFF

ST1
ST2

VSS

VDD

XOFF

XON

R/L

OGW
ST2X
ST1X

VOFF

AD120

PRELIMINARY (August, 2001, Version 0.0)

AMIC Technology, Inc

Input/Output Pin Function

Pin No.

Symbol

I/O

Description

Clock pulse

Right / left direction control for shift register
When

R /L

is LOW, data are shifted to the right, or ST1 / ST2 output0 output1

.... output257.

When R /L

is HIGH, data are shifted to the left, or ST1X / ST2X

output257

output256

...

output0.

XON

XON to

force all the outputs to VH voltage.

It is not synchronous to CP.

XOFF

XOFF to

force all the outputs to VOFF voltage.

It is not synchronous to CP.

OGW

Output Gate pulse Width to select output_waveform format.

4,5,

13,14

ST1, ST2,

ST1X, ST2X

I/O

When

R /L

is LOW, ST1 / ST2 are defined as inputs while ST1X / ST2X are defined

as outputs .
The synchronized ST1 / ST2 signals are placed at ST1X / ST2X after 256 CP pulses.
When

R /L

is HIGH, ST1X / ST2X are defined as inputs, while ST1/ST2 are defined

as outputs.
The synchronized ST1X / ST2X signals are placed at ST1 / ST2 after 256 CP pulses.

18 - 275

OUT0~

OUT257

Output drivers
These outputs are synchronized to CP pulses.
The output format and voltage level are controlled by OGW,

XON

XOFF

, ST1 /

ST2, ST1X / ST2X and

R /L

correspondingly as shown in the diagram.

VSS

PWR Reference voltage

VDD

PWR Supply voltage for logic operation

VDD and VSS are voltage levels of input / output logic signals

3, 15

PWR High voltage for output drivers

1, 17

PWR Low voltage for output drivers

2, 16

VOFF

PWR OFF voltage for output drivers

AD120

PRELIMINARY (August, 2001, Version 0.0)

AMIC Technology, Inc

Description

Operation

Output signals OUT0~OUT257 are used for control of the TFT gates of the LCD panel. A bi-directional shift register is
implemented to sequentially output signals OUT0~OUT257. A clock pulse CP is applied to the bi-directional shift register and
the direction of the register is controlled by

R /L

signal.

When

R /L

is LOW and either starting signal ST1 or ST2 goes to HIGH, the shift register starts shifting from OUT0 to OUT257.

The voltages of the corresponding outputs switch to VH, VL or VOFF depending on the starting signals as shown in the
diagram. The outputs of the starting signals ST1X / ST2X switch accordingly after 256 CP pulses following start of the shift
register which allows expansion of the outputs by cascading more devices.
When

R /L

is HIGH and either starting signal ST1X or ST2X goes to HIGH, the shift register starts shifting from OUT257 to

OUT0. The voltages of the corresponding outputs switch to VH, VL or VOFF depending on the starting signals as shown in the
diagram. The outputs of the starting signals ST1/ST2 switch accordingly after 256 CP pulses following start of the shift register
which allows expansion of the outputs by cascading more devices.

3-Level Output

- V

= 40V(max.)

OFF

- V

= 0~10V

- V

= 17~28V

OUT

Level

OFF

AD120

PRELIMINARY (August, 2001, Version 0.0)

AMIC Technology, Inc

Operation Diagram 1 (

/L = L, OGW = L)

~ ~

ST1

ST2

OUT0

OUT1

OUT2

OUT3

OUT256

OUT257

ST1X

ST2X

OFF

256

257

AD120

PRELIMINARY (August, 2001, Version 0.0)

AMIC Technology, Inc

Table 1. Function of XON

and

XOFF

XON

XOFF

OUT0~OUT257

VOFF

Table2

* The outputs are asynchronous to CP.

Table 2. Control of OUT1~OUT256

( XON

= H,

XOFF

= H)

(

/L = L) ST1

ST2

(

/L = H) ST1X

ST2X

OGW

OUT1~OUT256

VOFF

VH (CP = "L")

VL (CP = "H")

* The outputs are synchronous to CP.

Table 3. Control of OUT0 and OUT257

( XON

= H,

XOFF

= H)

(

/L = L) ST1

ST2

OUT0

(

/L = H) ST1X

ST2X

OUT257

VOFF

* The outputs are synchronous to CP.

AD120

PRELIMINARY (August, 2001, Version 0.0)

AMIC Technology, Inc

Absolute Maximum Ratings Over Operating Free-air Temperature Range

Parameter

Symbol

Ratings

Unit

Supply Voltage

VDD

-0.3 ~ +7.0

Supply Voltage

-0.3 ~ 42.0

Supply Voltage

-20.0 ~ +0.3

Supply Voltage

VOFF

VL-0.3 ~ VL+11.0

Supply Voltage

VH - VL

-0.3 ~ 42.0

Input Voltage

VIN

-0.3 ~ VDD+0.3

Storage Temperature

Tstg

-55 ~ 125

°C

Power_on Sequence and Voltage Levels

OFF

Logic Signal

Out0~Out257

Operating Voltage Range

Parameter

Symbol

Min.

Typ.

Max.

Unit

Supply Voltage

2.7

3.3

3.6

Supply Voltage

-15

-5

Supply Voltage

OFF

- V

10.0

Supply Voltage

- V

Clock Frequency

100

KHz

Operating Free-air Temperature

-20

+75

°C

AD120

PRELIMINARY (August, 2001, Version 0.0)

AMIC Technology, Inc

DC Charactertics

(VDD = 2.7~3.6V, Ta = -20~75°C)

Parameter

Symbol

Condition

Min.

Max.

Unit

Applicable Pin

Note

Low Level Input Voltage

VSS

0.2 X VDD

All input pins

High Level Input Voltage

0.8 X VDD

VDD

All input pins

Low Level Output Voltage

= 40µA

VSS

VSS + 0.4

High Level Output Voltage

= 40µA

VDD -0.4

VDD

ST1, ST2,

ST1X, ST2X

Output Resistance (1)

OUT

= V

+ 0.5

1000

OUT0~OUT257

Output Resistance (2)

OFF

OUT

= V

OFF

+ 0.5

1000

OUT0~OUT257

Output Resistance (3)

OUT

= V

- 0.5

1000

OUT0~OUT257

Input Current

= VDD / VSS

-5.0

+5.0

µA

All input pins

Operating Current (1)

1500

µA

VDD

1, 2

Operating Current (2)

100

µA

1, 2

Notes:

1. V

= 25V, V

OFF

= 0V, V

= -10V

2. CP = 50KHz

AC Charactertics

(VDD = 2.7~3.6V, Ta = -20~75°C)

Parameter

Symbol

Condition

Min.

Max.

Unit

Clock Frequency

100

KHz

CP High Pulse Width

CPH

µs

CP Low Pulse Width

CPL

µs

Input Rise Time

10% ~ 90%

Input Fall Time

90% ~ 10%

Gate Off Time

WOFF

µs

Data Setup Time

700

Data Hold Time

thd

700

Delay Time 1

tpd1

CL = 20pF

800

Delay Time 2

tpd2

CL = 300pF

1000

Delay Time 3

tpd3

CL = 300pF

1000

Delay Time 4

tpd4

CL = 300pF

1000

Delay Time 5

tpd5

CL = 300pF

1000

AD120

PRELIMINARY (August, 2001, Version 0.0)

AMIC Technology, Inc

Timing Waveform

------------------------------------------------------------------------------------------------------------------------------------------------------------------------

(OGW = H)

0.5 x V

OUT0~257

tpd2

80%

20%

80%

tpd2

OFF

0.5 x V

------------------------------------------------------------------------------------------------------------------------------------------------------------------------

(OGW = L)

0.5 x V

20%

0.5 x V

OUT0~OUT257

tpd2

80%

20%

80%

20%

OFF

ST1,
ST2

STX1,
STX2

OUT0~OUT257

~ ~

CPH

CPL

0.5 x V

256

0.5 x V

257

0.5 x V

thd

0.5 x V

tpd1

tpd2

80%

20%

50%

Input

Output

AD120

PRELIMINARY (August, 2001, Version 0.0)

AMIC Technology, Inc

Timing Waveform (continued)

XOFF

0.5 x V

OUT0~OUT257

0.5 x V

OFF

tpd3

80%

20%

------------------------------------------------------------------------------------------------------------------------------------------------------------------------

XON

0.5 x V

OUT0~OUT257

0.5 x V

tpd4

80%

20%

tpd4

Part Number AD120