Part Number AMD-756

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Preliminary Information

AMD-756

Peripheral Bus Controller

Data Sheet

Publication # 22548

Rev: B

Issue Date: August 1999

TM

Preliminary Information

Trademarks

AMD, the AMD logo, AMD Athlon, and combinations thereof, AMD-750, AMD-751, and AMD-756 are trademarks
of Advanced Micro Devices, Inc.

Microsoft and Windows are registered trademarks of Microsoft Corporation.

Other product names used in this publication are for identification purposes only and may be trademarks of their
respective companies.

© 1999 Advanced Micro Devices, Inc. All rights reserved.

The contents of this document are provided in connection with Advanced Micro
Devices, Inc. ("AMD") products. AMD makes no representations or warranties with
respect to the accuracy or completeness of the contents of this publication and
reserves the right to make changes to specifications and product descriptions at any
time without notice. No license, whether express, implied, arising by estoppel or oth-
erwise, to any intellectual property rights is granted by this publication. Except as
set forth in AMD's Standard Terms and Conditions of Sale, AMD assumes no liability
whatsoever, and disclaims any express or implied warranty, relating to its products
including, but not limited to, the implied warranty of merchantability, fitness for a
particular purpose, or infringement of any intellectual property right.

AMD's products are not designed, intended, authorized or warranted for use as com-
ponents in systems intended for surgical implant into the body, or in other applica-
tions intended to support or sustain life, or in any other application in which the
failure of AMD's product could create a situation where personal injury, death, or
severe property or environmental damage may occur. AMD reserves the right to dis-
continue or make changes to its products at any time without notice.

Table of Contents

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22548B/0--August 1999

AMD-756TM Peripheral Bus Controller Data Sheet

Preliminary Information

Contents

1

Features

1

1.1

PCI-to-ISA Bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.2

Enhanced IDE Controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.3

Universal Serial Bus Controller . . . . . . . . . . . . . . . . . . . . . . . . 4

1.4

Plug-n-Play Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.5

Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2

Overview

7

2.1

PCI-to-ISA Bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.1.1

PCI Bus Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.1.2

PCI Bus Target Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.2

ISA Bus Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.3

EIDE Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.4

Universal Serial Bus (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.5

Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3

Ordering Information

15

4

Signal Descriptions

17

4.1

Signal Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.2

Processor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4.2.1

A20M# (Processor A20 Mask) . . . . . . . . . . . . . . . . . . . . . . . . . 18

4.2.2

CPURST# (Processor Reset) . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4.2.3

FERR# (Floating Point Error) . . . . . . . . . . . . . . . . . . . . . . . . 18

4.2.4

IGNNE# (Ignore Numeric Exception) . . . . . . . . . . . . . . . . . . 19

4.2.5

INIT# (Initialization) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4.2.6

INTR (Processor Interrupt) . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4.2.7

NMI (Non-Maskable Interrupt) . . . . . . . . . . . . . . . . . . . . . . . . 20

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AMD-756TM Peripheral Bus Controller Data Sheet

22548B/0--August 1999

Preliminary Information

4.2.8

SMI# (System Management Interrupt) . . . . . . . . . . . . . . . . . 20

4.2.9

PICCLK (Interrupt Message Bus Clock) . . . . . . . . . . . . . . . . 20

4.2.10 PICD0# and PICD1# (Interrupt Message Data Bits) . . . . . . . 20
4.2.11 WSC# (Write Snoop Complete) . . . . . . . . . . . . . . . . . . . . . . . . 21
4.2.12 STPCLK# (Stop Clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4.3

PCI Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.3.1

AD[31:0] (PCI Address/Data Bus) Summary . . . . . . . . . . . . . 22

4.3.2

C/BE[3:0]# (PCI Command/Byte Enable) . . . . . . . . . . . . . . . . . 22

4.3.3

DEVSEL# (PCI Bus Device Select) . . . . . . . . . . . . . . . . . . . . . . 23

4.3.4

FRAME# (PCI Bus Cycle Frame) . . . . . . . . . . . . . . . . . . . . . . . 24

4.3.5

IDSEL (PCI Initialization Device Select) . . . . . . . . . . . . . . . . 24

4.3.6

IRDY# (PCI Bus Initiator Ready) . . . . . . . . . . . . . . . . . . . . . . . 24

4.3.7

PAR (PCI Bus Parity) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.3.8

PCIRST# (PCI Reset) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

4.3.9

PCLK (PCI Bus Clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

4.3.10 PGNT# (PCI Grant) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.3.11 PIRQ[D:A]# (PCI Interrupt Requests) . . . . . . . . . . . . . . . . . . . 27
4.3.12 PREQ# (PCI Request) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.3.13 SERR# (System Error) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.3.14 STOP# (Stop) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.3.15 TRDY# (PCI Target Ready) . . . . . . . . . . . . . . . . . . . . . . . . . . 28

4.4

ISA Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

4.4.1

AEN (Address Enable) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

4.4.2

BALE (Bus Address Latch Enable) . . . . . . . . . . . . . . . . . . . . . 29

4.4.3

BCLK (Bus Clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

4.4.4

DACK[7:5]#, DACK[3:0]# (DMA Acknowledge) . . . . . . . . . . 30

4.4.5

DRQ[7:5], DRQ[3:0] (DMA Request) . . . . . . . . . . . . . . . . . . . 30

4.4.6

IOCHCK# (I/O Channel Check) . . . . . . . . . . . . . . . . . . . . . . . 30

4.4.7

IOCHRDY (I/O Channel Ready) . . . . . . . . . . . . . . . . . . . . . . . 31

4.4.8

IOCS16# (16-Bit I/O Chip Select) . . . . . . . . . . . . . . . . . . . . . . 31

4.4.9

IOR# (I/O Read) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

4.4.10 IOW# (I/O Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.4.11 IRQ15, IRQ14, IRQ[12:9], IRQ[7:3] (Interrupt Requests) . . 32
4.4.12 NMPIRQ (Native Mode Primary IDE Port IRQ) . . . . . . . . . . 33
4.4.13 NMSIRQ (Native Mode Secondary IDE Port IRQ) . . . . . . . . 33
4.4.14 LA[23:17] (Unlatched Address) . . . . . . . . . . . . . . . . . . . . . . . 33
4.4.15 MASTER# (ISA Master Cycle Indicator) . . . . . . . . . . . . . . . . 33
4.4.16 MEMCS16# (16-Bit Memory Chip Select) . . . . . . . . . . . . . . . 34
4.4.17 MEMR# (Memory Read) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4.4.18 MEMW# (Memory Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4.4.19 OSC (Oscillator) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
4.4.20 REFRESH# (Refresh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
4.4.21 ROM_KBCS# (ROM and Keyboard Chip Select) . . . . . . . . . 35
4.4.22 RSTDRV (Reset Drive) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

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Preliminary Information

4.4.23 SA[16:0] (System Address Bus) . . . . . . . . . . . . . . . . . . . . . . . 36
4.4.24 SBHE# (System Byte High Enable) . . . . . . . . . . . . . . . . . . . . 36
4.4.25 SD[15:0] (ISA System Data) . . . . . . . . . . . . . . . . . . . . . . . . . . 36
4.4.26 SMEMR# (Standard Memory Read) . . . . . . . . . . . . . . . . . . . . 36
4.4.27 SMEMW# (Standard Memory Write) . . . . . . . . . . . . . . . . . . . 37
4.4.28 SPKR (Speaker) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
4.4.29 TC (Terminal Count) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

4.5

Ultra DMA Enhanced IDE Interface . . . . . . . . . . . . . . . . . . . 38

4.5.1

DADDRP[2:0] (Primary IDE Address) . . . . . . . . . . . . . . . . . . 38

4.5.2

DADDRS[2:0] (Secondary IDE Address) . . . . . . . . . . . . . . . . 38

4.5.3

DCS1P# (Primary Port Chip Select) . . . . . . . . . . . . . . . . . . . . 38

4.5.4

DCS1S# (Secondary Port Chip Select) . . . . . . . . . . . . . . . . . . 39

4.5.5

DCS3P# (Primary Port Chip Select) . . . . . . . . . . . . . . . . . . . . 39

4.5.6

DCS3S# (Secondary Port Chip Select) . . . . . . . . . . . . . . . . . . 39

4.5.7

DDATAP[15:0] (Primary IDE Data Bus) . . . . . . . . . . . . . . . . 39

4.5.8

DDATAS[15:0] (Secondary IDE Data Bus) . . . . . . . . . . . . . . 40

4.5.9

DDACKP# (Primary IDE DMA Acknowledge) . . . . . . . . . . . 40

4.5.10 DDACKS# (Secondary IDE DMA Acknowledge) . . . . . . . . . 41
4.5.11 DDMARDYP# (Primary Device DMA Ready,

Ultra DMA Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

4.5.12 DDMARDYS# (Secondary Device DMA Ready,
UltraDMAMode) 41
4.5.13 DDRQP (Primary IDE DMA Request) . . . . . . . . . . . . . . . . . . 41
4.5.14 DDRQS (Secondary IDE DMA Request) . . . . . . . . . . . . . . . . 42
4.5.15 DIORP# (Primary I/O Read) . . . . . . . . . . . . . . . . . . . . . . . . . . 42
4.5.16 DIORS# (Secondary I/O Read) . . . . . . . . . . . . . . . . . . . . . . . . 42
4.5.17 DIOWP# (Primary I/O Write) . . . . . . . . . . . . . . . . . . . . . . . . . 42
4.5.18 DIOWS# (Secondary I/O Write) . . . . . . . . . . . . . . . . . . . . . . . 43
4.5.19 DRDYP# (Primary Device Ready) . . . . . . . . . . . . . . . . . . . . . 43
4.5.20 DRDYS# (Secondary Device Ready) . . . . . . . . . . . . . . . . . . . 43
4.5.21 DSTROBEP (Primary Device Strobe, Ultra DMA Mode) . . . 44
4.5.22 DSTROBES (Secondary Device Strobe, Ultra DMA Mode) . 44
4.5.23 HDMARDYP# (Primary Host DMA Ready,

Ultra DMA Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

4.5.24 HDMARDYS# (Secondary Host DMA Ready,

Ultra DMA Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

4.5.25 HSTROBEP (Primary Host Strobe, Ultra DMA Mode) . . . . 45
4.5.26 HSTROBES (Secondary Host Strobe, Ultra DMA Mode) . . 45
4.5.27 STOPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4.5.28 STOPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

4.6

System Management Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

4.6.1

C32KHZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

4.6.2

CACHE_ZZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

4.6.3

PNPIRQ1 (Plug and Play Interrupt Request 1) . . . . . . . . . . 47

Document Outline

• 1 Features
  • 1.1 PCItoISA Bridge
  • 1.2 Enhanced IDE Controllers
  • 1.3 Universal Serial Bus Controller
  • 1.4 PlugnPlay Support
  • 1.5 Power Management
• 2 Overview
  • 2.1 PCItoISA Bridge
    • 2.1.1 PCI Bus Master Mode
    • 2.1.2 PCI Bus Target Mode
  • 2.2 ISA Bus Controller
  • 2.3 EIDE Controller
  • 2.4 Universal Serial Bus (USB)
  • 2.5 Power Management
• 3 Ordering Information
• 4 Signal Descriptions
  • 4.1 Signal Terminology
  • 4.2 Processor Interface
    • 4.2.1 A20M# (Processor A20 Mask)
    • 4.2.2 CPURST# (Processor Reset)
    • 4.2.3 FERR# (Floating Point Error)
    • 4.2.4 IGNNE# (Ignore Numeric Exception)
    • 4.2.5 INIT# (Initialization)
    • 4.2.6 INTR (Processor Interrupt)
    • 4.2.7 NMI (NonMaskable Interrupt)
    • 4.2.8 SMI# (System Management Interrupt)
    • 4.2.9 PICCLK (Interrupt Message Bus Clock)
    • 4.2.10 PICD0# and PICD1# (Interrupt Message Data Bits)
    • 4.2.11 WSC# (Write Snoop Complete)
    • 4.2.12 STPCLK# (Stop Clock)
  • 4.3 PCI Bus Interface
    • 4.3.1 AD[31:0] (PCI Address/Data Bus) Summary
    • 4.3.2 C/BE[3:0]# (PCI Command/Byte Enable)
    • 4.3.3 DEVSEL# (PCI Bus Device Select)
    • 4.3.4 FRAME# (PCI Bus Cycle Frame)
    • 4.3.5 IDSEL (PCI Initialization Device Select)
    • 4.3.6 IRDY# (PCI Bus Initiator Ready)
    • 4.3.7 PAR (PCI Bus Parity)
    • 4.3.8 PCIRST# (PCI Reset)
    • 4.3.9 PCLK (PCI Bus Clock)
    • 4.3.10 PGNT# (PCI Grant)
    • 4.3.11 PIRQ[D:A]# (PCI Interrupt Requests)
    • 4.3.12 PREQ# (PCI Request)
    • 4.3.13 SERR# (System Error)
    • 4.3.14 STOP# (Stop)
    • 4.3.15 TRDY# (PCI Target Ready)
  • 4.4 ISA Bus Interface
    • 4.4.1 AEN (Address Enable)
    • 4.4.2 BALE (Bus Address Latch Enable)
    • 4.4.3 BCLK (Bus Clock)
    • 4.4.4 DACK[7:5]#, DACK[3:0]# (DMA Acknowledge)
    • 4.4.5 DRQ[7:5], DRQ[3:0] (DMA Request)
    • 4.4.6 IOCHCK# (I/O Channel Check)
    • 4.4.7 IOCHRDY (I/O Channel Ready)
    • 4.4.8 IOCS16# (16Bit I/O Chip Select)
    • 4.4.9 IOR# (I/O Read)
    • 4.4.10 IOW# (I/O Write)
    • 4.4.11 IRQ15, IRQ14, IRQ[12:9], IRQ[7:3] (Interrupt Requests)
    • 4.4.12 NMPIRQ (Native Mode Primary IDE Port IRQ)
    • 4.4.13 NMSIRQ (Native Mode Secondary IDE Port IRQ)
    • 4.4.14 LA[23:17] (Unlatched Address)
    • 4.4.15 MASTER# (ISA Master Cycle Indicator)
    • 4.4.16 MEMCS16# (16Bit Memory Chip Select)
    • 4.4.17 MEMR# (Memory Read)
    • 4.4.18 MEMW# (Memory Write)
    • 4.4.19 OSC (Oscillator)
    • 4.4.20 REFRESH# (Refresh)
    • 4.4.21 ROM_KBCS# (ROM and Keyboard Chip Select)
    • 4.4.22 RSTDRV (Reset Drive)
    • 4.4.23 SA[16:0] (System Address Bus)
    • 4.4.24 SBHE# (System Byte High Enable)
    • 4.4.25 SD[15:0] (ISA System Data)
    • 4.4.26 SMEMR# (Standard Memory Read)
    • 4.4.27 SMEMW# (Standard Memory Write)
    • 4.4.28 SPKR (Speaker)
    • 4.4.29 TC (Terminal Count)
  • 4.5 Ultra DMA Enhanced IDE Interface
    • 4.5.1 DADDRP[2:0] (Primary IDE Address)
    • 4.5.2 DADDRS[2:0] (Secondary IDE Address)
    • 4.5.3 DCS1P# (Primary Port Chip Select)
    • 4.5.4 DCS1S# (Secondary Port Chip Select)
    • 4.5.5 DCS3P# (Primary Port Chip Select)
    • 4.5.6 DCS3S# (Secondary Port Chip Select)
    • 4.5.7 DDATAP[15:0] (Primary IDE Data Bus)
    • 4.5.8 DDATAS[15:0] (Secondary IDE Data Bus)
    • 4.5.9 DDACKP# (Primary IDE DMA Acknowledge)
    • 4.5.10 DDACKS# (Secondary IDE DMA Acknowledge)
    • 4.5.11 DDMARDYP# (Primary Device DMA Ready, Ultra DMA Mode)
    • 4.5.12 DDMARDYS# (Secondary Device DMA Ready, UltraDMAMode)
    • 4.5.13 DDRQP (Primary IDE DMA Request)
    • 4.5.14 DDRQS (Secondary IDE DMA Request)
    • 4.5.15 DIORP# (Primary I/O Read)
    • 4.5.16 DIORS# (Secondary I/O Read)
    • 4.5.17 DIOWP# (Primary I/O Write)
    • 4.5.18 DIOWS# (Secondary I/O Write)
    • 4.5.19 DRDYP# (Primary Device Ready)
    • 4.5.20 DRDYS# (Secondary Device Ready)
    • 4.5.21 DSTROBEP (Primary Device Strobe, Ultra DMA Mode)
    • 4.5.22 DSTROBES (Secondary Device Strobe, Ultra DMA Mode)
    • 4.5.23 HDMARDYP# (Primary Host DMA Ready, Ultra DMA Mode)
    • 4.5.24 HDMARDYS# (Secondary Host DMA Ready, Ultra DMA Mode)
    • 4.5.25 HSTROBEP (Primary Host Strobe, Ultra DMA Mode)
    • 4.5.26 HSTROBES (Secondary Host Strobe, Ultra DMA Mode)
    • 4.5.27 STOPP
    • 4.5.28 STOPS
  • 4.6 System Management Pins
    • 4.6.1 C32KHZ
    • 4.6.2 CACHE_ZZ
    • 4.6.3 PNPIRQ1 (Plug and Play Interrupt Request 1)
    • 4.6.4 CPUSLEEP#
    • 4.6.5 PNPCS0# (Plug and Play Chip Select 0)
    • 4.6.6 CPUSTOP# (Processor Clock Stop)
    • 4.6.7 PNPCS1# (Plug and Play Chip Select 1)
    • 4.6.8 DCSTOP# (DRAM Controller Stop)
    • 4.6.9 PNPIRQ2 (Plug and Play Interrupt Request 2)
    • 4.6.10 EXTSMI# (External SMI Input)
    • 4.6.11 BMREQ# (PCI Bus Master Request)
    • 4.6.12 FLAGRD# (Flag Read)
    • 4.6.13 PNPDAK# (Plug and Play DMA Acknowledge)
    • 4.6.14 FLAGWR (Flag Write)
    • 4.6.15 PNPDRQ (Plug and Play DMA Request)
    • 4.6.16 INTIRQ8# (Internal Real Time Clock Interrupt)
    • 4.6.17 SQWAVE (Square Wave Clock)
    • 4.6.18 PCISTOP# (PCI Bus Clock Stop)
    • 4.6.19 PNPIRQ0 (Plug and Play Interrupt Request 0)
    • 4.6.20 PME# (Power Management Interrupt)
    • 4.6.21 PWRBTN# (Power Button)
    • 4.6.22 PWRGD (Power Good)
    • 4.6.23 PWRON# (Main Power On)
    • 4.6.24 RI# (Ring Indicator)
    • 4.6.25 SERIRQ (Serial IRQ)
    • 4.6.26 MSIRQ (Mouse Interrupt Request)
    • 4.6.27 SMBALERT# (SMBus Alert)
    • 4.6.28 SMBUSC (System Management Bus Clock)
    • 4.6.29 SMBUSD (System Management Bus Data)
    • 4.6.30 SLPBTN# (Sleep Button)
    • 4.6.31 EXTIRQ8# (Real Time Clock Interrupt)
    • 4.6.32 SUSPEND# (Processor Suspend)
    • 4.6.33 THERM# (Thermal Warning Detect)
  • 4.7 Universal Serial Bus Interface
    • 4.7.1 USBCLK (Universal Serial Bus Clock)
    • 4.7.2 USBP[3:0] (USB Port [3:0] Data Positive)
    • 4.7.3 USBN[3:0] (USB Port [3:0] Data Negative)
    • 4.7.4 USBOC0# (USB Over-Current Detect 0)
    • 4.7.5 USBOC1# (USB Over-Current Detect 1)
  • 4.8 Keyboard Interface
    • 4.8.1 KBCK (Keyboard Clock)
    • 4.8.2 KA20G (Keyboard Gate A20)
    • 4.8.3 KBDT (Keyboard Data)
    • 4.8.4 KBRC# (Keyboard Reset)
    • 4.8.5 KEYLOCK (Keyboard Lock)
    • 4.8.6 DBRDY (Debug Ready)
    • 4.8.7 MSCK (Mouse Clock)
    • 4.8.8 MSDT (Mouse Data)
    • 4.8.9 EKIRQ1 (External Keyboard Controller IRQ1)
    • 4.8.10 EKIRQ12 (External Keyboard Controller IRQ12)
  • 4.9 Internal RealTime Clock
    • 4.9.1 RTCX_IN (Crystal/Oscillator Input)
    • 4.9.2 RTCX_OUT (Crystal/Oscillator Output)
  • 4.10 Power and Ground
    • 4.10.1 GND (Power Ground)
    • 4.10.2 GND_USB (USB Differential Output Ground)
    • 4.10.3 VDD3 (Power Supply for the Processor I/O Voltage)
    • 4.10.4 VDD_REF (Power Reference)
    • 4.10.5 VDD_RTC (Power Supply to RTC)
    • 4.10.6 VDDSOFT (Power Supply)
    • 4.10.7 VDDUSB (USB Differential Output Power)
• 5 Functional Operations
  • 5.1 PCI BusInitiated Accesses
    • 5.1.1 Overview
  • 5.2 PCI Bus Commands
    • 5.2.1 Interrupt Acknowledge
    • 5.2.2 Special Bus Cycles
    • 5.2.3 I/O Read and Write
    • 5.2.4 Memory Read and Write
    • 5.2.5 Configuration Read and Write
    • 5.2.6 Memory Read Multiple
    • 5.2.7 Dual Address Line
    • 5.2.8 Memory Read Line
    • 5.2.9 Memory Write Invalidate
  • 5.3 PCI Bus Features
    • 5.3.1 BacktoBack Cycles
    • 5.3.2 Subtractive Decoding
    • 5.3.3 ISA Bus Control Register
  • 5.4 ISA BusInitiated Cycles
    • 5.4.1 DMAInitiated Cycles
    • 5.4.2 ISA Bus Master Initiated Cycles
  • 5.5 PCI Bus Arbitration
  • 5.6 I/O and Memory Mapping
    • IDE Bus I/O Location
    • Bus Master IDE Register I/O Location
    • ISA Bus I/O Location (OnChip)
    • ISA Bus I/O Location (OffChip)
    • ISA Bus OffBoard Memory Location
    • 5.6.1 I/O Mapping
      • OnChip I/O
      • SA Bus I/O
    • 5.6.2 Memory Mapping
      • ISA Memory
    • 5.6.3 System ROM Memory Mapping
      • Flash Memory Support
  • 5.7 Power Planes and Reset
  • 5.8 Clock Generation
    • PCLK
    • OSC
    • USBCLK
    • KBCK
    • MSK
    • RTC_XIN, RTC_XOUT
    • PICCLK
    • BCLK
  • 5.9 Resets
  • 5.10 Direct Memory Access
    • 5.10.1 DMA Controllers
    • 5.10.2 DMA Controller Registers
      • Target and Master DMA Controllers Ports C0h…DFh
    • 5.10.3 Middle Address Bit Latches
    • 5.10.4 Page Registers
    • 5.10.5 DMA Address Generation
    • 5.10.6 Type F DMA
    • 5.10.7 DMA Channel Mapping Registers
    • 5.10.8 Ready Control Logic
    • 5.10.9 External Cascading
  • 5.11 Distributed DMA Support
    • 5.11.1 Target DMA Channel
    • 5.11.2 DMA Control Registers
      • Command Register
      • Mode Register
      • Request Register
      • SingleChannel Mask Register
      • Status Register
    • 5.11.3 DMA Software Commands
      • Master Clear
    • 5.11.4 DMA Addressing
    • 5.11.5 PCI Target DMA Configuration Registers
  • 5.12 ISA Bus Refresh Cycle Types
  • 5.13 Fast IDE/EIDE Interface
    • 5.13.1 IDE Drive Registers
    • 5.13.2 IDE Configuration Registers
    • 5.13.3 Ultra DMA Support
      • UDMA33/66 Protocol Changes
  • 5.14 Power Management Support
    • 5.14.1 Power Management Subsystem
    • 5.14.2 Power Plane Management
    • 5.14.3 SCI and SMI Control
    • 5.14.4 System Inactivity Timer
    • 5.14.5 Throttling Logic
    • 5.14.6 System Power State Controller (SPSC)
      • MOFF to FON and SOFF to FON
      • MOFF to SOFF
      • C2, C3, or POS to SOFF
      • Transitions Between FON and C2, C3, or POS
    • 5.14.7 Serial IRQ Protocol
    • 5.14.8 SMBus
      • Host Bus Controller
      • Host-as-Target Controller
    • 5.14.9 Plug and Play
    • 5.14.10 General-Purpose I/O
    • 5.14.11 General-Purpose I/O Functions
      • Debounce
      • GPIO Output Clocks
    • 5.14.12 AMD-751’ Controller Power Management
    • 5.14.13 VDD_SOFT Registers and Logic
      • Registers
      • Logic
    • 5.14.14 RTC and CMOS Memory
      • Power
      • Oscillator
      • VDD_SOFT Reset
      • Self Reset
      • External Real-Time Clock
      • New ACPI Requirements
      • PRDY
  • 5.15 Universal Serial Bus Controller (USBC)
    • Introduction
    • PCI Interface
    • PCI Master
    • PCI Target
    • Device Selection
    • Write Cycles
    • Read Cycles
    • Configuration Cycles
    • Locked Cycles
    • Abort Cycles
    • Generation of STOP#
    • 5.15.1 USBC Miscellaneous Functions
      • Power Switching
      • Over-Current Protection
      • Legacy Keyboard and Mouse Support
      • Keyboard/Mouse Input
      • Keyboard Output
      • Emulation Interrupts
      • Mixed Environment Interrupts
      • Gate A20 Sequence
      • Emulation Registers
      • HceInput Register
      • HceOutput Register
      • HceStatus Register
    • 5.15.2 System Management
      • Activity Monitoring
      • USBC Signaled Suspend and Resume
      • Selective Suspend and Resume
      • Device Signaled Resume
      • USB Interrupts
  • 5.16 Programmable Interrupt Controller (PIC)
    • Introduction
    • The Interrupt Request Register (IRR) and In-Service Register (ISR)
    • Priority Resolver
    • Interrupt Mask Register
    • Read/Write Control Logic
    • The Cascade Buffer/Comparator
    • Interrupt Sequence
    • 5.16.1 Programming
      • Initialization Command Words (ICWs)
      • Operational Command Words (OCWs)
      • ICW1 Vector and Control
      • ICW2 interrupt Vector
      • ICW3
      • ICW4
      • OCW1
      • OCW2
      • OCW3
      • Fully-Nested Mode
      • End of interrupt (EOI)
      • Automatic End of Interrupt (AEOI) Mode
      • Priority Rotation
      • Specific Priority
      • Interrupt Mask
      • Special Mask Mode
      • Poll Command
      • Reading the PIC Status
      • Edge-Triggered and Level-Triggered Modes
      • Special Full-Nested Mode
      • Buffered Mode
      • Cascade Mode
  • 5.17 I/O Advanced Programmable Interrupt Controller (IOAPIC)
    • Introduction
    • Local APIC
    • IOAPIC
    • Write Snoop Capable Input
    • Interrupt Message Bus (IMB)
    • Arbitration
• 6 Initialization
  • 6.1 Legacy I/O Registers
  • 6.2 PCI Function 1 Registers„IDE Controller
  • 6.3 PCI Function 3 Registers„Power Management
    • 6.3.1 Power Management Configuration Space Registers
    • 6.3.2 Power Management I/O Space Registers
  • 6.4 PCI Function 4 Registers„USB Controller
    • 6.4.1 Pins Latched At The Trailing Edge Of RESET
      • DADDRF[2:0], DCS1F#
      • ROM_KBCS#
• 7 Registers
  • 7.1 Table Conventions
  • 7.2 PCI Mechanism #1
  • 7.3 Register Summaries
  • 7.4 Legacy I/O Registers
    • 7.4.1 Keyboard Controller Registers
      • Traditional Keyboard Controllers
    • 7.4.2 DMA Controller I/O Registers
      • Master DMA Controller Registers
      • Slave DMA Controller Registers
      • DMA Page Registers
    • 7.4.3 Interrupt Controller Registers
      • Master Interrupt Controller Registers
      • Slave Interrupt Controller Registers
    • 7.4.4 Interrupt Controller Shadow Registers
    • 7.4.5 Timer/Counter Registers
    • 7.4.6 CMOS/RTC Registers
    • 7.4.7 Miscellaneous I/O Functions
  • 7.5 Function 0 Registers (PCIISA Bridge)
    • 7.5.1 ISA Bus Control
    • 7.5.2 Distributed DMA Control
  • 7.6 Function 1 Registers (Enhanced IDE Controller)
    • 7.6.1 Function 1 PCI Configuration Space Header
    • 7.6.2 IDE Configuration Registers
  • 7.7 Function 3 Registers (Power Management)
    • 7.7.1 Function 3 PCI Configuration Space Header
    • 7.7.2 Power Management Configuration Registers
    • 7.7.3 Power Management I/O Space Registers
    • 7.7.4 Processor Power Management Registers
      • General Purpose I/O Registers
      • System Management Bus Registers
  • 7.8 Function 4 Registers (USB)
    • 7.8.1 Function 4 USB Configuration
    • 7.8.2 USB Memory Mapped Registers (Open HCI Registers)
    • 7.8.3 I/O APIC Registers
      • Memory Mapped Registers
      • APIC ID-I/O APIC Identification Register
      • APIC ID-I/O APIC Version Register
      • APICARB Register
      • Redirection Table Entry Registers
• 8 Electrical Data
  • 8.1 Absolute Ratings
  • 8.2 Operating Ranges
  • 8.3 DC Characteristics
  • 8.4 Power Dissipation
• 9 Switching Characteristics
  • 9.1 OSC Switching Characteristics
  • 9.2 PCI Interface Timing
  • 9.3 USB Interface Timing
  • 9.4 ISA Interface Timing
  • 9.5 DMA Interface Timing
  • 9.6 EIDE Interface Timing
  • 9.7 Ultra DMA33 IDE Bus Interface Timing
• 10 Pin Designations
  • 10.1 Pin Designation Table
    • 10.1.1 State of Pins At Reset
    • 10.1.2 AMD-756’ Peripheral Bus Controller Pin Diagram
    • 10.1.3 Multiplexed Pins
• 11 Package Specifications