P r o d u c t B r i e f
Overview
The nP3705 family of integrated network proces-
sors is a derivative of the nP3700 family that
expands AMCC's nP
5TM
technology to lower
speed, cost-sensitive access applications.
Developed over several generations of traffic man-
agement and network processor products, nP
5
unites the flexibility of the industry's highest per-
formance network processing nPcore with the
most widely deployed and mature traffic manage-
ment technology. This unique combination
enables developers to deliver extremely fine-
grained control of subscriber traffic, without
impacting the ability to perform complex protocol
inter-working at media speeds. The nP3705 family
is designed from the ground up to provide soft-
ware compatibility with the earlier generations of
AMCC Network Processors. The single-stage pro-
gramming model dramatically simplifies software
development and troubleshooting for quickest
time-to-market.
Industry Leading Integration and Performance
The nP3705 is a 2.5-Gbps network processing and
traffic management solution. In addition to high-
performance packet processing and fine-grained
traffic management, the nP3705 includes special-
ized coprocessors that perform classification, polic-
ing, and coherent database management for
unparalleled line-rate performance. The devices
are offered in different speed grades to provide a
range of performance and cost options tuned to
the application.
Rapid Application Development
AMCC's nPsoft
TM
development environment
speeds the development, debugging, and delivery
of feature-rich, wire-speed, Layer 2-7 applications
by combining the simplified nPcoreTM program-
ming model of all AMCC NPUs with open, layered
nPsoft Services, advanced development tools, rich
reference application libraries, and both simulation
and real hardware-based development systems.
Because the nP3705 allows easy API access to on-
chip coprocessors for complex tasks, customer dif-
ferentiating features can be created faster and with
fewer lines of code.
Features
Supports 2.5-Gbps Traffic
· nP
5
Technology
· Mix and match Gigabit Ethernet, POS, and ATM
traffic
· Standalone or as a line card in a larger system
Proven nPcore Architecture
· 1 nPcore at 700 MHz optimized for network pro-
cessing
· Single-stage single-image programming model
· High-speed RLDRAM-II or FCRAM-II memory
interface for payload and context storage
· Per-flow metering and statistics for millions of
flows
Integrated Traffic Manager
· Per-flow queuing and scheduling
· Sophisticated, fine-grained scheduling algo-
rithms
Standards-Compliant Interfaces
· 14 FE/2 GE with Integrated MAC
· OIF SPI-3, OIF SPI-4.2 (1/4 rate)
· ATM Forum Utopia 2 / PL-2
Benefits
· High integration for Signifi-
cant form factor, cost, and
power savings
· Hardware-based Traffic Man-
ager for guaranteed perfor-
mance
· Software compatibility with
previous generation nP
devices: nP37x0, nP34xx,
nP7250
· Simple programming model
for rapid development and
quick time-to-market
Figure 1. Channelized 2xOC-3/STM-1 Multi-Service Line Card with CES
Channelized
2xOC-3 / STM-1,
6 xT3/E3
AMUR
RL/FC-DRAMII
Flexible Tributary
Interface
Circuit
Emulation
Services
SPI-3
QAB
SPI-3
GE
nP3705
QDR SRAM
CPU
Control Plane
SPI-3
SPI-4.2
RL/FC-DRAMII
nP3705
2.5-Gbps Network Processor with Integrated Traffic Manager
Figure 2. 2.5Gb/s Broadband Access Line Card
DSL Modem Bank or
PON
DSL Modem Bank or
PON
Utopia-2
nP3705
GE
QDR SRAM
RL/FC
DRAM
GE
Utopia-2
AMCC reserves the right to make changes to its products, or to discontinue any product or service without notice, and advises its customers to obtain the latest version of relevant information to
verify, before placing orders, that the information being relied upon is current.
AMCC is a registered trademark of Applied Micro Circuits Corporation. 3ware, SwitchedRAID and 3DM are registered trademarks in the United States and StorSwitch is a trademark in the United
States, of Applied Micro Circuits Corporation. All other trademarks are the property of their respective holders. Copyright © 2004 Applied Micro Circuits Corporation. All Rights Reserved.
nP3705_PB2012_10/03/04
nP3705
6290 Sequence Drive
San Diego, CA 92121
P 858.450.9333
F 858.450.9885
www.amcc.com
Applications
· OC-12/STM-4 ASAP applications ATM, IMA, FR, PPP, ML-FR/PPP
· Up to 2.5Gbs line cards in access systems - DSLAM, FTTx
· OC-12 SAR, ATM to Packet IWF
· L3-L7 Applications
MISSION
TM
-- Multi-Service Internetworking Solution
The nP3705, combined with AMCC's Amur (S1215) channelized framer
and ATM/HDLC/GFP processor extend AMCC's MISSION multi-service
offering to applications up to OC-12/STM-4 rates. This solution enables
the development of single multiprotocol solutions in place of multiple
single-protocol solutions. The MISSION architecture provides equip-
ment vendors with solutions that enable their customers to save on
both capital and operational expenditures (CapEx/OpEx).
MISSION Software
At the core of the MISSION value proposition is software that imple-
ments a wide variety of protocols on the chip set and enables flexible
potential additions to these base software features. AMCC provides
extensive offerings for the programmable nP37xx Integrated Network
Processors, including both rich off-the-shelf application software and a
complete development environment for extending this application
base if desired.
· The MISSION application software includes ready-to-use Multi-Ser-
vice Switching software ATM UNI/NNI, Inverse Multiplexing over
ATM (IMA), Multi-Link Frame Relay (ML-FR), Multi-Link PPP (ML-PPP),
Frame Relay and FR to ATM Interworking (FR IWF), MPLS Martini
encapsulation as well as OEM customer-extensible libraries for the
hardware-resident aspects of higher layer applications such as IPv4
and IPv6 routing, and Layer 2 packet switching.
Figure 3. nP3705 Block Diagram
18
Traffic
Manager
Queuing
Scheduling
nPcore @ 700 Mhz
nPcore @ 700 Mhz
24 Tasks
24 Tasks
Soft TM
LI
N
E
I
N
T
E
RF
A
C
ES
Policy
Engine
Statistics
Engine
SPU
Hash
Engine
Line
Interfaces
(CSM)
FE/GE
MACs
SPI4.2
2 x FE
Packet Transform
Engine
(PTE)
Scatch
Pad
RL/FC-DRAMII
36
QDR SR
A
M
/ L
A
-
1
HOST CPU
FCN / QAB
JT
A
G
DEBUG
SPI-3 + GE
2xGE
SPI-3
12xFE
2xUL2/PL2
16
XSC
Memory Access Unit
18
Traffic
Manager
Queuing
Scheduling
nPcore @ 700 Mhz
nPcore @ 700 Mhz
24 Tasks
24 Tasks
Soft TM
LI
N
E
I
N
T
E
RF
A
C
ES
Policy
Engine
Statistics
Engine
SPU
Hash
Engine
Line
Interfaces
(CSM)
FE/GE
MACs
SPI4.2
2 x FE
Packet Transform
Engine
(PTE)
Scatch
Pad
RL/FC-DRAMII
36
QDR SR
A
M
/ L
A
-
1
HOST CPU
FCN / QAB
JT
A
G
DEBUG
SPI-3 + GE
2xGE
SPI-3
12xFE
2xUL2/PL2
16
XSC
Memory Access Unit
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