December 2004

AS7C251MNTF18A

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Alliance Semiconductor

P. 1 of 18

2.5V 1M x 18 Flowthrough Synchronous SRAM with NTD

Features

ˇ Organization: 1,048,576 words × 18 bits
ˇ NTD

architecture for efficient bus operation

ˇ Fast clock to data access: 7.5/8.5/10 ns
ˇ Fast OE access time: 3.5/4.0 ns
ˇ Fully synchronous operation
ˇ Flow-through mode
ˇ Asynchronous output enable control
ˇ Available in 100-pin TQFP package

ˇ Individual byte write and global write
ˇ Clock enable for operation hold
ˇ Multiple chip enables for easy expansion
ˇ 2.5V core power supply
ˇ Self-timed write cycles
ˇ Interleaved or linear burst modes
ˇ Snooze mode for standby operation

Logic block diagram

Selection guide

-75

-85

-10

Units

Minimum cycle time

8.5

Maximum clock access time

7.5

8.5

Maximum operating current

275

250

230

Maximum standby current

Maximum CMOS standby current (DC)

r
it
e Buf

f
er

Address

CLK

Output

buffer

DQ [a,b]

CLK

CE0
CE1
CE2

A[19:0]

CEN

Control

CLK

logic

Data

CLK

input

1M x 18

SRAM

array

R/W

DQ [a,b]

BWa

BWb

CLK

ADV / LD

LBO

burst logic

addr. registers

Write delay

CLK

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16 Mb 2.5V Synchronous SRAM products list

1,2

1 Core Power Supply: VDD = 2.5V + 0.125V
2 I/O Supply Voltage: VDDQ = 2.5V + 0.125V

PL-SCD

Pipelined Burst Synchronous SRAM - Single Cycle Deselect

PL-DCD

Pipelined Burst Synchronous SRAM - Double Cycle Deselect

Flow-through Burst Synchronous SRAM

NTD

-PL

Pipelined Burst Synchronous SRAM with NTD

NTD-FT

Flow-through Burst Synchronous SRAM with NTD

Org

Part Number

Mode

Speed

1MX18

AS7C251MPFS18A

PL-SCD

166/133 MHz

512KX32

AS7C25512PFS32A

PL-SCD

166/133 MHz

512KX36

AS7C25512PFS36A

PL-SCD

166/133 MHz

1MX18

AS7C251MPFD18A

PL-DCD

166/133 MHz

512KX32

AS7C25512PFD32A

PL-DCD

166/133 MHz

512KX36

AS7C25512PFD36A

PL-DCD

166/133 MHz

1MX18

AS7C251MFT18A

7.5/8.5/10 ns

512KX32

AS7C25512FT32A

7.5/8.5/10 ns

512KX36

AS7C25512FT36A

7.5/8.5/10 ns

1MX18

AS7C251MNTD18A

NTD-PL

166/133 MHz

512KX32

AS7C25512NTD32A

NTD-PL

166/133 MHz

512KX36

AS7C25512NTD36A

NTD-PL

166/133 MHz

1MX18

AS7C251MNTF18A

NTD-FT

7.5/8.5/10 ns

512KX32

AS7C25512NTF32A

NTD-FT

7.5/8.5/10 ns

512KX36

AS7C25512NTF36A

NTD-FT

7.5/8.5/10 ns

1. NTD: No Turnaround Delay. NTD

is a trademark of Alliance Semiconductor Corporation. All trademarks mentioned in this document are the property

of their respective owners.

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P. 3 of 18

100-pin TQFP - top view

1
2
3
4
5
6
7
8
9
10

12
13
14
15
16
17
18
19
20
21
22
23

24
25
26
27

28
29
30

79
78
77
76
75
74
73
72
71
70
69
68
67

66
65
64
63
62

61
60
59
58
57

56
55
54
53
52
51

LBO

A A

CE0

CE1

CE2

CLK

R/W

CEN

ADV

/
L

TQFP 14 x 20mm

NC
NC
NC

DDQ

SSQ

NC
NC

DQb0
DQb1

SSQ

DDQ

DQb2
DQb3

DQb4
DQb5

DDQ

SSQ

DQb6
DQb7

DQPb

SSQ

DDQ

NC
NC
NC

A
NC
NC

DDQ

SSQ

DQPa
DQa7
DQa6

SSQ

DDQ

DQa5
DQa4
V

ZZ
DQa3

DQa2

DDQ

SSQ

DQa1

DQa0
NC
NC

SSQ

DDQ

NC
NC
NC

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Functional Description

The AS7C251MNTF18A family is a high performance CMOS 16 Mbit synchronous Static Random Access Memory (SRAM)
organized as 1,048,576 words × 18 bits and incorporates a LATE Write.

This variation of the 16Mb+ synchronous SRAM uses the No Turnaround Delay (NTD

) architecture, featuring an enhanced

write operation that improves bandwidth over flowthrough burst devices. In a normal flowthrough burst device, the write data,
command, and address are all applied to the device on the same clock edge. If a read command follows this write command,
the system must wait for one 'dead' cycle for valid data to become available. This dead cycle can significantly reduce overall
bandwidth for applications requiring random access or read-modify-write operations.

NTD

devices use the memory bus more efficiently by introducing a write latency which matches the one-cycle flow-

through read latency. Write data is applied one cycle after the write command and address, allowing the read pipeline to clear.
With NTD

, write and read operations can be used in any order without producing dead bus cycle.

Assert R/W low to perform write cycles. Byte write enable controls write access to specific bytes, or can be tied low for full 18
bit writes. Write enable signals, along with the write address, are registered on a rising edge of the clock. Write data is applied
to the device one clock cycle later. Unlike some asynchronous SRAMs, output enable OE does not need to be toggled for write
operations; it can be tied low for normal operations. Outputs go to a high impedance state when the device is de-selected by
any of the three chip enable inputs.

Use the ADV (burst advance) input to perform burst read, write and deselect operations. When ADV is high, external addresses, chip
select, R/W pins are ignored, and internal address counters increment in the count sequence specified by the LBO control. Any
device operations, including burst, can be stalled using the CEN=1, the clock enable input.

The AS7C251MNTF18A operates with a 2.5V ą 5% power supply for the device core (V

). DQ circuits use a separate

power supply (V

DDQ

). These devices are available in a 100-pin TQFP package.

TQFP capacitance

* Guaranteed not tested

TQFP thermal resistance

Parameter

Symbol

Test conditions

Min

Max

Unit

Input capacitance

= 0V

I/O capacitance

I/O

OUT

= 0V

Description

Conditions

Symbol

Typical

Units

Thermal resistance
(junction to ambient)

1 This parameter is sampled

Test conditions follow standard test methods
and procedures for measuring thermal
impedance, per EIA/JESD51

1layer

°C/W

4layer

°C/W

Thermal resistance
(junction to top of case)

°C/W

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Signal descriptions

Snooze Mode

SNOOZE MODE is a low current, power-down mode in which the device is deselected and current is reduced to I

SB2

. The duration of

SNOOZE MODE is dictated by the length of time the ZZ is in a High state.

The ZZ pin is an asynchronous, active high input that causes the device to enter SNOOZE MODE.

When the ZZ pin becomes a logic High, I

SB2

is guaranteed after the time t

ZZI

is met. After entering SNOOZE MODE, all inputs except ZZ

is disabled and all outputs go to High-Z. Any operation pending when entering SNOOZE MODE is not guaranteed to successfully complete.
Therefore, SNOOZE MODE (READ or WRITE) must not be initiated until valid pending operations are completed. Similarly, when exiting
SNOOZE MODE during t

PUS

, only a DESELECT or READ cycle should be given while the SRAM is transitioning out of SNOOZE MODE.

Signal

I/O Properties

Description

CLK

CLOCK

Clock. All inputs except OE, LBO, and ZZ are synchronous to this clock.

CEN

SYNC

Clock enable. When de-asserted high, the clock input signal is masked.

A, A0, A1

SYNC

Address. Sampled when all chip enables are active and ADV/LD is asserted.

DQ[a,b]

I/O

SYNC

Data. Driven as output when the chip is enabled and OE is active.

CE0, CE1,
CE2

SYNC

Synchronous chip enables. Sampled at the rising edge of CLK, when ADV/LD is asserted.
Are ignored when ADV/LD is high.

ADV/LD

SYNC

Advance or Load. When sampled high, the internal burst address counter will increment in
the order defined by the LBO input value. When low, a new address is loaded.

R/W

SYNC

A high during LOAD initiates a READ operation. A low during LOAD initiates a WRITE
operation. Is ignored when ADV/LD is high.

BW[a,b]

SYNC

Byte write enables. Used to control write on individual bytes. Sampled along with WRITE
command and BURST WRITE.

ASYNC

Asynchronous output enable. I/O pins are not driven when OE is inactive.

LBO

STATIC

Selects Burst mode. When tied to V

or left floating, device follows interleaved Burst order. When

driven Low, device follows linear Burst order. This signal is internally pulled High.

ASYNC

Snooze. Places device in low power mode; data is retained. Connect to GND if unused.

No connect

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Burst order

Synchronous truth table

[5,6,7,8,9,11]

Key: X = Don't Care, H = HIGH, L = LOW.

BWn = H means all byte write signals (BWa, BWb

) are HIGH.

n = L means one or more byte write

signals are LOW.
Notes:
1 CONTINUE BURST cycles, whether READ or WRITE, use the same control inputs. The type of cycle performed (READ or WRITE) is chose in the initial
BEGIN BURST cycle. A CONINUE DESELECT cycle can only be entered if a DESELECT CYCLE is executed first.
2 DUMMY READ and WRITE ABORT cycles can be considered NOPs because the device performs no external operation. A WRITE ABORT means a
WRITE command is given, but no operation is performed.
3 OE may be wired LOW to minimize the number of control signal to the SRAM. The device will automatically turn off the output drivers during a WRITE
cycle. OE may be used when the bus turn-on and turn-off times do not meet an application's requirements.
4 If an INHIBIT CLOCK command occurs during a READ operation, the DQ bus will remain active (Low-Z). If it occurs during a WRITE cycle, the bus will
remain in High-Z. No WRITE operations will be performed during the INHIBIT CLOCK cycle.
5

a enables WRITEs to byte "a" (DQa pins);

b enables WRITEs to byte "b" (DQb pins).

6 All inputs except

and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.

7 Wait states are inserted by setting

CEN

HIGH.

8 This device contains circuitry that will ensure that the outputs will be in High-Z during power-up.
9 The device incorporates a 2-bit burst counter. Address wraps to the initial address every fourth BURST CYCLE.
10 The address counter is incremented for all CONTINUE BURST cycles.
11 ZZ pin is always Low in this truth table.

Interleaved burst order (LBO = 1)

Linear burst order (LBO = 0)

A1A0 A1A0 A1A0 A1A0

Starting address

0 0

0 1

1 0

1 1

Starting Address

0 0

0 1

1 0

1 1

First increment

0 1

0 0

1 1

1 0

First increment

0 1

1 0

1 1

0 0

Second increment

1 0

1 1

0 0

0 1

Second increment

1 0

1 1

0 0

0 1

Third increment

1 1

1 0

0 1

0 0

Third increment

1 1

0 0

0 1

1 0

CE0 CE1 CE2 ADV/LD R/W

BWn

OE CEN

Address

source

CLK

Operation

Notes

L to H

DESELECT Cycle

High-Z

L to H

DESELECT Cycle

High-Z

L to H

DESELECT Cycle

High-Z

L to H

CONTINUE DESELECT Cycle

High-Z

External L to H

READ Cycle (Begin Burst)

L to H

READ Cycle (Continue Burst)

1,10

External L to H NOP/DUMMY READ (Begin Burst) High-Z

L to H

DUMMY READ (Continue Burst)

High-Z 1,2,10

External L to H

WRITE CYCLE (Begin Burst)

L to H

WRITE CYCLE (Continue Burst)

1,3,10

External L to H NOP/WRITE ABORT (Begin Burst) High-Z

2,3

L to H

WRITE ABORT (Continue Burst)

High-Z

1,2,3,

Current L to H

INHIBIT CLOCK

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P. 7 of 18

State diagram for NTD SRAM

Absolute maximum ratings

Note: Stresses greater than those listed in this table may cause permanent damage to the device. This is a stress rating only, and functional operation of the
device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions may affect reliability.

Recommended operating conditions

Parameter

Symbol

Min

Max

Unit

Power supply voltage relative to GND

, V

DDQ

0.3

+3.6

Input voltage relative to GND (input pins)

0.3

+ 0.3

Input voltage relative to GND (I/O pins)

0.3

DDQ

+ 0.3

Power dissipation

1.8

Short circuit output current

OUT

Storage temperature

stg

+150

Temperature under bias

bias

65 +135

Parameter

Symbol

Min

Nominal

Max

Unit

Supply voltage for inputs

2.375

2.5

2.625

Supply voltage for I/O

DDQ

2.375

2.5

2.625

Ground supply

Vss

Dsel

Rea

Read

Burst

Read

Writ

Burs

Read

Wr
i
t
e

Dsel

Read

Burst

Write

Ds
el

Dse

Wri

rit

Burst

Dsel

Burst

Write

Read

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P. 8 of 18

DC electrical characteristics

LBO and ZZ pins have an internal pull-up or pull-down, and input leakage = ą10

ľA.

max < VDD +1.5V for pulse width less than 0.2 X t

CYC

min = -1.5 for pulse width less than 0.2 X t

CYC

operating conditions and maximum limits

Parameter

Sym

Conditions

Min

Max

Unit

Input leakage current

= Max, 0V < V

< V

-2

ľA

Output leakage current

, V

= Max, 0V < V

OUT

< V

DDQ

-2

ľA

Input high (logic 1) voltage

Address and control pins

1.7*

+0.3

I/O pins

1.7*

DDQ

+0.3

Input low (logic 0) voltage

Address and control pins

-0.3**

0.7

I/O pins

-0.3**

0.7

Output high voltage

= 4 mA, V

DDQ

= 2.375V

1.7

Output low voltage

= 8 mA, V

DDQ

= 2.625V

0.7

Parameter

Sym

Conditions

-75

-85

-10

Unit

Operating power supply current

1 I

given with no output loading. I

increases with faster cycle times and greater output loading.

CE0 < V

, CE1 > V

, CE2 < V

, f = f

Max

OUT

= 0 mA, ZZ

< V

275

250

230

Standby power supply current

All V

0.2V or > V

0.2V, Deselected,

f = f

Max

, ZZ

< V

SB1

Deselected, f = 0, ZZ

< 0.2V,

all V

0.2V or V

0.2V

SB2

Deselected, f = f

Max

, ZZ

0.2V,

all V

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Timing characteristics over operating range

Snooze Mode Electrical Characteristics

Parameter

Sym

-75

-85

-10

Unit

Notes

See "Notes:" on page 15.

Min

Max

Min

Max

Min

Max

Cycle time

CYC

8.5

Clock access time

7.5

8.5

Output enable low to data valid

3.5

4.0

Clock high to output low Z

LZC

2.5

2,3,4

Data Output invalid from clock high

3.0

Output enable low to output low Z

LZOE

2,3,4

Output enable high to output high Z

HZOE

3.5

4.0

2,3,4

Clock high to output high Z

HZC

3.5

4.0

2,3,4

Output enable high to invalid output

OHOE

Clock high pulse width

2.5

3.0

4.0

Clock low pulse width

2.5

3.0

4.0

Address and Control setup to clock high

2.0

Data setup to clock high

2.0

Write setup to clock high

2.0

6, 7

Chip select setup to clock high

CSS

2.0

6, 8

Address hold from clock high

0.5

Data hold from clock high

0.5

Write hold from clock high

0.5

6, 7

Chip select hold from clock high

CSH

0.5

6, 8

Clock enable setup to clock high

CENS

2.0

Clock enable hold from clock high

CENH

0.5

ADV setup to clock high

ADVS

2.0

ADV hold from clock high

ADVH

0.5

Description

Conditions

Symbol

Min

Max

Units

Current during Snooze Mode

ZZ > V

SB2

ZZ active to input ignored

PDS

cycle

ZZ inactive to input sampled

PUS

cycle

ZZ active to SNOOZE current

ZZI

cycle

ZZ inactive to exit SNOOZE current

RZZI

cycle

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P. 12 of 18

Timing waveform of read/write cycle

Note: Ý = XOR when LBO = high/no connect. Ý = ADD when LBO = low. BW[a:d] is don't care.

CYC

CENS

CLK

CEN

CE0, CE2

ADV/LD

R/W

ADDRESS

D/Q

Command

HZOE

BWn

D(A1)

D(A5)

Q(A6)

D(A2)

D(A2Ý01)

Q(A3)

Q(A4)

Q(A4Ý01)

CENH

LZC

HZC

LZOE

Read

Q(A3)

Read

Q(A4)

Burst

Read

Q(A4Ý01)

Write

D(A5)

Read

Q(A6)

Write

D(A7)

DSEL

CSS

ADVH

CE1

Write
D(A1)

Write
D(A2)

ADVS

CSH

Burst

Write

D(A2Ý01)

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P. 15 of 18

AC test conditions

Notes:

1) For test conditions, see "AC test conditions", Figures A, B, C
2) This parameter measured with output load condition in Figure C.
3) This parameter is sampled, but not 100% tested.
4) t

HZOE

is less than t

LZOE

and t

HZC

is less than t

LZC

at any given temperature and voltage.

5) t

measured high above V

and t

measured as low below V

6) This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK. All other synchronous inputs must
meet the setup and hold times with stable logic levels for all rising edges of CLK when chip is enabled.
7) Write refers to

R/W and BW[a,b]

8) Chip select refers to

CE0, CE1, and CE2

Undefined/don't care

Falling input

Rising input

ˇ Output load: For t

LZC

, t

LZOE

, t

HZOE

, and t

HZC

, see Figure C. For all others, see Figure B.

ˇ Input pulse level: GND to 2.5V. See Figure A.

ˇ Input rise and fall time (measured at 0.25V and 2.25V): 2 ns. See Figure A.

ˇ Input and output timing reference levels: 1.25V.

OUT

Figure B: Output load (A)

30 pF*

Figure A: Input waveform

10%

90%

GND

90%

10%

+2.5V

= V

DDQ

Thevenin equivalent:

353

/1538

5 pF*

319

/1667

OUT

GND

Figure C: Output load(B)

*including scope

and jig capacitance

+2.5V

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P. 17 of 18

Ordering information

Note: Add suffix `N' to the above part numbers for Lead Free Parts (Ex. AS7C251MNTF18A-85TQCN)

Part numbering guide

1. Alliance Semiconductor SRAM prefix

2. Operating voltage: 25 = 2.5V

3. Organization: 1M

4. NTF = No Turn-Around Delay. Flow-through mode

5. Organization: 18 = x 18

6. Production version: A = first production version

7. Clock access time: [-75 = 7.5 ns access time; -85 = 8.5 ns access time; -10 = 10.0 ns access time]

8. Package type: TQ = TQFP

9. Operating temperature: C = commercial (

° C to 70° C); I = industrial (-40° C to 85° C)

10. N = Lead free part

Package
&Width

75

85

10

TQFP x18

AS7C251MNTF18A-75TQC

AS7C251MNTF18A-85TQC

AS7C251MNTF18A-10TQC

AS7C251MNTF18A-75TQI

AS7C251MNTF18A-85TQI

AS7C251MNTF18A-10TQI

AS7C

NTF

XX

C/I

AS7C251MNTF18A

Š Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are
trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their respective
companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes
no responsibility for any errors that may appear in this document. The data contained herein represents Alliance's best data and/or
estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without notice. If the product
described herein is under development, significant changes to these specifications are possible. The information in this product data
sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide,
any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the
application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of
Alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any
intellectual property rights, except as express agreed to in Alliance's Terms and Conditions of Sale (which are available from
Alliance). All sales of Alliance products are made exclusively according to Alliance's Terms and Conditions of Sale. The purchase of
products from Alliance does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other
intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components in life-
supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the
inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to
indemnify Alliance against all claims arising from such use.

Alliance Semiconductor Corporation

2575, Augustine Drive,

Santa Clara, CA 95054

Tel: 408 - 855 - 4900

Fax: 408 - 855 - 4999

www.alsc.com

Part Number: AS7C251MNTF18A

Document Version: v 1.1

Part Number AS7C251MNTF18A

Document Outline