Data Sheet - Preliminary ADSP-BF538/BF538F Blackfin Embedded Processor Datasheet Rev. PrD

Preliminary Technical Data

Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc.

Blackfin

Embedded Processor

ADSP-BF538/ADSP-BF538F

Rev. PrD

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
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Fax: 781.461.3113

FEATURES

Up to 500 MHz high performance Blackfin processor

Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs,

40-bit shifter

RISC-like register and instruction model for ease of pro-

gramming and compiler friendly support

Advanced debug, trace, and performance monitoring

0.8 V to 1.2 V core V

with on-chip voltage regulation

3.3 V tolerant I/O with specific 5 V tolerant pins
316-ball Pb-free mini-BGA package

MEMORY

148K bytes of on-chip memory:

16K bytes of instruction SRAM/cache
64K bytes of instruction SRAM
32K bytes of data SRAM
32K bytes of data SRAM/cache
4K bytes of scratchpad SRAM

512K bytes or 1M byte of flash memory (ADSP-BF538F parts

only)

Four dual-channel memory DMA controllers

Memory management unit providing memory protection
External memory controller with glueless support

for SDRAM, SRAM, flash, and ROM

Flexible memory booting options from SPI

and external

memory

PERIPHERALS

Parallel peripheral interface (PPI/GPIO)

supporting ITU-R 656 video data formats

Four dual-channel, full-duplex synchronous serial ports, sup-

porting 16 stereo I

channels

Two DMA controllers supporting 26 DMA channels
Controller area network (CAN) 2.0B controller
Three SPI-compatible ports
Three timer/counters with PWM support
Three UARTs with support for IrDA

Two TWI controllers compatible with I

industry standard

Up to 54 general-purpose I/O pins (GPIO)
Real time clock, watchdog timer, and core timer
On-chip PLL capable of 0.5x To 64x frequency multiplication
Debug/JTAG interface

Figure 1. Functional Block Diagram

UART0

SPORT0-1

WATCHDOG

TIMER

RTC

SPI0

TIMER0-2

PPI

SPI1-2

SPORT2-3

UART1-2

GPIO

PORT

GPIO

PORT

GPIO

PORT

GPIO

PORT

EXTERNAL PORT

FLASH, SDRAM CONTROL

BOOT ROM

JTAG TEST AND EMULATION

VOLTAGE REGULATOR

DMA

CONTROLLER0

INSTRUCTION

MEMORY

DATA

MEMORY

INTERRUPT

CONTROLLER

I
P

DMA ACCESS

BUS 1

DMA CORE

BUS 0

DMA

EXTERNAL

BUS 1

I
P

TWI0-1

CAN 2.0B

GPIO

512 KB OR 1 MB

FLASH MEMORY

(ADSP-BF538F ONLY)

DMA

CONTROLLER1

DMA ACCESS

BUS 0

DMA CORE

BUS 1

DMA

EXTERNAL

BUS 0

Rev. PrD

Page 2 of 56

May 2006

ADSP-BF538/ADSP-BF538F

Preliminary Technical Data

TABLE OF CONTENTS

General Description ................................................. 3

Low Power Architecture ......................................... 3

System Integration ................................................ 3

ADSP-BF538/ADSP-BF538F Processor Peripherals ....... 3

Blackfin Processor Core .......................................... 4

Memory Architecture ............................................ 5

DMA Controllers .................................................. 8

Real Time Clock ................................................... 9

Watchdog Timer .................................................. 9

Timers ............................................................... 9

Serial Ports (SPORTs) .......................................... 10

Serial Peripheral Interface (SPI) Ports ...................... 10

Two Wire Interface ............................................. 10

UART Ports ...................................................... 10

General-Purpose Ports ......................................... 11

Parallel Peripheral Interface ................................... 11

Controller Area Network (CAN) Interface ................ 12

Dynamic Power Management ................................ 12

Voltage Regulation .............................................. 14

Clock Signals ..................................................... 14

Booting Modes ................................................... 15

Instruction Set Description ................................... 15

Development Tools ............................................. 16

Designing an Emulator Compatible Processor Board ... 17

Voltage Regulator Layout Guidelines ....................... 17

Pin Descriptions .................................................... 18

Specifications ........................................................ 22

Operating Conditions ........................................... 22

Operating Conditions--Applies to 5V Tolerant pins .... 22

Electrical Characteristics ....................................... 22

Absolute Maximum Ratings ................................... 23

Package Information ............................................ 23

ESD Sensitivity ................................................... 23

Timing Specifications ........................................... 24

Clock and Reset Timing ..................................... 24

Asynchronous Memory Read Cycle Timing ............ 25

Asynchronous Memory Write Cycle Timing ........... 27

SDRAM Interface Timing .................................. 29

External Port Bus Request and Grant Cycle Timing .. 30

Parallel Peripheral Interface Timing ...................... 32

Serial Port Timing ............................................ 35

Serial Peripheral Interface Port--Master Timing ...... 39

Serial Peripheral Interface Port--Slave Timing ........ 40

General-Purpose Port Timing ............................. 41

Timer Cycle Timing .......................................... 42

JTAG Test And Emulation Port Timing ................. 43

Output Drive Currents ......................................... 44

Power Dissipation ............................................... 46

Test Conditions .................................................. 46

Thermal Characteristics ........................................ 50

316-Ball Mini-BGA Pinout ....................................... 51

Outline Dimensions ................................................ 54

Surface Mount Design .......................................... 55

Ordering Guide ..................................................... 55

REVISION HISTORY

5/06--Revision PrD:

For this revision, the following sections were changed.

Functional Block Diagram ......................................... 1

Booting Modes ...................................................... 15

Pin Descriptions .................................................... 18

Output Drive Currents ............................................ 44

Power Dissipation .................................................. 46

Test Conditions ..................................................... 46

316-Ball Mini-BGA Pinout ....................................... 51

ADSP-BF538/ADSP-BF538F

Preliminary Technical Data

Rev. PrD

Page 3 of 56

May 2006

GENERAL DESCRIPTION

The ADSP-BF538/ADSP-BF538F processors are members of
the Blackfin family of products, incorporating the Analog
Devices/Intel Micro Signal Architecture (MSA). Blackfin pro-
cessors combine a dual-MAC state-of-the-art signal processing
engine, the advantages of a clean, orthogonal RISC-like micro-
processor instruction set, and single-instruction, multiple-data
(SIMD) multimedia capabilities into a single instruction set
architecture.

The ADSP-BF538/ADSP-BF538F processors are completely
code compatible with other Blackfin processors, differing only
with respect to performance, peripherals, and on-chip memory.
Specific performance, peripherals, and memory configurations
are shown in

Table 1

By integrating a rich set of industry-leading system peripherals
and memory, Blackfin processors are the platform of choice for
next generation applications that require RISC-like program-
mability, multimedia support and leading edge signal
processing in one integrated package.

LOW POWER ARCHITECTURE

Blackfin processors provide world class power management and
performance. Blackfin processors are designed in a low power
and low voltage design methodology and feature dynamic
power management, the ability to vary both the voltage and fre-
quency of operation to significantly lower overall power
consumption. Varying the voltage and frequency can result in a

substantial reduction in power consumption, compared with
just varying the frequency of operation. This translates into
longer battery life and lower heat dissipation.

SYSTEM INTEGRATION

The ADSP-BF538/ADSP-BF538F processors are highly inte-
grated system-on-a-chip solution for the next generation of
consumer and industrial applications including audio and video
signal processing. By combining advanced memory configura-
tions, such as on-chip flash memory, with industry-standard
interfaces with a high performance signal processing core, users
can develop cost-effective solutions quickly without the need for
costly external components. The system peripherals include
three UART ports, three SPI ports, four serial ports (SPORT),
one CAN interface, 2 two wire interfaces (TWI), four general-
purpose timers (three with PWM capability), a real-time clock, a
watchdog timer, a parallel peripheral interface, general-purpose
I/O, and general-purpose I/O pins.

ADSP-BF538/ADSP-BF538F PROCESSOR
PERIPHERALS

The ADSP-BF538/ADSP-BF538F processors contain a rich set
of peripherals connected to the core via several high bandwidth
buses, providing flexibility in system configuration as well as
excellent overall system performance (see the block diagram

on Page 1

). The general-purpose peripherals include functions

such as UART, Timers with PWM (pulse width modulation)
and pulse measurement capability, general-purpose I/O pins, a
real time clock, and a watchdog timer. This set of functions sat-
isfies a wide variety of typical system support needs and is
augmented by the system expansion capabilities of the device. In
addition to these general-purpose peripherals, the
ADSP-BF538/ADSP-BF538F processors contain high speed
serial and parallel ports for interfacing to a variety of audio,
video, and modem codec functions. A CAN 2.0B controller is
provided for automotive control networks. An interrupt con-
troller manages interrupts from the on-chip peripherals or
external sources. Power management control functions tailor
the performance and power characteristics of the processors
and system to many application scenarios.

All of the peripherals, except for general-purpose I/O, CAN,
TWI, real time clock, and timers, are supported by a flexible
DMA structure. There are also two separate memory DMA con-
trollers dedicated to data transfers between the processor's
various memory spaces, including external SDRAM and asyn-
chronous memory. Multiple on-chip buses running at up to
133 MHz provide enough bandwidth to keep the processor core
running along with activity on all of the on-chip and external
peripherals.

The ADSP-BF538/ADSP-BF538F processors include an on-chip
voltage regulator in support of the ADSP-BF538/ADSP-BF538F
processor's dynamic power management capability. The voltage
regulator provides a range of core voltage levels from a single
2.25 V to 3.6 V input. The voltage regulator can be bypassed at
the user's discretion.

Table 1. Processor Features

Feature

ADSP

-
BF538

ADSP

-
BF538

ADSP

-
BF538

Maximum Performance

500 MHz 1000 MMACs

Instruction SRAM/Cache

16 K bytes

Instruction SRAM

64 K bytes

Data SRAM/Cache

32 K bytes

Data SRAM

32 K bytes

Scratchpad

4 K bytes

Flash

512 K bytes 1 M byte

SPORTs

SPIs

TWIs (connection to I

compatible devices)

UARTs

CAN

PPI

Package Option

See

Ordering Guide on Page 55

Rev. PrD

Page 4 of 56

May 2006

ADSP-BF538/ADSP-BF538F

Preliminary Technical Data

BLACKFIN PROCESSOR CORE

As shown in

Figure 2 on Page 4

, the Blackfin processor core

contains two 16-bit multipliers, two 40-bit accumulators, two
40-bit ALUs, four video ALUs, and a 40-bit shifter. The compu-
tation units process 8-bit, 16-bit, or 32-bit data from the register
file.

The compute register file contains eight 32-bit registers. When
performing compute operations on 16-bit operand data, the
register file operates as 16 independent 16-bit registers. All
operands for compute operations come from the multiported
register file and instruction constant fields.

Each MAC can perform a 16-bit by 16-bit multiply in each
cycle, accumulating the results into the 40-bit accumulators.
Signed and unsigned formats, rounding, and saturation are
supported.

The ALUs perform a traditional set of arithmetic and logical
operations on 16-bit or 32-bit data. In addition, many special
instructions are included to accelerate various signal processing
tasks. These include bit operations such as field extract and pop-
ulation count, modulo 2

multiply, divide primitives, saturation

and rounding, and sign/exponent detection. The set of video
instructions include byte alignment and packing operations, 16-

bit and 8-bit adds with clipping, 8-bit average operations, and 8-
bit subtract/absolute value/accumulate (SAA) operations. Also
provided are the compare/select and vector search instructions.

For certain instructions, two 16-bit ALU operations can be per-
formed simultaneously on register pairs (a 16-bit high half and
16-bit low half of a compute register). By also using the second
ALU, quad 16-bit operations are possible.

The 40-bit shifter can perform shifts and rotates and is used to
support normalization, field extract, and field deposit
instructions.

The program sequencer controls the flow of instruction execu-
tion, including instruction alignment and decoding. For
program flow control, the sequencer supports PC relative and
indirect conditional jumps (with static branch prediction), and
subroutine calls. Hardware is provided to support zero over-
head looping. The architecture is fully interlocked, meaning that
the programmer need not manage the pipeline when executing
instructions with data dependencies.

The address arithmetic unit provides two addresses for simulta-
neous dual fetches from memory. It contains a multiported
register file consisting of four sets of 32-bit index, modify,
length, and base registers (for circular buffering), and eight
additional 32-bit pointer registers (for C style indexed stack
manipulation).

Figure 2. Blackfin Processor Core

SEQUENCER

ALIGN

DECODE

LOOP BUFFER

DAG0

DAG1

BARREL
SHIFTER

DATA ARITHMETIC UNIT

CONTROL

UNIT

ADDRESS ARITHMETIC UNIT

LD0 32 BITS

LD1 32 BITS

SD 32 BITS

R7.L
R6.L

R5.L

R4.L

R3.L

R2.L
R1.L

R0.L

R7.H
R6.H

R5.H

R4.H

R3.H

R2.H
R1.H

R0.H

R7
R6

R2
R1

ADSP-BF538/ADSP-BF538F

Preliminary Technical Data

Rev. PrD

Page 5 of 56

May 2006

Blackfin processors support a modified Harvard architecture in
combination with a hierarchical memory structure. Level 1 (L1)
memories are those that typically operate at the full processor
speed with little or no latency. At the L1 level, the instruction
memory holds instructions only. The two data memories hold
data, and a dedicated scratchpad data memory stores stack and
local variable information.

In addition, multiple L1 memory blocks are provided, offering a
configurable mix of SRAM and cache. The Memory Manage-
ment Unit (MMU) provides memory protection for individual
tasks that may be operating on the core and can protect system
registers from unintended access.

The architecture provides three modes of operation: User mode,
Supervisor mode, and Emulation mode. User mode has
restricted access to certain system resources, thus providing a
protected software environment, while supervisor mode has
unrestricted access to the system and core resources.

The Blackfin processor instruction set has been optimized so
that 16-bit opcodes represent the most frequently used instruc-
tions, resulting in excellent compiled code density. Complex
DSP instructions are encoded into 32-bit opcodes, representing
fully featured multifunction instructions. Blackfin processors
support a limited multi-issue capability, where a 32-bit instruc-
tion can be issued in parallel with two 16-bit instructions,
allowing the programmer to use many of the core resources in a
single instruction cycle.

The Blackfin processor assembly language uses an algebraic syn-
tax for ease of coding and readability. The architecture has been
optimized for use in conjunction with the C/C++ compiler,
resulting in fast and efficient software implementations.

MEMORY ARCHITECTURE

The ADSP-BF538/ADSP-BF538F processors view memory as a
single unified 4 Gbyte address space, using 32-bit addresses. All
resources, including internal memory, external memory, and
I/O control registers, occupy separate sections of this common
address space. The memory portions of this address space are
arranged in a hierarchical structure to provide a good cost/per-
formance balance of some very fast, low latency on-chip
memory as cache or SRAM, and larger, lower cost and perfor-
mance off-chip memory systems. See

Figure 3

The L1 memory system is the primary highest performance
memory available to the Blackfin processor. The off-chip mem-
ory system, accessed through the External Bus Interface Unit
(EBIU), provides expansion with SDRAM, flash memory, and
SRAM, optionally accessing up to 132 Mbytes of physical
memory.

The memory DMA controllers provide high bandwidth data
movement capability. They can perform block transfers of code
or data between the internal memory and the external memory
spaces.

Internal (On-chip) Memory

The ADSP-BF538/ADSP-BF538F processors have three blocks
of on-chip memory providing high bandwidth access to the
core.

The first is the L1 instruction memory, consisting of 80 Kbytes
SRAM, of which 16 Kbytes can be configured as a four way set-
associative cache. This memory is accessed at full processor
speed.

The second on-chip memory block is the L1 data memory, con-
sisting of two banks of up to 32 Kbytes each. Each memory bank
is configurable, offering both two-way set-associative cache and
SRAM functionality. This memory block is accessed at full pro-
cessor speed.

The third memory block is a 4K byte scratchpad SRAM which
runs at the same speed as the L1 memories, but is only accessible
as data SRAM and cannot be configured as cache memory.

External (Off-Chip) Memory

External memory is accessed via the EBIU. This 16-bit interface
provides a glueless connection to a bank of synchronous DRAM
(SDRAM) as well as up to four banks of asynchronous memory
devices including flash, EPROM, ROM, SRAM, and memory
mapped I/O devices.

Figure 3. ADSP-BF538/ADSP-BF538F Internal/External Memory Map

SDRAM MEMORY (16M BYTE - 128M BYTE)

RESERVED

CORE MMR REGISTERS (2M BYTE)

RESERVED

SCRATCHPAD SRAM (4K BYTE)

INSTRUCTION SRAM (32K BYTE)

SYSTEM MMR REGISTERS (2M BYTE)

RESERVED

DATA BANK B SRAM / CACHE (16K BYTE)

DATA BANK A SRAM / CACHE (16K BYTE)

ASYNC MEMORY BANK 3 (1M BYTE) OR

ON-CHIP FLASH

ASYNC MEMORY BANK 2 (1M BYTE) OR

ON-CHIP FLASH

ASYNC MEMORY BANK 1 (1M BYTE) OR

ON-CHIP FLASH

ASYNC MEMORY BANK 0 (1M BYTE) OR

ON-CHIP FLASH

INSTRUCTION SRAM / CACHE (16K BYTE)

I
N

0xFFFF FFFF

0xFFE0 0000

0xFFB0 0000

0xFFA1 4000

0xFFA1 0000

0xFF90 8000

0xFF90 4000

0xFF80 8000

0xFF80 4000

0xEF00 0000

0x2040 0000

0x2030 0000

0x2020 0000

0x2010 0000

0x2000 0000

0x0800 0000

0x0000 0000

0xFFC0 0000

0xFFB0 1000

0xFFA0 8000

RESERVED

Rev. PrD

Page 6 of 56

May 2006

ADSP-BF538/ADSP-BF538F

Preliminary Technical Data

The PC133-compliant SDRAM controller can be programmed
to interface to up to 128 Mbytes of SDRAM. The SDRAM con-
troller allows one row to be open for each internal SDRAM
bank, for up to four internal SDRAM banks, improving overall
system performance.

The asynchronous memory controller can be programmed to
control up to four banks of devices with very flexible timing
parameters for a wide variety of devices. Each bank occupies a
1 Mbyte segment regardless of the size of the devices used, so
that these banks will only be contiguous if each is fully popu-
lated with 1 Mbyte of memory.

Flash Memory

The ADSP-BF538F4 and ADSP-BF538F8 processors contain a
separate flash die, connected to the EBIU bus, within the pack-
age of the processors.

Figure 4 on Page 6

shows how the flash

memory die and Blackfin processor die are connected.

The ADSP-BF538F4 contains a 512 Kbits bottom boot sector
flash memory. The ADSP-BF538F8 contains a 1 Mbit bottom
boot sector flash memory. Features include the following.

· access times as fast as 70 ns (EBIU registers must be set

appropriately)

· sector protection

· one million write cycles per sector

· 20 year data retention

The Blackfin processor connects to the flash memory die with
address, data, chip enable, write enable, and output enable con-
trols as if it were an external memory device.

The flash chip enable pin FCE must be connected to AMS0 or
AMS31 through a printed circuit board trace. When connected
to AMS0 the Blackfin processor can boot from the flash die.

When connected to AMS31 the flash memory will appear as
non-volatile memory in the processor memory map shown in

Figure 3 on Page 5

Flash Memory Programming

The ADSP-BF538F4 and ADSP-BF538F8 flash memory may be
programmed before or after mounting on the printed circuit
board.

To program the flash prior to mounting on the printed circuit
board, use a hardware programming tool that can provide the
data, address, and control stimuli to the flash die through the
external pins on the package. During this programming, V

DDEXT

and GND must be provided to the package and the Blackfin
must be held in reset with bus request (BR) asserted and a
CLKIN provided.

The VisualDSP++

tools may be used to program the flash

memory after the device is mounted on a printed circuit board.

Flash Memory Sector Protection

To use the sector protection feature, a high voltage (+12 V nom-
inal) must be applied to the flash FRESET pin. Refer to the flash
datasheet for details.

I/O Memory Space

Blackfin processors do not define a separate I/O space. All
resources are mapped through the flat 32-bit address space. On-
chip I/O devices have their control registers mapped into mem-
ory mapped registers (MMRs) at addresses near the top of the
4 Gbyte address space. These are separated into two smaller
blocks, one which contains the control MMRs for all core func-
tions, and the other which contains the registers needed for
setup and control of the on-chip peripherals outside of the core.
The MMRs are accessible only in supervisor mode and appear
as reserved space to on-chip peripherals.

Booting

The ADSP-BF538/ADSP-BF538F processors contain a small
boot kernel, which configures the appropriate peripheral for
booting. If the processors are configured to boot from boot
ROM memory space, the processors start executing from the
on-chip boot ROM. For more information, see

Booting Modes

on Page 15

Event Handling

The event controller on the ADSP-BF538/ADSP-BF538F pro-
cessors handle all asynchronous and synchronous events to the
processors. The processor provides event handling that sup-
ports both nesting and prioritization. Nesting allows multiple
event service routines to be active simultaneously. Prioritization
ensures that servicing of a higher priority event takes prece-
dence over servicing of a lower priority event. The controller
provides support for five different types of events:

· Emulation An emulation event causes the processor to

enter emulation mode, allowing command and control of
the processor via the JTAG interface.

· Reset This event resets the processor.

Figure 4. Internal Connection of Flash Memory (ADSP-BF538Fx)

VSS

FRESET

FCE

RESET

DATA15-0

GND

VDDEXT

ADDR19-1

ARE AWE

GND

DATA15-0

ARD

AWE

VCC

BYTE

RESET

AMS3-0

RESET

ARE

ARDY

ADDR19-1

RY/

VDDEXT

ADSP-BF538Fx
package

Blac

kfin

die

Fla

die

AMS3-0

DQ15-0

A18-0

ADSP-BF538/ADSP-BF538F

Preliminary Technical Data

Rev. PrD

Page 7 of 56

May 2006

· Non-maskable interrupt (NMI) The NMI event can be

generated by the software watchdog timer or by the NMI
input signal to the processor. The NMI event is frequently
used as a power-down indicator to initiate an orderly shut-
down of the system.

· Exceptions Events that occur synchronously to program

flow (the exception are taken before the instruction is
allowed to complete). Conditions such as data alignment
violations and undefined instructions cause exceptions.

· Interrupts Events that occur asynchronously to program

flow. They are caused by input pins, timers, and other
peripherals, as well as by an explicit software instruction.

Each event type has an associated register to hold the return
address and an associated return-from-event instruction. When
an event is triggered, the state of the processors are saved on the
supervisor stack.

The ADSP-BF538/ADSP-BF538F processor's event controllers
consist of two stages, the core event controller (CEC) and the
system interrupt controller (SIC). the core event controller
works with the system interrupt controller to prioritize and con-
trol all system events. Conceptually, interrupts from the
peripherals enter into the SIC, and are then routed directly into
the general-purpose interrupts of the CEC.

Core Event Controller (CEC)

The CEC supports nine general-purpose interrupts (IVG157),
in addition to the dedicated interrupt and exception events. Of
these general-purpose interrupts, the two lowest priority inter-
rupts (IVG1514) are recommended to be reserved for software
interrupt handlers, leaving seven prioritized interrupt inputs to

support the peripherals of the processor.

Table 2

describes the

inputs to the CEC, identifies their names in the event vector
table (EVT), and lists their priorities.

System Interrupt Controllers (SIC)

The system interrupt controllers (SIC0, SIC1) provide the map-
ping and routing of events from the many peripheral interrupt
sources to the prioritized general-purpose interrupt inputs of
the CEC. Although the ADSP-BF538/ADSP-BF538F processors
provide a default mapping, the user can alter the mappings and
priorities of interrupt events by writing the appropriate values
into the interrupt assignment registers (IAR).

Table 3

describes

the inputs into the SICs and the default mappings into the CEC.

Table 2. Core Event Controller (CEC)

Priority
(0 is Highest)

Event Class

EVT Entry

Emulation/Test Control

EMU

Reset

RST

Non-Maskable Interrupt

NMI

Exception

EVX

Reserved

Hardware Error

IVHW

Core Timer

IVTMR

General Interrupt 7

IVG7

General Interrupt 8

IVG8

General Interrupt 9

IVG9

General Interrupt 10

IVG10

General Interrupt 11

IVG11

General Interrupt 12

IVG12

General Interrupt 13

IVG13

General Interrupt 14

IVG14

General Interrupt 15

IVG15

Table 3. System and Core Event Mapping

Event Source

Core
Event Name

PLL Wakeup Interrupt

IVG7

DMA Controller 0 Error

IVG7

DMA Controller 1 Error

IVG7

PPI Error Interrupt

IVG7

SPORT0 Error Interrupt

IVG7

SPORT1 Error Interrupt

IVG7

SPORT2 Error Interrupt

IVG7

SPORT3 Error Interrupt

IVG7

SPI0 Error Interrupt

IVG7

SPI1 Error Interrupt

IVG7

SPI2 Error Interrupt

IVG7

UART0 Error Interrupt

IVG7

UART1 Error Interrupt

IVG7

UART2 Error Interrupt

IVG7

CAN Error Interrupt

IVG7

Real Time Clock Interrupts

IVG8

DMA0 Interrupt (PPI)

IVG8

DMA1 Interrupt (SPORT0 RX)

IVG9

DMA2 Interrupt (SPORT0 TX)

IVG9

DMA3 Interrupt (SPORT1 RX)

IVG9

DMA4 Interrupt (SPORT1 TX)

IVG9

DMA8 Interrupt (SPORT2 RX)

IVG9

DMA9 Interrupt (SPORT2 TX)

IVG9

DMA10 Interrupt (SPORT3 RX)

IVG9

DMA11 Interrupt (SPORT3 TX)

IVG9

DMA5 Interrupt (SPI0)

IVG10

DMA14 Interrupt (SPI1)

IVG10

DMA15 Interrupt (SPI2)

IVG10

DMA6 Interrupt (UART0 RX)

IVG10

DMA7 Interrupt (UART0 TX)

IVG10

DMA16 Interrupt (UART1 RX)

IVG10

DMA17 Interrupt (UART1 TX)

IVG10

Rev. PrD

Page 8 of 56

May 2006

ADSP-BF538/ADSP-BF538F

Preliminary Technical Data

Event Control

The ADSP-BF538/ADSP-BF538F processors provide the user
with a very flexible mechanism to control the processing of
events. In the CEC, three registers are used to coordinate and
control events. Each register is 16 bits wide:

· CEC interrupt latch register (ILAT) The ILAT register

indicates when events have been latched. The appropriate
bit is set when the processor has latched the event and
cleared when the event has been accepted into the system.
This register is updated automatically by the controller, but
it may also be written to clear (cancel) latched events. This
register may be read while in supervisor mode and may
only be written while in supervisor mode when the corre-
sponding IMASK bit is cleared.

· CEC interrupt mask register (IMASK) The IMASK regis-

ter controls the masking and unmasking of individual
events. When a bit is set in the IMASK register, that event is
unmasked and will be processed by the CEC when asserted.
A cleared bit in the IMASK register masks the event, pre-
venting the processor from servicing the event even though
the event may be latched in the ILAT register. This register
may be read or written while in supervisor mode. (Note
that general-purpose interrupts can be globally enabled and
disabled with the STI and CLI instructions, respectively.)

· CEC interrupt pending register (IPEND) The IPEND

register keeps track of all nested events. A set bit in the
IPEND register indicates the event is currently active or
nested at some level. This register is updated automatically
by the controller but may be read while in supervisor mode.

The SIC allows further control of event processing by providing
three 32-bit interrupt control and status registers. Each register
contains a bit corresponding to each of the peripheral interrupt
events shown in

Table 3 on Page 7

· SIC interrupt mask registers (SIC_IMASKx) These regis-

ters control the masking and unmasking of each peripheral
interrupt event. When a bit is set in these registers, that
peripheral event is unmasked and will be processed by the
system when asserted. A cleared bit in these registers masks
the peripheral event, preventing the processor from servic-
ing the event.

· SIC interrupt status registers (SIC_ISRx) As multiple

peripherals can be mapped to a single event, these registers
allow the software to determine which peripheral event
source triggered the interrupt. A set bit indicates the
peripheral is asserting the interrupt, and a cleared bit indi-
cates the peripheral is not asserting the event.

· SIC interrupt wakeup enable registers (SIC_IWRx) By

enabling the corresponding bit in these registers, a periph-
eral can be configured to wake up the processor, should the
core be idled when the event is generated. (

For more infor-

mation, see Dynamic Power Management on Page 12.

)

Because multiple interrupt sources can map to a single general-
purpose interrupt, multiple pulse assertions can occur simulta-
neously, before or during interrupt processing for an interrupt
event already detected on this interrupt input. The IPEND reg-
ister contents are monitored by the SIC as the interrupt
acknowledgement.

The appropriate ILAT register bit is set when an interrupt rising
edge is detected (detection requires two core clock cycles). The
bit is cleared when the respective IPEND register bit is set. The
IPEND bit indicates that the event has entered into the proces-
sor pipeline. At this point the CEC will recognize and queue the
next rising edge event on the corresponding event input. The
minimum latency from the rising edge transition of the general-
purpose interrupt to the IPEND output asserted is three core
clock cycles; however, the latency can be much higher, depend-
ing on the activity within and the state of the processor.

DMA CONTROLLERS

The ADSP-BF538/ADSP-BF538F processors have multiple,
independent DMA controllers that support automated data
transfers with minimal overhead for the processor core. DMA
transfers can occur between the processor internal memories
and any of its DMA capable peripherals. Additionally, DMA
transfers can be accomplished between any of the DMA capable
peripherals and external devices connected to the external
memory interfaces, including the SDRAM controller and the
asynchronous memory controller. DMA capable peripherals
include the SPORTs, SPI port, UART, and PPI. Each individual
DMA capable peripheral has at least one dedicated DMA
channel.

The DMA controllers support both 1-dimensional (1D) and 2-
dimensional (2D) DMA transfers. DMA transfer initialization
can be implemented from registers or from sets of parameters
called descriptor blocks.

The 2D DMA capability supports arbitrary row and column
sizes up to 64K elements by 64K elements, and arbitrary row
and column step sizes up to ±32K elements. Furthermore, the
column step size can be less than the row step size, allowing

DMA18 Interrupt (UART2 RX)

IVG10

DMA19 Interrupt (UART2 TX)

IVG10

Timer0, Timer1, Timer2 Interrupts

IVG11

TWI0 Interrupt

IVG11

TWI1 Interrupt

IVG11

CAN Receive Interrupt

IVG11

CAN Transmit Interrupt

IVG11

Port F GPIO Interrupts A and B

IVG12

MDMA0 Stream 0 Interrupt

IVG13

MDMA0 Stream 1 Interrupt

IVG13

MDMA1 Stream 0 Interrupt

IVG13

MDMA1 Stream 1 Interrupt

IVG13

Software Watchdog Timer

IVG13

Table 3. System and Core Event Mapping (Continued)

Event Source

Core
Event Name

ADSP-BF538/ADSP-BF538F

Preliminary Technical Data

Rev. PrD

Page 9 of 56

May 2006

implementation of interleaved data streams. This feature is
especially useful in video applications where data can be de-
interleaved on the fly.

Examples of DMA types supported by the processor DMA con-
troller include:

· A single, linear buffer that stops upon completion

· A circular, auto-refreshing buffer that interrupts on each

full or fractionally full buffer

· 1-D or 2-D DMA using a linked list of descriptors

· 2-D DMA using an array of descriptors, specifying only the

base DMA address within a common page

In addition to the dedicated peripheral DMA channels, there are
four memory DMA channels provided for transfers between the
various memories of the ADSP-BF538/ADSP-BF538F proces-
sor's systems. This enables transfers of blocks of data between
any of the memories--including external SDRAM, ROM,
SRAM, and flash memory--with minimal processor interven-
tion. Memory DMA transfers can be controlled by a very
flexible descriptor based methodology or by a standard register
based autobuffer mechanism.

REAL TIME CLOCK

The ADSP-BF538/ADSP-BF538F processor's real time clock
(RTC) provides a robust set of digital watch features, including
current time, stopwatch, and alarm. The RTC is clocked by a
32.768 KHz crystal external to the processor. The RTC periph-
eral has dedicated power supply pins so that it can remain
powered up and clocked even when the rest of the processors
are in a low power state. The RTC provides several programma-
ble interrupt options, including interrupt per second, minute,
hour, or day clock ticks, interrupt on programmable stopwatch
countdown, or interrupt at a programmed alarm time.

The 32.768 KHz input clock frequency is divided down to a
1 Hz signal by a prescaler. The counter function of the timer
consists of four counters: a 60 second counter, a 60 minute
counter, a 24 hour counter, and an 32,768 day counter.

When enabled, the alarm function generates an interrupt when
the output of the timer matches the programmed value in the
alarm control register. There are two alarms: The first alarm is
for a time of day. The second alarm is for a day and time of that
day.

The stopwatch function counts down from a programmed
value, with one second resolution. When the stopwatch is
enabled and the counter underflows, an interrupt is generated.

Like the other peripherals, the RTC can wake up the ADSP-
BF538/ADSP-BF538F processor from sleep mode upon genera-
tion of any RTC wakeup event. Additionally, an RTC wakeup
event can wake up the processor from deep sleep mode, and
wake up the on-chip internal voltage regulator from a powered
down state.

Connect RTC pins RTXI and RTXO with external components
as shown in

Figure 5

WATCHDOG TIMER

The ADSP-BF538/ADSP-BF538F processors include a 32-bit
timer that can be used to implement a software watchdog func-
tion. A software watchdog can improve system availability by
forcing the processor to a known state through generation of a
hardware reset, non-maskable interrupt (NMI), or general-pur-
pose interrupt, if the timer expires before being reset by
software. The programmer initializes the count value of the
timer, enables the appropriate interrupt, then enables the timer.
Thereafter, the software must reload the counter before it
counts to zero from the programmed value. This protects the
system from remaining in an unknown state where software,
which would normally reset the timer, has stopped running due
to an external noise condition or software error.

If configured to generate a hardware reset, the watchdog timer
resets both the core and the processor peripherals. After a reset,
software can determine if the watchdog was the source of the
hardware reset by interrogating a status bit in the watchdog
timer control register.

The timer is clocked by the system clock (SCLK), at a maximum
frequency of f

SCLK

TIMERS

There are four general-purpose programmable timer units in
the ADSP-BF538/ADSP-BF538F processors. Three timers have
an external pin that can be configured either as a pulse width
modulator (PWM) or timer output, as an input to clock the
timer, or as a mechanism for measuring pulse widths and peri-
ods of external events. These timers can be synchronized to an
external clock input to the PF1 pin, an external clock input to
the PPI_CLK pin, or to the internal SCLK.

The timer units can be used in conjunction with the UART to
measure the width of the pulses in the data stream to provide an
auto-baud detect function for a serial channel.

The timers can generate interrupts to the processor core provid-
ing periodic events for synchronization, either to the system
clock or to a count of external signals.

Figure 5. External Components for RTC

RTXO

SUGGESTED COMPONENTS:
ECLIPTEK EC38J (THROUGH-HOLE PACKAGE)
EPSON MC405 12 PF LOAD (SURFACE MOUNT PACKAGE)
C1 = 22 PF
C2 = 22 PF
R1 = 10M OHM

NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECIFIED FOR X1.
CONTACT CRYSTAL MANUFACTURER FOR DETAILS. C1 AND C2
SPECIFICATIONS ASSUME BOARD TRACE CAPACITANCE OF 3 PF.

RTXI

Rev. PrD

Page 10 of 56

May 2006

ADSP-BF538/ADSP-BF538F

Preliminary Technical Data

In addition to the three general-purpose programmable timers,
a fourth timer is also provided. This extra timer is clocked by the
internal processor clock and is typically used as a system tick
clock for generation of operating system periodic interrupts.

SERIAL PORTS (SPORTs)

The ADSP-BF538/ADSP-BF538F processors incorporate four
dual-channel synchronous serial ports for serial and multipro-
cessor communications. The SPORTs support the following
features:

· I

S capable operation.

· Bidirectional operation Each SPORT has two sets of inde-

pendent transmit and receive pins, enabling eight channels
of I

S stereo audio.

· Buffered (8-deep) transmit and receive ports Each port

has a data register for transferring data words to and from
other processor components and shift registers for shifting
data in and out of the data registers.

· Clocking Each transmit and receive port can either use an

external serial clock or generate its own, in frequencies
ranging from (f

SCLK

/131,070) Hz to (f

SCLK

/2) Hz.

· Word length Each SPORT supports serial data words

from 3 to 32 bits in length, transferred most significant bit
first or least significant bit first.

· Framing Each transmit and receive port can run with or

without frame sync signals for each data word. Frame sync
signals can be generated internally or externally, active high
or low, and with either of two pulsewidths and early or late
frame sync.

· Companding in hardware Each SPORT can perform

A-law or -law companding according to ITU recommen-
dation G.711. Companding can be selected on the transmit
and/or receive channel of the SPORT without additional
latencies.

· DMA operations with single-cycle overhead Each SPORT

can automatically receive and transmit multiple buffers of
memory data. The processor can link or chain sequences of
DMA transfers between a SPORT and memory.

· Interrupts Each transmit and receive port generates an

interrupt upon completing the transfer of a data word or
after transferring an entire data buffer or buffers through
DMA.

· Multichannel capability Each SPORT supports 128 chan-

nels out of a 1024 channel window and is compatible with
the H.100, H.110, MVIP-90, and HMVIP standards.

SERIAL PERIPHERAL INTERFACE (SPI) PORTS

The ADSP-BF538/ADSP-BF538F processors incorporate three
SPI compatible ports that enable the processor to communicate
with multiple SPI compatible devices.

The SPI interface uses three pins for transferring data: two data
pins (master output-slave input, MOSIx, and master input-slave
output, MISOx) and a clock pin (serial clock, SCKx). An SPI
chip select input pin (SPIxSS) lets other SPI devices select the

processor. For SPI0, seven SPI chip select output pins
(SPI0SEL71) let the processor select other SPI devices. The SPI
select pins are reconfigured GPIO pins. SPI1 and SPI2 have a
single SPI select for SPI point-to-point communication. Using
these pins, the SPI ports provide a full-duplex, synchronous
serial interface, which supports both master/slave modes and
multimaster environments.

The SPI ports' baud rate and clock phase/polarities are pro-
grammable, and it has an integrated DMA controller,
configurable to support transmit or receive data streams. Each
SPI's DMA controller can only service unidirectional accesses at
any given time.

The SPI port's clock rate is calculated as:

Where the 16-bit SPIx_BAUD register contains a value of 2 to
65,535.

During transfers, the SPI port simultaneously transmits and
receives by serially shifting data in and out on its two serial data
lines. The serial clock line synchronizes the shifting and sam-
pling of data on the two serial data lines.

TWO WIRE INTERFACE

The ADSP-BF538/ADSP-BF538F processors have 2 two wire
interface (TWI) modules that are compatible with the Philips
Inter-IC bus standard. The TWI modules offer the capabilities
of simultaneous master and slave operation, support for 7-bit
addressing and multimedia data arbitration. The TWI also
includes master clock synchronization and support for clock
low extension.

The TWI interface uses two pins for transferring clock (SCLx)
and data (SDAx) and supports the protocol at speeds up to
400 kbits/sec.

The TWI interface pins are compatible with 5V logic levels.

UART PORTs

The ADSP-BF538/ADSP-BF538F processors incorporate three
full-duplex Universal Asynchronous Receiver/Transmitter
(UART) ports, which are fully compatible with PC standard
UARTs. The UART ports provide a simplified UART interface
to other peripherals or hosts, supporting full-duplex, DMA sup-
ported, asynchronous transfers of serial data. The UART ports
include support for 5 to 8 data bits, 1 or 2 stop bits, and none,
even, or odd parity. The UART ports support two modes of
operation:

· PIO (programmed I/O) The processor sends or receives

data by writing or reading I/O mapped UART registers.
The data is double buffered on both transmit and receive.

· DMA (direct memory access) The DMA controller trans-

fers both transmit and receive data. This reduces the
number and frequency of interrupts required to transfer
data to and from memory. Each UART has two dedicated

SPI Clock Rate

SCLK

SPIx_BAUD

---------------------------------------

ADSP-BF538/ADSP-BF538F

Preliminary Technical Data

Rev. PrD

Page 11 of 56

May 2006

DMA channels, one for transmit and one for receive. These
DMA channels have lower default priority than most DMA
channels because of their relatively low service rates.

The UART port's baud rate, serial data format, error code gen-
eration and status, and interrupts are programmable:

· Supporting bit rates ranging from (f

SCLK

/ 1,048,576) to

SCLK

/16) bits per second.

· Supporting data formats from 7 to12 bits per frame.

· Both transmit and receive operations can be configured to

generate maskable interrupts to the processor.

The UART port's clock rate is calculated as:

Where the 16-bit UART_Divisor comes from the UARTx_DLH
register (most significant 8 bits) and UARTx_DLL register (least
significant 8 bits).

In conjunction with the general-purpose timer functions, auto-
baud detection is supported.

The capabilities of the UARTs are further extended with sup-
port for the Infrared Data Association (IrDA

) Serial Infrared

Physical Layer Link Specification (SIR) protocol.

GENERAL-PURPOSE PORTS

The ADSP-BF538/ADSP-BF538F processors have up to 54 gen-
eral-purpose I/O pins that are multiplexed with other
peripherals. They are arranged into ports C, D, E, and F as
shown in

Table 4

The general-purpose I/O pins may be individually controlled by
manipulation of the control and status registers. These pins may
be polled to determine their status.

· GPIO direction control register Specifies the direction of

each individual GPIOx pin as input or output.

· GPIO control and status registers The processor employs

a "write one to modify" mechanism that allows any combi-
nation of individual GPIO to be modified in a single
instruction, without affecting the level of any other GPIO.
Four control registers and a data register are provided for
each GPIO port. One register is written in order to set
GPIO values, one register is written in order to clear GPIO
values, one register is written in order to toggle GPIO val-
ues, and one register is written in order to specify a GPIO
input or output. Reading the GPIO Data allows software to
determine the state of the input GPIO pins.

In addition to the GPIO function described above, the 16 port F
pins can be individually configured to generate interrupts.

· Flag interrupt mask registers The two Flag interrupt

mask registers allow each individual PFx pin to function as
an interrupt to the processor. similar to the two flag control
registers that are used to set and clear individual flag values,
one flag interrupt mask register sets bits to enable interrupt
function, and the other flag interrupt mask register clears
bits to disable interrupt function. PFx pins defined as

inputs can be configured to generate hardware interrupts,
while output PFx pins can be triggered by software
interrupts.

· Flag interrupt sensitivity registers The two flag interrupt

sensitivity registers specify whether individual PFx pins are
level- or edge-sensitive and specify--if edge-sensitive--
whether just the rising edge or both the rising and falling
edges of the signal are significant. One register selects the
type of sensitivity, and one register selects which edges are
significant for edge-sensitivity.

PARALLEL PERIPHERAL INTERFACE

The ADSP-BF538/ADSP-BF538F processors provide a parallel
peripheral interface (PPI) that can connect directly to parallel
A/D and D/A converters, video encoders and decoders, and
other general-purpose peripherals. The PPI consists of a dedi-
cated input clock pin, up to 3 frame synchronization pins, and
at up to 16 data pins. The input clock supports parallel data rates
at up to f

SCLK

/2 MHz, and the synchronization signals can be con-

figured as either inputs or outputs.

The PPI supports a variety of general-purpose and ITU-R 656
modes of operation. In general-purpose mode, the PPI provides
half-duplex, bi-directional data transfer with up to 16 bits of
data. Up to 3 frame synchronization signals are also provided.
In ITU-R 656 mode, the PPI provides half-duplex, bi-direc-
tional transfer of 8- or 10-bit video data. Additionally, on-chip
decode of embedded start-of-line (SOL) and start-of-field (SOF)
preamble packets is supported.

General-Purpose Mode Descriptions

The general-purpose modes of the PPI are intended to suit a
wide variety of data capture and transmission applications.
Three distinct submodes are supported:

· Input mode frame syncs and data are inputs into the PPI.

· Frame capture mode frame syncs are outputs from the

PPI, but data are inputs.

· Output mode frame syncs and data are outputs from the

PPI.

UART Clock Rate

SCLK

UART_Divisor

-----------------------------------------------

Table 4. GPIO Ports

Peripheral

Alternate GPIO Port Function

PPI

GPIO Port F150

SPORT2

GPIO Port E70

SPORT3

GPIO Port E158

SPI1

GPIO Port D40

SPI2

GPIO Port D95

UART1

GPIO Port D1110

UART2

GPIO Port D1312

CAN

GPIO Port C10

GPIO

GPIO Port C94

Rev. PrD

Page 12 of 56

May 2006

ADSP-BF538/ADSP-BF538F

Preliminary Technical Data

Input Mode

Input mode is intended for ADC applications, as well as video
communication with hardware signaling. In its simplest form,
PPI_FS1 is an external frame sync input that controls when to
read data. The PPI_DELAY MMR allows for a delay (in
PPI_CLK cycles) between reception of this frame sync and the
initiation of data reads. The number of input data samples is
user programmable and defined by the contents of the
PPI_Count register. Data widths of 8-bits, and 10-bits through
16-bits are supported, and are programmed using the
PPI_CONTROL register.

Frame Capture Mode

Frame capture mode allows the video source(s) to act as a slave
(e.g., for frame capture). The ADSP-BF538/ADSP-BF538F pro-
cessors control when to read from the video source(s). PPI_FS1
is an HSYNC output and PPI_FS2 is a VSYNC output.

Output Mode

Output mode is used for transmitting video or other data with
up to three output frame syncs. Typically, a single frame sync is
appropriate for data converter applications, whereas two or
three frame syncs could be used for sending video with hard-
ware signaling.

ITU-R 656 Mode Descriptions

The ITU-R 656 modes of the PPI are intended to suit a wide
variety of video capture, processing, and transmission applica-
tions. Three distinct submodes are supported:

· Active video only mode

· Vertical blanking only mode

· Entire field mode

Active Video Only Mode

Active video only mode is used when only the active video por-
tion of a field is of interest and not any of the blanking intervals.
The PPI does not read in any data between the end of active
video (EAV) and start of active video (SAV) preamble symbols,
or any data present during the vertical blanking intervals. In this
mode, the control byte sequences are not stored to memory;
they are filtered by the PPI. After synchronizing to the start of
Field 1, the PPI ignores incoming samples until it sees an SAV
code. The user specifies the number of active video lines per
frame (in PPI_Count register).

Vertical Blanking Interval Mode

In this mode, the PPI only transfers vertical blanking interval
(VBI) data.

Entire Field Mode

In this mode, the entire incoming bit stream is read in through
the PPI. This includes active video, control preamble sequences,
and ancillary data that may be embedded in horizontal and ver-
tical blanking intervals. Data transfer starts immediately after
synchronization to Field 1. Data is transferred to or from the
synchronous channels through eight DMA engines that work
autonomously from the processor core.

CONTROLLER AREA NETWORK (CAN) INTERFACE

The ADSP-BF538/ADSP-BF538F processors provide a CAN
controller that is a communication controller implementing the
Controller Area Network (CAN) V2.0B protocol. This protocol
is an asynchronous communications protocol used in both
industrial and automotive control systems. CAN is well suited
for control applications due to its capability to communicate
reliably over a network since the protocol incorporates CRC
checking message error tracking, and fault node confinement.

The CAN controller is based on a 32 entry mailbox RAM and
supports both the standard and extended identifier (ID) mes-
sage formats specified in the CAN protocol specification,
revision 2.0, part B.

Each mailbox consists of eight 16-bit data words. The data is
divided into fields, which includes a message identifier, a time
stamp, a byte count, up to 8 bytes of data, and several control
bits. Each node monitors the messages being passed on the net-
work. If the identifier in the transmitted message matches an
identifier in one of it's mailboxes, then the module knows that
the message was meant for it, passes the data into it's appropri-
ate mailbox, and signals the processor of message arrival with an
interrupt.

The CAN controller can wake up the processor from sleep mode
upon generation of a wakeup event, such that the processor can
be maintained in a low power mode during idle conditions.
Additionally, a CAN wakeup event can wake up the processor
from deep sleep, and wake up the on-chip internal voltage regu-
lator from a powered-down state.

The electrical characteristics of each network connection are
very stringent, therefore the CAN interface is typically divided
into 2 parts: a controller and a transceiver. This allows a single
controller to support different drivers and CAN networks. The
ADSP-BF538/ADSP-BF538F CAN module represents the con-
troller part of the interface. This module's network I/O is a
single transmit output and a single receive input, which connect
to a line transceiver.

The CAN clock is derived from the processor system clock
(SCLK) through a programmable divider and therefore does not
require an additional crystal.

DYNAMIC POWER MANAGEMENT

The ADSP-BF538/ADSP-BF538F processors provide five oper-
ating modes, each with a different performance/power profile.
In addition, dynamic power management provides the control
functions to dynamically alter the processor core supply voltage,
further reducing power dissipation. Control of clocking to each
of the processor peripherals also reduces power consumption.
See

Table 5

for a summary of the power settings for each mode.

Full-On Operating Mode--Maximum Performance

In the full-on mode, the PLL is enabled and is not bypassed,
providing capability for maximum operational frequency. This
is the powerup default execution state in which maximum per-
formance can be achieved. The processor core and all enabled
peripherals run at full speed.

ADSP-BF538/ADSP-BF538F

Preliminary Technical Data

Rev. PrD

Page 13 of 56

May 2006

Active Operating Mode--Moderate Power Savings

In the active mode, the PLL is enabled but bypassed. Because the
PLL is bypassed, the processor's core clock (CCLK) and system
clock (SCLK) run at the input clock (CLKIN) frequency. In this
mode, the CLKIN to CCLK multiplier ratio can be changed,
although the changes are not realized until the full-on mode is
entered. DMA access is available to appropriately configured L1
memories.

In the active mode, it is possible to disable the PLL through the
PLL Control register (PLL_CTL). If disabled, the PLL must be
re-enabled before transitioning to the Full-On or Sleep modes.

Sleep Operating Mode--High Dynamic Power Savings

The sleep mode reduces dynamic power dissipation by disabling
the clock to the processor core (CCLK). The PLL and system
clock (SCLK), however, continue to operate in this mode. Typi-
cally an external event or RTC activity will wake up the
processor. When in the Sleep mode, assertion of wakeup causes
the processor to sense the value of the BYPASS bit in the PLL
control register (PLL_CTL). If BYPASS is disabled, the proces-
sor transitions to the full on mode. If BYPASS is enabled, the
processor will transition to the Active mode. When in the sleep
mode, system DMA access to L1 memory is not supported.

Deep Sleep Operating Mode--Maximum Dynamic Power
Savings

The deep sleep mode maximizes dynamic power savings by dis-
abling the clocks to the processor core (CCLK) and to all
synchronous peripherals (SCLK). Asynchronous peripherals
such as the RTC may still be running, but will not be able to
access internal resources or external memory. This powered
down mode can only be exited by assertion of the reset interrupt
(RESET) or by an asynchronous interrupt generated by the
RTC. When in deep sleep mode, an RTC asynchronous inter-
rupt causes the processor to transition to the active mode.
Assertion of RESET while in deep sleep mode causes the proces-
sor to transition to the Full On mode.

Hibernate Operating Mode--Maximum Static Power
Savings

The hibernate mode maximizes static power savings by dis-
abling the voltage and clocks to the processor core (CCLK) and
to all the synchronous peripherals (SCLK). The internal voltage
regulator for the processor can be shut off by writing b#00 to the

FREQ bits of the VR_CTL register. This disables both CCLK
and SCLK. Furthermore, it sets the internal power supply volt-
age (V

DDINT

) to 0 V to provide the lowest static power dissipation.

Any critical information stored internally (memory contents,
register contents, etc.) must be written to a non-volatile storage
device prior to removing power if the processor state is to be
preserved. Since V

DDEXT

is still supplied in this mode, all of the

external pins three-state, unless otherwise specified. This allows
other devices that may be connected to the processor to have
power still applied without drawing unwanted current. The
internal supply regulator can be woken up either by a real time
clock wakeup, by CAN bus traffic, by asserting the RESET pin
or by an external source.

Power Savings

As shown in

Table 6

, the ADSP-BF538/ADSP-BF538F proces-

sors support three different power domains. The use of multiple
power domains maximizes flexibility, while maintaining com-
pliance with industry standards and conventions. By isolating
the internal logic of the processor into its own power domain,
separate from the RTC and other I/O, the processor can take
advantage of Dynamic Power Management, without affecting
the RTC or other I/O devices. There are no sequencing require-
ments for the various power domains.

The power dissipated by a processors are largely a function of
the clock frequency of the processors and the square of the oper-
ating voltage. For example, reducing the clock frequency by 25%
results in a 25% reduction in power dissipation, while reducing
the voltage by 25% reduces power dissipation by more than
40%. Further, these power savings are additive, in that if the
clock frequency and supply voltage are both reduced, the power
savings can be dramatic.

The dynamic power management feature of the processor
allows both the processor's input voltage (V

DDINT

) and clock fre-

quency (f

CCLK

) to be dynamically controlled.

The savings in power dissipation can be modeled using the
power savings factor and % power savings calculations.

The power savings factor is calculated as:

where the variables in the equations are:

· f

CCLKNOM

is the nominal core clock frequency

· f

CCLKRED

is the reduced core clock frequency

· V

DDINTNOM

is the nominal internal supply voltage

Table 5. Power Settings

Mode

PLL

PLL
Bypassed

Core
Clock
(CCLK)

System
Clock
(SCLK)

Core
Power

Full On

Enabled

Active

Enabled/
Disabled

Yes

Enabled

Sleep

Enabled

Disabled

Enabled

Deep Sleep Disabled

Disabled

Disabled On

Hibernate

Disabled

Disabled Off

Table 6. Power Domains

Power Domain

VDD Range

RTC crystal I/O and logic

VDDRTC

All internal logic except RTC

VDDINT

All I/O except RTC

VDDEXT

Power Savings Factor

CCLKRED

CCLKNOM

--------------------------

DDINTRED

DDINTNOM

--------------------------------

RED

NOM

---------------

Rev. PrD

Page 14 of 56

May 2006

ADSP-BF538/ADSP-BF538F

Preliminary Technical Data

· V

DDINTRED

is the reduced internal supply voltage

· T

NOM

is the duration running at f

CCLKNOM

· T

RED

is the duration running at f

CCLKRED

The Power Savings Factor is calculated as:

VOLTAGE REGULATION

The Blackfin processor provides an on-chip voltage regulator
that can generate processor core voltage levels 0.8 V to
1.2V(5%/+10%) from an external 2.7 V to 3.6 V supply.

Figure 6

shows the typical external components required to

complete the power management system.

The regulator con-

trols the internal logic voltage levels and is programmable with
the voltage regulator control register (VR_CTL) in increments
of 50 mV. To reduce standby power consumption, the internal
voltage regulator can be programmed to remove power to the
processor core while I/O power (V

DDRTC

, V

DDEXT

) is still supplied.

While in hibernate mode, I/O power is still being applied, elimi-
nating the need for external buffers. The voltage regulator can
be activated from this power-down state either through an RTC
wakeup, a CAN wakeup, a general-purpose wakeup, or by
asserting RESET, which will then initiate a boot sequence. The
regulator can also be disabled and bypassed at the user's
discretion.

CLOCK SIGNALS

The ADSP-BF538/ADSP-BF538F processors can be clocked by
an external crystal, a sine wave input, or a buffered, shaped
clock derived from an external clock oscillator.

If an external clock is used, it should be a TTL compatible signal
and must not be halted, changed, or operated below the speci-
fied frequency during normal operation. This signal is
connected to the processor's CLKIN pin. When an external
clock is used, the XTAL pin must be left unconnected.

Alternatively, because the ADSP-BF538/ADSP-BF538F proces-
sors include an on-chip oscillator circuit, an external crystal
may be used. The crystal should be connected across the CLKIN
and XTAL pins, with two capacitors connected as shown in

Figure 7

. Capacitor values are dependent on crystal type and

should be specified by the crystal manufacturer. A parallel-reso-
nant, fundamental frequency, microprocessor-grade crystal
should be used.

As shown in

Figure 8 on Page 14

, the core clock (CCLK) and

system peripheral clock (SCLK) are derived from the input
clock (CLKIN) signal. An on-chip PLL is capable of multiplying
the CLKIN signal by a user programmable 1× to 63× multiplica-
tion factor (bounded by specified minimum and maximum
VCO frequencies). The default multiplier is 10×, but it can be
modified by a software instruction sequence. On-the-fly fre-
quency changes can be effected by simply writing to the
PLL_DIV register.

All on-chip peripherals are clocked by the system clock (SCLK).
The system clock frequency is programmable by means of the
SSEL30 bits of the PLL_DIV register. The values programmed
into the SSEL fields define a divide ratio between the PLL output
(VCO) and the system clock. SCLK divider values are 1 through
15.

Table 7

illustrates typical system clock ratios:

See EE-228: Switching Regulator Design Considerations for ADSP-BF533

Blackfin Processors.

Figure 6. Voltage Regulator Circuit

% Power Savings

Power Savings Factor

(

) 100%

DDEXT

DDINT

OUT

1-0

EXTERNAL COMPONENTS

2.25V - 3.6V
INPUT VOLTAGE
RANGE

FDS9431A

ZHCS1000

100 µF

1 µF

10 µH

0.1 µF

NOTE: VR

OUT

1-0 SHOULD BE TIED TOGETHER EXTERNALLY

AND DESIGNER SHOULD MINIMIZE TRACE LENGTH TO FDS9431A.

100 µF

Figure 7. External Crystal Connections

Figure 8. Frequency Modification Methods

Table 7. Example System Clock Ratios

Signal Name
SSEL30

Divider Ratio
VCO/SCLK

Example Frequency Ratios (MHz)

VCO

SCLK

0001

1:1

100

0110

6:1

300

1010

10:1

500

CLKIN

CLKOUT

XTAL

BLACKFIN

PROCESSOR

PLL

0.5x - 64x

1:15

1, 2, 4, 8

VCO

CLKI N

"FINE" ADJUSTMENT

REQUIRES PLL SEQUENCING

"COURSE" ADJUSTMENT

O N-THE-F LY

CCLK

SCLK

CCLK

SCLK

133 MHz

ADSP-BF538/ADSP-BF538F

Preliminary Technical Data

Rev. PrD

Page 15 of 56

May 2006

The maximum frequency of the system clock is f

SCLK

. Note that

the divisor ratio must be chosen to limit the system clock fre-
quency to its maximum of f

SCLK

. The SSEL value can be changed

dynamically without any PLL lock latencies by writing the
appropriate values to the PLL divisor register (PLL_DIV).

Note that when the SSEL value is changed, it will affect all the
peripherals that derive their clock signals from the SCLK signal.

The core clock (CCLK) frequency can also be dynamically
changed by means of the CSEL10 bits of the PLL_DIV register.
Supported CCLK divider ratios are 1, 2, 4, and 8, as shown in

Table 8

. This programmable core clock capability is useful for

fast core frequency modifications.

BOOTING MODES

The ADSP-BF538/ADSP-BF538F processors have three mecha-
nisms (listed in

Table 9

) for automatically loading internal L1

instruction memory after a reset. A fourth mode is provided to
execute from external memory, bypassing the boot sequence.

The BMODE pins of the reset configuration register, sampled
during power-on resets and software initiated resets, implement
the following modes:

· Execute from 16-bit external memory Execution starts

from address 0x2000 0000 with 16-bit packing. The boot
ROM is bypassed in this mode. All configuration settings
are set for the slowest device possible (3-cycle hold time;
15-cycle R/W access times; 4-cycle setup).

· Boot from 8-bit or 16-bit external flash memory The 8-bit

flash boot routine located in boot ROM memory space is
set up using asynchronous memory bank 0. If FCE is con-
nected to AMS0, then the on-chip flash is booted from the

ADSP-BF538F. All configuration settings are set for the
slowest device possible (3-cycle hold time; 15-cycle R/W
access times; 4-cycle setup).

· Boot from SPI serial EEPROM/flash (8-, 16-, or 24-bit

addressable, or Atmel AT45DB041, AT45DB081, or
AT45DB161) The SPI uses the PF2 output pin to select a
single SPI EEPROM/flash device, submits a read command
and successive address bytes (0x00) until a valid 8-, 16-, or
24-bit, or Atmel addressable device is detected, and begins
clocking data into the processor at the beginning of L1
instruction memory.

· Boot from SPI host device The Blackfin processor oper-

ates in SPI slave mode and is configured to receive the bytes
of the .LDR file from an SPI host (master) agent. To hold
off the host device from transmitting while the boot ROM
is busy, the Blackfin processor asserts a GPIO pin, called
host wait (HWAIT), to signal the host device not to send
any more bytes until the flag is deasserted. The flag is cho-
sen by the user and this information is transferred to the
Blackfin processor via bits 10:5 of the FLAG header.

For each of the boot modes, a 10-byte header is first read from
an external memory device. The header specifies the number of
bytes to be transferred and the memory destination address.
Multiple memory blocks may be loaded by any boot sequence.
Once all blocks are loaded, program execution commences from
the start of L1 instruction SRAM.

In addition, bit 4 of the reset configuration register can be set by
application code to bypass the normal boot sequence during a
software reset. For this case, the processor jumps directly to the
beginning of L1 instruction memory.

To augment the boot modes, a secondary software loader is pro-
vided that adds additional booting mechanisms. This secondary
loader provides the capability to boot from 16-bit flash memory,
fast flash, variable baud rate, and other sources. In all boot
modes except bypass, program execution starts from on-chip L1
memory address 0xFFA0 0000.

INSTRUCTION SET DESCRIPTION

The Blackfin processor family assembly language instruction set
employs an algebraic syntax designed for ease of coding and
readability. The instructions have been specifically tuned to pro-
vide a flexible, densely encoded instruction set that compiles to
a very small final memory size. The instruction set also provides
fully featured multifunction instructions that allow the pro-
grammer to use many of the processor core resources in a single
instruction. Coupled with many features more often seen on
microcontrollers, this instruction set is very efficient when com-
piling C and C++ source code. In addition, the architecture
supports both user (algorithm/application code) and supervisor
(O/S kernel, device drivers, debuggers, ISRs) modes of opera-
tion, allowing multiple levels of access to core processor
resources.

Table 8. Core Clock Ratios

Signal Name
CSEL10

Divider Ratio
VCO/CCLK

Example Frequency Ratios

VCO

CCLK

1:1

300

2:1

300

150

4:1

500

125

8:1

200

Table 9. Booting Modes

BMODE1 0 Description

Execute from 16-bit external memory
(bypass boot ROM)

Boot from 8-bit or 16-bit flash (ADSP-BF538 only) or
Boot from on board flash (ADSP-BF538F only)

Boot from SPI serial master

Boot from SPI serial slave EEPROM /flash
(8-,16-, or 24-bit address range, or Atmel
AT45DB041, AT45DB081, or AT45DB161serial flash)

Rev. PrD

Page 16 of 56

May 2006

ADSP-BF538/ADSP-BF538F

Preliminary Technical Data

The assembly language, which takes advantage of the proces-
sor's unique architecture, offers the following advantages:

· Seamlessly integrated DSP/CPU features are optimized for

both 8-bit and 16-bit operations.

· A multi-issue load/store modified Harvard architecture,

which supports two 16-bit MAC or four 8-bit ALU plus
two load/store plus two pointer updates per cycle.

· All registers, I/O, and memory are mapped into a unified

4 Gbyte memory space, providing a simplified program-
ming model.

· Microcontroller features, such as arbitrary bit and bit-field

manipulation, insertion, and extraction; integer operations
on 8-, 16-, and 32-bit data types; and separate user and
supervisor stack pointers.

· Code density enhancements, which include intermixing of

16- and 32-bit instructions (no mode switching, no code
segregation). Frequently used instructions are encoded in
16 bits.

DEVELOPMENT TOOLS

The ADSP-BF538/ADSP-BF538F processors are supported with
a complete set of CROSSCORE

software and hardware devel-

opment tools, including Analog Devices emulators and
VisualDSP++

development environment. The same emulator

hardware that supports other Blackfin processors also fully
emulates the ADSP-BF538/ADSP-BF538F processors.

The VisualDSP++ project management environment lets pro-
grammers develop and debug an application. This environment
includes an easy to use assembler (which is based on an alge-
braic syntax), an archiver (librarian/library builder), a linker, a
loader, a cycle-accurate instruction-level simulator, a C/C++
compiler, and a C/C++ runtime library that includes DSP and
mathematical functions. A key point for these tools is C/C++
code efficiency. The compiler has been developed for efficient
translation of C/C++ code to processor assembly. The proces-
sors have architectural features that improve the efficiency of
compiled C/C++ code.

The VisualDSP++ debugger has a number of important fea-
tures. Data visualization is enhanced by a plotting package that
offers a significant level of flexibility. This graphical representa-
tion of user data enables the programmer to quickly determine
the performance of an algorithm. As algorithms grow in com-
plexity, this capability can have increasing significance on the
designer's development schedule, increasing productivity. Sta-
tistical profiling enables the programmer to non intrusively poll
the processors as they are running the program. This feature,
unique to VisualDSP++, enables the software developer to pas-
sively gather important code execution metrics without
interrupting the real time characteristics of the program. Essen-
tially, the developer can identify bottlenecks in software quickly
and efficiently. By using the profiler, the programmer can focus
on those areas in the program that impact performance and take
corrective action.

Debugging both C/C++ and assembly programs with the
VisualDSP++ debugger, programmers can:

· View mixed C/C++ and assembly code (interleaved source

and object information).

· Insert breakpoints.

· Set conditional breakpoints on registers, memory,

and stacks.

· Trace instruction execution.

· Perform linear or statistical profiling of program execution.

· Fill, dump, and graphically plot the contents of memory.

· Perform source level debugging.

· Create custom debugger windows.

The VisualDSP++ IDDE lets programmers define and manage
software development. Its dialog boxes and property pages let
programmers configure and manage all of the Blackfin develop-
ment tools, including the color syntax highlighting in the
VisualDSP++ editor. This capability permits programmers to:

· Control how the development tools process inputs and

generate outputs.

· Maintain a one-to-one correspondence with the tool's

command line switches.

The VisualDSP++ Kernel (VDK) incorporates scheduling and
resource management tailored specifically to address the mem-
ory and timing constraints of DSP programming. These
capabilities enable engineers to develop code more effectively,
eliminating the need to start from the very beginning, when
developing new application code. The VDK features include
threads, critical and unscheduled regions, semaphores, events,
and device flags. The VDK also supports priority-based, pre-
emptive, cooperative, and time-sliced scheduling approaches. In
addition, the VDK was designed to be scalable. If the application
does not use a specific feature, the support code for that feature
is excluded from the target system.

Because the VDK is a library, a developer can decide whether to
use it or not. The VDK is integrated into the VisualDSP++
development environment, but can also be used via standard
command line tools. When the VDK is used, the development
environment assists the developer with many error prone tasks
and assists in managing system resources, automating the gen-
eration of various VDK based objects, and visualizing the
system state, when debugging an application that uses the VDK.

Use the Expert Linker to visually manipulate the placement of
code and data on the embedded system. View memory utiliza-
tion in a color coded graphical form, easily move code and data
to different areas of the processor or external memory with the
drag of the mouse, examine run time stack and heap usage. The
Expert Linker is fully compatible with existing Linker Definition
File (LDF), allowing the developer to move between the graphi-
cal and textual environments.

Analog Devices emulators use the IEEE 1149.1 JTAG Test
Access Port of the ADSP-BF538/ADSP-BF538F processors to
monitor and control the target board processor during emula-
tion. The emulator provides full speed emulation, allowing

ADSP-BF538/ADSP-BF538F

Preliminary Technical Data

Rev. PrD

Page 17 of 56

May 2006

inspection and modification of memory, registers, and proces-
sor stacks. Non intrusive in-circuit emulation is assured by the
use of the processor's JTAG interface--the emulator does not
affect target system loading or timing.

In addition to the software and hardware development tools
available from Analog Devices, third parties provide a wide
range of tools supporting the Blackfin processor family. Hard-
ware tools include Blackfin processor PC plug-in cards. Third
party software tools include DSP libraries, real time operating
systems, and block diagram design tools.

Evaluation Kit

Analog Devices offers a range of EZ-KIT Lite

evaluation plat-

forms to use as a cost effective method to learn more about
developing or prototyping applications with Analog Devices
processors, platforms, and software tools. Each EZ-KIT Lite
includes an evaluation board along with an evaluation suite of
the VisualDSP++ development and debugging environment
with the C/C++ compiler, assembler, and linker. Also included
are sample application programs, power supply, and a USB
cable. All evaluation versions of the software tools are limited
for use only with the EZ-KIT Lite product.

The USB controller on the EZ-KIT Lite board connects the
board to the USB port of the user's PC, enabling the
VisualDSP++ evaluation suite to emulate the on-board proces-
sor in-circuit. This permits the customer to download, execute,
and debug programs for the EZ-KIT Lite system. It also allows
in-circuit programming of the on-board flash device to store
user-specific boot code, enabling the board to run as a standal-
one unit without being connected to the PC.

With a full version of VisualDSP++ installed (sold separately),
engineers can develop software for the EZ-KIT Lite or any cus-
tom defined system. Connecting one of Analog Devices JTAG
emulators to the EZ-KIT Lite board enables high-speed, non-
intrusive emulation.

DESIGNING AN EMULATOR COMPATIBLE
PROCESSOR BOARD

The Analog Devices family of emulators are tools that every sys-
tem developer needs to test and debug hardware and software
systems. Analog Devices has supplied an IEEE 1149.1 JTAG
Test Access Port (TAP) on each JTAG processor. The emulator
uses the TAP to access the internal features of the processor,
allowing the developer to load code, set breakpoints, observe
variables, observe memory, and examine registers. The proces-
sor must be halted to send data and commands, but once an
operation has been completed by the emulator, the processor
system is set running at full speed with no impact on system
timing.

To use these emulators, the target board must include a header
that connects the processor's JTAG port to the emulator.

For details on target board design issues including mechanical
layout, single processor connections, multiprocessor scan
chains, signal buffering, signal termination, and emulator pod
logic, see EE-68: Analog Devices JTAG Emulation Technical Ref-

erence on the Analog Devices web site (

www.analog.com

)--use

site search on "EE-68." This document is updated regularly to
keep pace with improvements to emulator support.

VOLTAGE REGULATOR LAYOUT GUIDELINES

Regulator external component placement, board routing, and
bypass capacitors all have a significant effect on noise injected
into the other analog circuits on-chip. The VROUT1-0 traces
and voltage regulator external components should be consid-
ered as noise sources when doing board layout and should not
be routed or placed near sensitive circuits or components on the
board. All internal and I/O power supplies should be well
bypassed with bypass capacitors placed as close to the ADSP-
BF538/ADSP-BF538F processors as possible.

For further details on the on-chip voltage regulator and related
board design guidelines, see the EE-228: Switching Regulator
Design Considerations for ADSP-BF533 Blackfin Processors
applications note on the Analog Devices web site (

www.ana-

log.com

)--use site search on "EE-228.".

Rev. PrD

Page 18 of 56

May 2006

ADSP-BF538/ADSP-BF538F

Preliminary Technical Data

PIN DESCRIPTIONS

ADSP-BF538/ADSP-BF538F processor pin definitions are listed
in

Table 10

. In order to maintain maximum functionality and

reduce package size and pin count, some pins have dual, multi-

plexed functionality. In cases where pin functionality is
reconfigurable, the default state is shown in plain text, while
alternate functionality is shown in italics.

Table 10. Pin Descriptions

Pin Name

I/O

Function

Driver Type

Memory Interface

ADDR191

Address Bus for Async/Sync Access

DATA150

I/O

Data Bus for Async/Sync Access

ABE10/SDQM10

Byte Enables/Data Masks for Async/Sync Access

Bus Request (This pin should be pulled HIGH when not used.)

Bus Grant

BGH

Bus Grant Hang

Asynchronous Memory Control

AMS30

Bank Select

ARDY

Hardware Ready Control (This pin should always be pulled LOW when not used.)

AOE

Output Enable

ARE

Read Enable

AWE

Write Enable

Flash Control

FCE

Flash Enable (This pin should be left unconnected if not used.)

FRESET

Flash Reset (This pin should be left unconnected if not used.)

Synchronous Memory Control

SRAS

Row Address Strobe

SCAS

Column Address Strobe

SWE

Write Enable

SCKE

Clock Enable

CLKOUT

Clock Output

SA10

A10 Pin

SMS

Bank Select

Timers

TMR0

I/O

Timer 0

TMR1/PPI_FS1

I/O

Timer 1/PPI Frame Sync1

TMR2/PPI_FS2

I/O

Timer 2/PPI Frame Sync2

Two Wire Interface Port (These pins are open drain and require a pullup resistor. See version 2.1 of the I

C specification for

proper resistor values.)

SDA0

I/O 5V

TWI0 Serial Data

SCL0

I/O 5V

TWI0 Serial Clock

SDA1

I/O 5V

TWI1 Serial Data

SCL1

I/O 5V

TWI1 Serial Clock

ADSP-BF538/ADSP-BF538F

Preliminary Technical Data

Rev. PrD

Page 19 of 56

May 2006

Serial Port0

RSCLK0

I/O

SPORT0 Receive Serial Clock

RFS0

I/O

SPORT0 Receive Frame Sync

DR0PRI

SPORT0 Receive Data Primary

DR0SEC

SPORT0 Receive Data Secondary

TSCLK0

I/O

SPORT0 Transmit Serial Clock

TFS0

I/O

SPORT0 Transmit Frame Sync

DT0PRI

SPORT0 Transmit Data Primary

DT0SEC

SPORT0 Transmit Data Secondary

Serial Port1

RSCLK1

I/O

SPORT1 Receive Serial Clock

RFS1

I/O

SPORT1 Receive Frame Sync

DR1PRI

SPORT1 Receive Data Primary

DR1SEC

SPORT1 Receive Data Secondary

TSCLK1

I/O

SPORT1 Transmit Serial Clock

TFS1

I/O

SPORT1 Transmit Frame Sync

DT1PRI

SPORT1 Transmit Data Primary

DT1SEC

SPORT1 Transmit Data Secondary

SPI0 Port

MOSI0

I/O

SPI0 Master Out Slave In

MISO0

I/O

SPI0 Master In Slave Out (This pin should always be pulled HIGH through a 4.7
K

resistor if booting via the SPI port.)

SCK0

I/O

SPI0 Clock

UART0 Port

RX0

UART Receive

TX0

UART Transmit

PPI Port

PPI30

I/O

PPI30

PPI_CLK

PPI Clock

Port C: Controller Area Network/GPIO

CANTX/PC0

I/O 5V

CAN Transmit/GPIO

CANRX/PC1

I/O 5V

CAN Receive/GPIO

PC[9:4]

I/O

GPIO

Port D: SPI1/SPI2/UART1/UART2/GPIO

MOSI1/PD0

I/O

SPI1 Master Out Slave In/GPIO

MISO1/PD1

I/O

SPI1 Master In Slave Out/GPIO

SCK1/PD2

I/O

SPI1 Clock/GPIO

SPI1SS/PD3

I/O

SPI1 Slave Select Input/GPIO

SPI1SEL/PD4

I/O

SPI1 Slave Select Enable/GPIO

MOSI2/PD5

I/O

SPI2 Master Out Slave In/GPIO

MISO2/PD6

I/O

SPI2 Master In Slave Out/GPIO

Table 10. Pin Descriptions (Continued)

Pin Name

I/O

Function

Driver Type

Rev. PrD

Page 20 of 56

May 2006

ADSP-BF538/ADSP-BF538F

Preliminary Technical Data

SCK2/PD7

I/O

SPI2 Clock/GPIO

SPI2SS/PD8

I/O

SPI2 Slave Select Input/GPIO

SPI2SEL/PD9

I/O

SPI2 Slave Select Enable/GPIO

RX1/PD10

I/O

UART1 Receive/GPIO

TX1/PD11

I/O

UART1 Transmit/GPIO

RX2/PD12

I/O

UART2 Receive/GPIO

TX2/PD13

I/O

UART2 Transmit/GPIO

Port E: SPORT2/SPORT3/GPIO

RSCLK2/PE0

I/O

SPORT2 Receive Serial Clock/GPIO

RFS2/PE1

I/O

SPORT2 Receive Frame Sync/GPIO

DR2PRI /PE2

I/O

SPORT2 Receive Data Primary/GPIO

DR2SEC/PE3

I/O

SPORT2 Receive Data Secondary/GPIO

TSCLK2/PE4

I/O

SPORT2 Transmit Serial Clock/GPIO

TFS2/PE5

I/O

SPORT2 Transmit Frame Sync/GPIO

DT2PRI/PE6

I/O

SPORT2 Transmit Data Primary/GPIO

DT2SEC/PE7

I/O

SPORT2 Transmit Data Secondary/GPIO

RSCLK3/PE8

I/O

SPORT3 Receive Serial Clock/GPIO

RFS3/PE9

I/O

SPORT3 Receive Frame Sync/GPIO

DR3PRI/PE10

I/O

SPORT3 Receive Data Primary/GPIO

DR3SEC/PE11

I/O

SPORT3 Receive Data Secondary/GPIO

TSCLK3/PE12

I/O

SPORT3 Transmit Serial Clock/GPIO

TFS3/PE13

I/O

SPORT3 Transmit Frame Sync/GPIO

DT3PRI/PE14

I/O

SPORT3 Transmit Data Primary/GPIO

DT3SEC/PE15

I/O

SPORT3 Transmit Data Secondary/GPIO

Port F: Parallel Peripheral Interface Port/SPI0/Timers/GPIO

SPI0SS/PF0

I/O

SPI Slave Select Input/GPIO

SPI0SEL1/TMRCLK/PF1

I/O

SPI Slave Select Enable 1/External Timer Reference/GPIO

SPI0SEL2/PF2

I/O

SPI Slave Select Enable 2/GPIO

PPI_FS3/SPI0SEL3/PF3

I/O

PPI Frame Sync 3/SPI Slave Select Enable 3/GPIO

PPI15/SPI0SEL4/PF4

I/O

PPI 15/SPI Slave Select Enable 4/GPIO

PPI14/SPI0SEL5/PF5

I/O

PPI 14/SPI Slave Select Enable 5/GPIO

PPI13/SPI0SEL6/PF6

I/O

PPI 13/SPI Slave Select Enable 6/GPIO

PPI12/SPI0SEL7/PF7

I/O

PPI 12/SPI Slave Select Enable 7/GPIO

PPI11/PF8

I/O

PPI 11/GPIO

PPI10/PF9

I/O

PPI 10/GPIO

PPI9/PF10

I/O

PPI 9/GPIO

PPI8/PF11

I/O

PPI 8/GPIO

PPI7/PF12

I/O

PPI 7/GPIO

PPI6/PF13

I/O

PPI 6/GPIO

PPI5/PF14

I/O

PPI 5/GPIO

PPI4/PF15

I/O

PPI 4/GPIO

Table 10. Pin Descriptions (Continued)

Pin Name

I/O

Function

Driver Type

Rev. PrD

Page 22 of 56

May 2006

ADSP-BF538/ADSP-BF538F

Preliminary Technical Data

SPECIFICATIONS

Note that component specifications are subject to change
without notice.

OPERATING CONDITIONS

OPERATING CONDITIONS--APPLIES TO 5V TOLERANT PINS

ELECTRICAL CHARACTERISTICS

Parameter

Specifications subject to change without notice.

Min

Nominal

Max

Unit

DDINT

Internal Supply Voltage

0.8

1.2

1.32

DDEXT

External Supply Voltage

2.25

3.3

3.6

DDRTC

Real Time Clock Power Supply Voltage

2.25

3.6

High Level Input Voltage

, @ V

DDEXT

=maximum

The 3.3 V tolerant pins are capable of accepting up to 3.6 V maximum V

The following bi-directional pins are 3.3 V tolerant: DATA150, MISO0, MOSI0, PF150, PPI30,

SCK1, MISO1, MOSI1, SPI1SS, SPI1SEL, SCK2, MISO2, MOSI2, SPI2SS, SPI2SEL, RX1, TX1, RX2, TX2, DT2PRI, DT2SEC, TSCLK2, DR2PRI, DT2SEC, RSCLK2, RFS2,
TFS2, DT3PRI, DT3SEC, DR3PRI, DR3SEC, RSCLK3, RFS3, TFS3, RFS0, RFS1, RSCLK0, RSCLK1, TSCLK0, TSCLK1, SCK0, TFS0, TFS1, and TMR20. The following
input-only pins are 3.3 V tolerant: RESET, RX0, TCK, TDI, TMS, TRST, ARDY, BMODE10, BR, DR0PRI, DR0SEC, DR1PRI, DR1SEC, NMI, PPI_CLK, RTXI, and GP.

2.0

3.6

IHCLKIN

High Level Input Voltage

, @ V

DDEXT

=maximum

Parameter value applies to the CLKIN pins.

2.2

3.6

Low Level Input Voltage

2, 4

, @ V

DDEXT

=minimum

Parameter value applies to all input and bi-directional pins.

0.3

0.6

Parameter

Specifications subject to change without notice.

Min

Nominal

Max

Unit

The 5.V tolerant pins are capable of accepting up to 5.5 V maximum V

. The following bi-directional pins are 5 V tolerant: SCL0, SCL1, SDA0, SDA1, CANRX, CANTX.

High Level Input Voltage, @ V

DDEXT

=maximum

2.0

5.5

Low Level Input Voltage, @ V

DDEXT

=minimum

0.3

0.8

Parameter

Specifications subject to change without notice.

Test Conditions

Min

Max

Unit

High Level Output Voltage

Applies to output and bidirectional pins.

@ V

DDEXT

=3.0V, I

= 0.5 mA

2.4

Low Level Output Voltage

@ V

DDEXT

=3.0V, I

= 2.0 mA

0.4

High Level Input Current

Applies to input pins.

@ V

DDEXT

=maximum, V

= V

maximum

TBD

Low Level Input Current

Applies to three-statable pins.

@ V

DDEXT

=maximum, V

= 0 V

TBD

OZH

Three-State Leakage Current

@ V

DDEXT

= maximum, V

= V

maximum

OZL

Three-State Leakage Current

Applies to all signal pins.

@ V

DDEXT

= maximum, V

= 0 V

Input Capacitance

5, 6

Guaranteed, but not tested.

= 1 MHz, T

MBIENT

= 25°C, V

= 2.5 V

TBD

ADSP-BF538/ADSP-BF538F

Preliminary Technical Data

Rev. PrD

Page 23 of 56

May 2006

ABSOLUTE MAXIMUM RATINGS

Stresses greater than those listed below may cause permanent
damage to the device. These are stress ratings only. Functional
operation of the device at these or any other conditions greater
than those indicated in the operational sections of this specifica-
tion is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

PACKAGE INFORMATION

The information presented in

Figure 9

and

Table 12

provides

information about how to read the package brand and relate it
to specific product features. For a complete listing of product
offerings, see the

Ordering Guide on Page 55

ESD SENSITIVITY

Parameter

Rating

Internal (Core) Supply Voltage (V

DDINT

)

0.3 V to +1.4 V

External (I/O) Supply Voltage (V

DDEXT

)

0.3 V to +3.8 V

Input Voltage

0.5 V to +3.6 V

Input Voltage

The 5.V tolerant pins are capable of accepting up to 5.5 V maximum V

. The

following bi-directional pins are 5 V tolerant: SCL0, SCL1, SDA0, SDA1,
CANRX, CANTX. For other duty cycles, see

Table 11

0.5 V to +5.5 V

Output Voltage Swing

0.5 V to V

DDEXT

+0.5 V

Load Capacitance

200 pF

Storage Temperature Range

°C to +150°C

Junction Temperature Under bias

+125

°C

Table 11. Maximum Duty Cycle for Input

Transient Voltage

Applies to all signal pins with the exception of CLKIN, XTAL, and VROUT10.

Max (V)

Only one of the listed options can apply to a particular design.

Min (V)

Maximum Duty Cycle

3.63

0.33

100%

3.80

0.50

48%

3.90

0.60

30%

4.00

0.70

20%

4.10

0.80

10%

4.20

0.90

4.30

1.00

Figure 9. Product Information on Package

Table 12. Package Brand Information

Brand Key

Field Description

t Temperature

Range

Package Type

Lead Free Option (optional)

ccc

See Ordering Guide

vvvvvv.x Assembly

Lot

Code

n.n

Silicon Revision

yyww

Date Code

vvvvvv.x n.n

tppZccc

ADSP-BF5xx

yyww country_of_origin

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADSP-BF538/ADSP-BF538F processors feature proprietary ESD protection circuitry, permanent
damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper
ESD precautions are recommended to avoid performance degradation or loss of functionality.

Rev. PrD

Page 24 of 56

May 2006

ADSP-BF538/ADSP-BF538F

Preliminary Technical Data

TIMING SPECIFICATIONS

Table 13

describes the timing requirements for the ADSP-

BF538/ADSP-BF538F processor clocks. Take care in selecting
MSEL, SSEL, and CSEL ratios so as not to exceed the maximum
core clock, system clock and Voltage Controlled Oscillator

(VCO) operating frequencies, as described in

Absolute Maxi-

mum Ratings on Page 23

Table 14

describes Phase Locked

Loop operating conditions.

Clock and Reset Timing

Table 15

and

Figure 10

describe clock and reset operations. Per

Absolute Maximum Ratings on Page 23

, combinations of

CLKIN and clock multipliers must not select core/peripheral
clocks in excess of 500/133 MHz.

Table 13. Core and System Clock Requirements--ADSP-BF538/ADSP-BF538F--500 MHz

Parameter

Min

Max

Unit

CCLK

Core Clock Frequency (V

DDINT

= 1.2 V minimum)

500

MHz

CCLK

Core Clock Frequency (V

DDINT

= 1.045 V minimum)

444

MHz

CCLK

Core Clock Frequency (V

DDINT

= 0.95 V minimum)

400

MHz

CCLK

Core Clock Frequency (V

DDINT

= 0.85 V minimum)

333

MHz

Table 14. Phase Locked Loop Operating Conditions

Parameter

Min

Max

Unit

VCO

Voltage Controlled Oscillator (VCO) Frequency

Max CCLK

MHz

Table 15. Clock and Reset Timing

Parameter

Min

Max

Unit

Timing Requirements

CKIN

CLKIN Period

20.0

100.0

CKINL

CLKIN Low Pulse

8.0

CKINH

CLKIN High Pulse

8.0

WRST

RESET Asserted Pulsewidth Low

11 t

CKIN

Applies to bypass mode and non-bypass mode.

Applies after power-up sequence is complete. At power-up, the processor's internal phase locked loop requires no more than 2000 CLKIN cycles, while RESET is asserted,

assuming stable power supplies and CLKIN (not including startup time of external clock oscillator).

Figure 10. Clock and Reset Timing

RESET

CLKIN

CKINH

CKIN

CKINL

WRST

ADSP-BF538/ADSP-BF538F

Preliminary Technical Data

Rev. PrD

Page 25 of 56

May 2006

Asynchronous Memory Read Cycle Timing

Table 16

and

Table 17 on Page 26

and

Figure 11

and

Figure 12

on Page 26

describe asynchronous memory read cycle opera-

tions for synchronous and for asynchronous ARDY.

Table 16. Asynchronous Memory Read Cycle Timing with Synchronous ARDY

Parameter

Min

Max

Unit

Timing Requirements

SDAT

DATA15 0 Setup Before CLKOUT

2.1

HDAT

DATA15 0 Hold After CLKOUT

0.8

SARDY

ARDY Setup Before the Falling Edge of CLKOUT

TBD

HARDY

ARDY Hold After the Falling Edge of CLKOUT

TBD

Output Delay After CLKOUT

6.0

Output Hold After CLKOUT

0.8

Output pins include AMS30, ABE10, ADDR191, AOE, ARE.

Figure 11. Asynchronous Memory Read Cycle Timing with Synchronous ARDY

SDAT

CLKOUT

AMSx

ABE10

BE, ADDRESS

READ

HDAT

DATA150

AOE

SARDY

HARDY

ACCESS EXTENDED

3 CYCLES

HOLD

1 CYCLE

ARE

HARDY

ARDY

ADDR191

SETUP

2 CYCLES

PROGRAMMED READ ACCESS

4 CYCLES

SARDY

ADSP-BF538/ADSP-BF538F

Preliminary Technical Data

Rev. PrD

Page 27 of 56

May 2006

Asynchronous Memory Write Cycle Timing

Table 18

and

Table 19 on Page 28

and

Figure 13

and

Figure 14

on Page 28

describe asynchronous memory write cycle opera-

tions for synchronous and for asynchronous ARDY.

Table 18. Asynchronous Memory Write Cycle Timing with Synchronous ARDY

Parameter

Min

Max

Unit

Timing Requirements

SARDY

ARDY Setup Before the Falling Edge of CLKOUT

TBD

HARDY

ARDY Hold After the Falling Edge of CLKOUT

TBD

Switching Characteristics

DDAT

DATA15 0 Disable After CLKOUT

6.0

ENDAT

DATA15 0 Enable After CLKOUT

1.0

Output Delay After CLKOUT

6.0

Output Hold After CLKOUT

0.8

Output pins include AMS30, ABE10, ADDR191, DATA150, AOE, AWE.

Figure 13. Asynchronous Memory Write Cycle Timing with Synchronous ARDY

ENDAT

CLKOUT

AMSx

ABE10

BE, ADDRESS

WRITE DATA

DDAT

DATA150

AWE

SARDY

HARDY

SETUP

2 CYCLES

PROGRAMMED WRITE

ACCESS 2 CYCLES

ACCESS

EXTENDED

1 CYCLE

HOLD

1 CYCLE

ARDY

ADDR191

HARD Y

SARDY

Rev. PrD

Page 30 of 56

May 2006

ADSP-BF538/ADSP-BF538F

Preliminary Technical Data

External Port Bus Request and Grant Cycle Timing

Table 21

and

Table 22 on Page 31

and

Figure 16

and

Figure 17

on Page 31

describe external port bus request and grant cycle

operations for synchronous and for asynchronous BR.

Table 21. External Port Bus Request and Grant Cycle Timing with Synchronous BR

Parameter

Min

Max

Unit

Timing Requirements

BR Setup to Falling Edge of CLKOUT

TBD

Falling Edge of CLKOUT to BR Deasserted Hold Time

TBD

Switching Characteristics

CLKOUT Low to xMS, Address, and RD/WR disable

4.5

CLKOUT Low to xMS, Address, and RD/WR enable

4.5

DBG

CLKOUT High to BG High Setup

3.6

EBG

CLKOUT High to BG Deasserted Hold Time

3.6

DBH

CLKOUT High to BGH High Setup

3.6

EBH

CLKOUT High to BGH Deasserted Hold Time

3.6

Figure 16. External Port Bus Request and Grant Cycle Timing with Synchronous BR

ADDR19-1

AMSx

CLKOUT

AWE

BGH

ARE

ABE1-0

EBG

DBG

EBH

DBH

Rev. PrD

Page 32 of 56

May 2006

ADSP-BF538/ADSP-BF538F

Preliminary Technical Data

Parallel Peripheral Interface Timing

Table 23

and

Figure 18

Figure 19

Figure 20

, and

Figure 21

describe Parallel Peripheral Interface operations.

Table 23. Parallel Peripheral Interface Timing

Parameter

Min

Max

Unit

Timing Requirements

PCLKW

PPI_CLK Width

6.0

PCLK

PPI_CLK Period

15.0

SFSPE

External Frame Sync Setup Before PPI_CLK

3.0

HFSPE

External Frame Sync Hold After PPI_CLK

3.0

SDRPE

Receive Data Setup Before PPI_CLK

2.0

HDRPE

Receive Data Hold After PPI_CLK

4.0

Switching Characteristics -- GP Output and Frame Capture Modes

DFSPE

Internal Frame Sync Delay After PPI_CLK

10.0

HOFSPE

Internal Frame Sync Hold After PPI_CLK

0.0

DDTPE

Transmit Data Delay After PPI_CLK

10.0

HDTPE

Transmit Data Hold After PPI_CLK

0.0

PPI_CLK frequency cannot exceed f

SCLK

Figure 18. PPI GP Rx Mode with Internal Frame Sync Timing

SDRPE

HDRPE

POLS = 0

POLC = 0

POLS = 1

FRAME
SYNC IS
DRIVEN
OUT

DATA0
IS
SAMPLED

POLC = 1

DFSPE

HOFSPE

PPI_CLK

PPI_FS1

PPI_FS2

PPI_DATA

ADSP-BF538/ADSP-BF538F

Preliminary Technical Data

Rev. PrD

Page 35 of 56

May 2006

Serial Port Timing

Table 24

through

Table 27 on Page 36

and

Figure 22 on Page 36

through

Figure 24 on Page 38

describe Serial Port operations.

Table 24. Serial Ports--External Clock

Parameter

Min

Max

Unit

Timing Requirements

SFSE

TFS/RFS Setup Before TSCLK/RSCLK (externally generated TFS/RFS)

3.0

HFSE

TFS/RFS Hold After TSCLK/RSCLK (externally generated TFS/RFS)

3.0

SDRE

Receive Data Setup Before RSCLK

3.0

HDRE

Receive Data Hold After RSCLK

3.0

SCLKEW

TSCLK/RSCLK Width

4.5

SCLKE

TSCLK/RSCLK Period

15.0

Switching Characteristics

DFSE

TFS/RFS Delay After TSCLK/RSCLK (Internally Generated TFS/RFS)

10.0

HOFSE

TFS/RFS Hold After TSCLK/RSCLK (Internally Generated TFS/RFS)

0.0

DDTE

Transmit Data Delay After TSCLK

10.0

HDTE

Transmit Data Hold After TSCLK

0.0

Referenced to sample edge.

Referenced to drive edge.

Table 25. Serial Ports--Internal Clock

Parameter

Min

Max

Unit

Timing Requirements

SFSI

TFS/RFS Setup Before TSCLK/RSCLK (externally generated TFS/RFS)

8.0

HFSI

TFS/RFS Hold After TSCLK/RSCLK (externally generated TFS/RFS)

2.0

SDRI

Receive Data Setup Before RSCLK

6.0

HDRI

Receive Data Hold After RSCLK

0.0

SCLKEW

TSCLK/RSCLK Width

4.5

SCLKE

TSCLK/RSCLK Period

15.0

Switching Characteristics

DFSI

TFS/RFS Delay After TSCLK/RSCLK (Internally Generated TFS/RFS)

3.0

HOFSI

TFS/RFS Hold After TSCLK/RSCLK (Internally Generated TFS/RFS)

1.0

DDTI

Transmit Data Delay After TSCLK

3.0

HDTI

Transmit Data Hold After TSCLK

2.0

SCLKIW

TSCLK/RSCLK Width

4.5

Referenced to sample edge.

Referenced to drive edge.

Table 26. Serial Ports--Enable and Three-State

Parameter

Min

Max

Unit

Switching Characteristics

DTENE

Data Enable Delay from External TSCLK

DDTTE

Data Disable Delay from External TSCLK

10.0

DTENI

Data Enable Delay from Internal TSCLK

2.0

DDTTI

Data Disable Delay from Internal TSCLK

3.0

Referenced to drive edge.

Rev. PrD

Page 36 of 56

May 2006

ADSP-BF538/ADSP-BF538F

Preliminary Technical Data

Table 27. External Late Frame Sync

Parameter

Min

Max

Unit

Switching Characteristics

DDTLFSE

Data Delay from Late External TFS or External RFS with MCE = 1, MFD = 0

1, 2

10.0

DTENLFS

Data Enable from late FS or MCE = 1, MFD = 0

1, 2

MCE = 1, TFS enable and TFS valid follow t

DTENLFS

and t

DDTLFSE

If external RFS/TFS setup to RSCLK/TSCLK > t

SCLKE

/2, then t

DDTE/I

and t

DTENE/I

apply; otherwise t

DDTLFSE

and t

DTENLFS

apply.

Figure 22. Serial Ports

DDTTE

DTENE

DDTTI

DTENI

DRIVE

EDGE

DRIVE

EDGE

DRIVE

EDGE

DRIVE

EDGE

TSCLK / RSCLK

TSCLK (EXT)

TFS ("LATE", EXT.)

TSCLK (INT)

TFS ("LATE", INT.)

SDRI

RSCLK

RFS

DRIVE

EDGE

SAMPLE

EDGE

HDRI

SFSI

HFSI

DFSE

HOFSE

SCLKIW

DATA RECEIVE- INTERNAL CLOCK

SDRE

DATA RECEIVE- EXTERNAL CLOCK

RSCLK

RFS

DRIVE

EDGE

SAMPLE

EDGE

HDRE

SFSE

HFSE

DFSE

SCLKEW

HOFSE

NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK OR TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.

DDTI

HDTI

TSCLK

TFS

DRIVE

EDGE

SAMPLE

EDGE

SFSI

HFSI

SCLKIW

DFSI

HOFSI

DATA TRANSMIT- INTERNAL CLOCK

DDTE

HDTE

TSCLK

TFS

DRIVE

EDGE

SAMPLE

EDGE

SFSE

HFSE

DFSE

SCLKEW

HOFSE

DATA TRANSMIT- EXTERNAL CLOCK

NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK OR TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.

ADSP-BF538/ADSP-BF538F

Preliminary Technical Data

Rev. PrD

Page 39 of 56

May 2006

Serial Peripheral Interface Port--Master Timing

Table 28

and

Figure 25

describe SPI port master operations.

Table 28. Serial Peripheral Interface (SPI) Port--Master Timing

Parameter

Min

Max

Unit

Timing Requirements

SSPIDM

Data Input Valid to SCK Edge (Data Input Setup)

7.5

HSPIDM

SCK Sampling Edge to Data Input Invalid

1.5

Switching Characteristics

SDSCIM

SPI0SELx Low to First SCK edge (x= 0 or 1)

SCLK

1.5

SPICHM

Serial Clock High period

SCLK

1.5

SPICLM

Serial Clock Low period

SCLK

1.5

SPICLK

Serial Clock Period

SCLK

1.5

HDSM

Last SCK Edge to SPI0SELx High (x=0 or 1)

SCLK

1.5

SPITDM

Sequential Transfer Delay

SCLK

1.5

DDSPIDM

SCK Edge to Data Out Valid (Data Out Delay)

HDSPIDM

SCK Edge to Data Out Invalid (Data Out Hold)

1.0

4.0

Figure 25. Serial Peripheral Interface (SPI) Port--Master Timing

SSPIDM

HSPIDM

HDSPIDM

LSB

MSB

HSPIDM

DDSPIDM

MOSI

(OUTPUT)

MISO

(INPUT)

SPISELx

(OUTPUT)

SCK

(CPOL = 0)

(OUTPUT)

SCK

(CPOL = 1)

(OUTPUT)

SPICHM

SPICLM

SPICLK

SPICHM

HDSM

SPITDM

HDSPIDM

LSB VALID

LSB

MSB

MSB VALID

HSPIDM

DDSPIDM

MOSI

(OUTPUT)

MISO

(INPUT)

SSPIDM

CPHA=1

CPHA=0

MSB VALID

SDSCIM

SSPIDM

LSB VALID

Rev. PrD

Page 40 of 56

May 2006

ADSP-BF538/ADSP-BF538F

Preliminary Technical Data

Serial Peripheral Interface Port--Slave Timing

Table 29

and

Figure 26

describe SPI port slave operations.

Table 29. Serial Peripheral Interface (SPI) Port--Slave Timing

Parameter

Min

Max

Unit

Timing Requirements

SPICHS

Serial Clock High Period

SCLK

1.5

SPICLS

Serial Clock low Period

SCLK

1.5

SPICLK

Serial Clock Period

SCLK

1.5

HDS

Last SCK Edge to SPI0SS Not Asserted

SCLK

1.5

SPITDS

Sequential Transfer Delay

SCLK

1.5

SDSCI

SPI0SS Assertion to First SCK Edge

SCLK

1.5

SSPID

Data Input Valid to SCK Edge (Data Input Setup)

1.6

HSPID

SCK Sampling Edge to Data Input Invalid

1.6

Switching Characteristics

DSOE

SPI0SS Assertion to Data Out Active

DSDHI

SPI0SS Deassertion to Data High impedance

DDSPID

SCK Edge to Data Out Valid (Data Out Delay)

HDSPID

SCK Edge to Data Out Invalid (Data Out Hold)

Figure 26. Serial Peripheral Interface (SPI) Port--Slave Timing

HSPID

DDSPID

DSDHI

LSB

MSB

MSB VALID

HSPID

DSOE

DDSPID

HDSPID

MISO

(OUTPUT)

MOSI

(INPUT)

SSPID

SPISS

(INPUT)

SCK

(CPOL = 0)

(INPUT)

SCK

(CPOL = 1)

(INPUT)

SDSCI

SPICHS

SPICLS

SPICLK

HDS

SPICHS

SSPID

HSPID

DSDHI

LSB VALID

MSB

MSB VALID

DSOE

DDSPID

MISO

(OUTPUT)

MOSI

(INPUT)

SSPID

LSB VALID

LSB

CPHA=1

CPHA=0

SPITDS

ADSP-BF538/ADSP-BF538F

Preliminary Technical Data

Rev. PrD

Page 43 of 56

May 2006

JTAG Test And Emulation Port Timing

Table 32

and

Figure 29

describe JTAG port operations.

Table 32. JTAG Port Timing

Parameter

Min

Max

Unit

Timing Requirements

TCK

TCK Period

STAP

TDI, TMS Setup Before TCK High

HTAP

TDI, TMS Hold After TCK High

SSYS

System Inputs Setup Before TCK High

HSYS

System Inputs Hold After TCK High

TRSTW

TRST Pulsewidth

(measured in TCK cycles)

TCK

Switching Characteristics

DTDO

TDO Delay from TCK Low

DSYS

System Outputs Delay After TCK Low

System Inputs=ARDY, BMODE10, BR, DATA150.DR0PRI, DR0SEC, DR1PRI, DR1SEC, MISO0, MOSI0, NMI, PF150, PPI_CLK, PPI30.SCL0, SCL1, SDA0, SDA1,

SCK, SCK1, MISO1, MOSI1, SPI1SS, SPI1SEL, SCK2, MISO2, MOSI2, SPI2SS, SPI2SEL, RX1, TX1, RX2, TX2, DT2PRI, DT2SEC, TSCLK2, DR2PRI, DT2SEC, RSCLK2,
RFS2, TFS2, DT3PRI, DT3SEC, DR3PRI, DR3SEC, RSCLK3, RFS3, TFS3, CANTX, CANRX, RESET, RFS0, RFS1, RSCLK0, RSCLK1, TSCLK0, TSCLK1, RX0,.SCK0, TFS0,
TFS1, and TMR20,

50 MHz Maximum

System Outputs = AMS, AOE, ARE, AWE, ABE, BG, DATA150, DT0PRI, DT0SEC, DT1PRI, DT1SEC, MISO0, MOSI0, PF150, PPI30, SCK1, MISO1, MOSI1, SPI1SS,

SPI1SEL, SCK2, MISO2, MOSI2, SPI2SS, SPI2SEL, RX1, TX1, RX2, TX2, DT2PRI, DT2SEC, TSCLK2, DR2PRI, DR2SEC, RSCLK2, RFS2, TFS2, DT3PRI, DT3SEC, TSCLK3,
DR3PRI, DR3SEC, RSCLK3, RFS3, TFS3, CANTX, CANRX, RFS0, RFS1, RSCLK0, RSCLK1, TSCLK0, TSCLK1, CLKOUT, TX0, SA10, SCAS, SCK0, SCKE, SMS, SRAS,
SWE, and TMR20.

Figure 29. JTAG Port Timing

TMS

TDI

TDO

SYSTEM

INPUTS

SYSTEM

OUTPUTS

TCK

HTAP

STAP

DTDO

SSYS

HSYS

DSYS

Rev. PrD

Page 44 of 56

May 2006

ADSP-BF538/ADSP-BF538F

Preliminary Technical Data

OUTPUT DRIVE CURRENTS

Figure 30

through

Figure 37 on Page 45

shows typical current-

voltage characteristics for the output drivers of the ADSP-
BF538/ADSP-BF538F processors. The curves represent the cur-
rent drive capability of the output drivers as a function of output
voltage.

Figure 30. Drive Current A (Low V

DDEXT

)

Figure 31. Drive Current A (High V

DDEXT

)

(
m

)

SOURCE VOL TAGE (V)

0.5

1.0

1.5

2.0

2.5

3. 0

100

120

100

D DE XT

= 2.25V @ 95°C

D DE XT

= 2.50V @ 25°C

D DE XT

= 2.75V @ -40°C

(
m

)

SOURCE VOLTAGE (V)

0.5

1.0

1.5

2.0

2.5

3. 0

3.5

150

100

150

100

O H

4.0

D D EX T

= 3.0V @ 95°C

D D EX T

= 3.3V @ 25°C

D D EX T

= 3.6V @ -40°C

Figure 32. Drive Current B (Low V

DDEXT

)

Figure 33. Drive Current B (High V

DDEXT

)

(
m

)

SOURCE VOLTAGE (V)

0.5

1. 0

1.5

2.0

2.5

3.0

150

100

150

100

D D EX T

= 2. 25V @ 95°C

DD E XT

= 2.50V @ 25° C

D DE XT

= 2.75V @ -40°C

(
m

)

SOURCE VOLTAGE (V)

0.5

1.0

1.5

2.0

2.5

3. 0

3.5

150

100

200

150

O H

4.0

100

200

DD E XT

= 3.0V @ 95°C

DD E XT

= 3.3V @ 25°C

D D EX T

= 3.6V @ - 40°C

ADSP-BF538/ADSP-BF538F

Preliminary Technical Data

Rev. PrD

Page 45 of 56

May 2006

Figure 34. Drive Current C (Low V

DDEXT

)

Figure 35. Drive Current C (High V

DDEXT

)

Figure 36. Drive Current D (Low V

DDEXT

)

(
m

)

SOURCE VOLTAGE (V)

0.5

1. 0

1.5

2.0

2.5

3.0

D D EXT

= 2.25V @ 95°C

D D EXT

= 2.50V @ 25°C

D D EX T

= 2.75V @ -40°C

(
m

)

SOURCE VOLTAGE (V)

0.5

1.0

1.5

2.0

2.5

3. 0

3.5

O L

4.0

100

D D EX T

= 3. 0V @ 95° C

D D EX T

= 3. 3V @ 25° C

DD E XT

= 3.6V @ -40°C

(
m

)

SOURCE VOLTAGE (V)

0.5

1.0

1.5

2.0

2. 5

3.0

100

D DE XT

= 2.25V @ 95°C

D DE XT

= 2.50V @ 25°C

D D E XT

= 2.75V @ -40°C

Figure 37. Drive Current D (High V

DDEXT

)

Figure 38. Drive Current E (Low V

DDEXT

)

Figure 39. Drive Current E (High V

DDEXT

)

(
m

)

SOURCE VOLTAGE (V)

0.5

1.0

1.5

2.0

2.5

3. 0

3.5

100

150

4.0

100

150

D DE XT

= 3.0V @ 95° C

D DE XT

= 3.3V @ 25° C

DD E XT

= 3.6V @ -40°C

-40

(
m

)

SOURCE VOLTAGE (V)

0.5

1.0

1.5

2.0

2.5

3.0

-60

-10

-20

-30

-50

DD E XT

= 2.25V @ 95°C

DD E XT

= 2.50V @ 25°C

D D EX T

= 2.75V @ -40° C

-40

(
m

)

SOURCE VOLTAGE (V)

0. 5

1.0

1.5

2.0

2.5

3. 0

3.5

-10

-20

-80

-70

4.0

-60

-50

-30

D D EX T

= 3. 0V @ 95°C

D D EX T

= 3. 3V @ 25°C

D D EXT

= 3.6V @ -40°C

Rev. PrD

Page 46 of 56

May 2006

ADSP-BF538/ADSP-BF538F

Preliminary Technical Data

POWER DISSIPATION

Total power dissipation has two components: one due to inter-
nal circuitry (P

INT

) and one due to the switching of external

output drivers (P

EXT

Table 33

through

Table 35

show the power

dissipation for internal circuitry (V

DDINT

See the ADSP-BF53x Blackfin Processor Hardware Reference
Manual for definitions of the various operating -modes and for
instructions on how to minimize system power.

Many operating conditions can affect power dissipation. System
designers should refer to EE-TBD: Estimating Power for
ADSP-BF538/ADSP-BF538F Blackfin Processors." This docu-
ment will provide detailed information for optimizing your
design for lowest power.

TEST CONDITIONS

All timing parameters appearing in this data sheet were mea-
sured under the conditions described in this section.

Figure 40

shows the measurement point for AC measurements (except
output enable/disable). The measurement point V

MEAS

is 1.5 V

for V

DDEXT

(nominal) = 2.5/3.3 V.

Output Enable Time Measurement

Output pins are considered to be enabled when they have made
a transition from a high impedance state to the point when they
start driving.

The output enable time t

ENA

is the interval from the point when a

reference signal reaches a high or low voltage level to the point
when the output starts driving as shown on the right side of

Fig-

ure 41, "Output Enable/Disable," on page 47

The time t

ENA_MEASURED

is the interval, from when the reference

signal switches, to when the output voltage reaches V

TRIP

(high)

or V

TRIP

(low). V

TRIP

(high) is 2.0 V and V

TRIP

(low) is 1.0 V for

DDEXT

(nominal) = 2.5/3.3 V. Time t

TRIP

is the interval from

when the output starts driving to when the output reaches the
V

TRIP

(high) or V

TRIP

(low) trip voltage.

Time t

ENA

is calculated as shown in the equation:

If multiple pins (such as the data bus) are enabled, the measure-
ment value is that of the first pin to start driving.

Output Disable Time Measurement

Output pins are considered to be disabled when they stop driv-
ing, go into a high impedance state, and start to decay from their
output high or low voltage. The output disable time t

DIS

is the

difference between t

DIS

MEASURED

and t

DECAY

as shown on the left

side of

Figure 41

The time for the voltage on the bus to decay by V is dependent
on the capacitive load C

and the load current I

. This decay time

can be approximated by the equation:

The time t

DECAY

is calculated with test loads C

and I

, and with

V equal to 0.5 V for V

DDEXT

(nominal) = 2.5/3.3 V.

The time t

DIS

MEASURED

is the interval from when the reference sig-

nal switches, to when the output voltage decays V from the
measured output high or output low voltage.

Table 33. Internal Power Dissipation (Hibernate mode)

(nominal

)

Nominal assumes an operating temperature of 25°C.

Unit

DDHIBERNATE

Measured at V

DDEXT

= 3.65 V with voltage regulator off (V

DDINT

= 0 V).

TBD

DDRTC

Measured at V

DDRTC

= 3.3 V at 25°C.

TBD

Table 34. Internal Power Dissipation (Deep Sleep mode)

DDINT

Assumes V

DDINT

is regulated externally.

(nominal

)

Nominal assumes an operating temperature of 25°C.

Unit

0.80

19.00

0.90

25.00

1.00

32.00

1.10

40.00

1.26

54.00

Table 35. Internal Power Dissipation (Full On

mode)

Processor executing 75% dual MAC, 25% ADD with moderate data bus

activity.

DDINT

@ f

CCLK

(MHz)

Assumes V

DDINT

is regulated externally.

(nominal

)

Nominal assumes an operating temperature of 25°C.

Unit

0.8 @ 50 MHz

32.00

0.8 @ 250 MHz

72.00

0.9 @ 300 MHz

98.00

1.0 @ 350 MHz

132.00

1.1 @ 444 MHz

180.00

1.26 @ 500 MHz

235.00

Figure 40. Voltage Reference Levels for AC

Measurements (Except Output Enable/Disable)

INPUT

OUTPUT

1.5V

ENA

ENA_MEASURED

TRIP

DIS

DIS_MEASURED

DECAY

(

) I

ADSP-BF538/ADSP-BF538F

Preliminary Technical Data

Rev. PrD

Page 47 of 56

May 2006

Example System Hold Time Calculation

To determine the data output hold time in a particular system,
first calculate t

DECAY

using the equation given above. Choose V

to be the difference between the ADSP-BF538/ADSP-BF538F
processor's output voltage and the input threshold for the
device requiring the hold time. C

is the total bus capacitance

(per data line), and I

is the total leakage or three-state current

(per data line). The hold time will be t

DECAY

plus the various out-

put disable times as specified in the

Timing Specifications on

Page 24

(for example t

DSDAT

for an SDRAM write cycle as shown

Table 20 on Page 29

Capacitive Loading

Output delays and holds are based on standard capacitive loads:
30 pF on all pins (see

Figure 42

). V

LOAD

is 1.5 V for V

DDEXT

(nominal) = 2.5/3.3 V.

Figure 43

through

Figure 52 on Page 49

show how output rise time varies with capacitance. The delay
and hold specifications given should be derated by a factor
derived from these figures. The graphs in these figures may not
be linear outside the ranges shown.

Figure 41. Output Enable/Disable

Figure 42. Equivalent Device Loading for AC Measurements
(Includes All Fixtures)

REFERENCE

SIGNAL

DIS

OUTPUT STARTS DRIVING

(MEASURED)

(MEASURED) +

DIS_MEASURED

(MEASURED)

2.0V

1.0V

(MEASURED)

HIGH IMPEDANCE STATE.

TEST CONDITIONS CAUSE THIS

VOLTAGE TO BE APPROXIMATELY 1.5V.

OUTPUT STOPS DRIVING

ENA

DECAY

ENA-MEASURED

TRIP

1.5V

30pF

OUTPUT

PIN

Figure 43. Typical Output Delay or Hold for Driver A at V

DDEXT

MIN

Figure 44. Typical Output Delay or Hold for Driver A at V

DDEXT

MAX

ABE0

(133 MHz DRIVER), V

DDEXT

(MIN)

= 2.25V, TEMPERATURE = 85°C

LOAD CAPACITANCE (pF)

RISE TIME

AND

ALL

TIME

(10%

90%)

100

150

200

250

FALL TIME

ABE0

(133 MHz DRIVER), V

DDEXT

(MAX)

= 3.65V, TEMPERATURE = 85°C

LOAD CAPACITANCE (pF)

RISE TIME

AND

ALL

TIME

(10%

90%)

100

150

200

250

FALL TIME

Rev. PrD

Page 48 of 56

May 2006

ADSP-BF538/ADSP-BF538F

Preliminary Technical Data

Figure 45. Typical Output Delay or Hold for Driver B at V

DDEXT

MIN

Figure 46. Typical Output Delay or Hold for Driver B at V

DDEXT

MAX

CLKOUT (CLKOUT DRIVER), V

DDEXT

(MIN)

= 2.25V, TEMPERATURE = 85°C

LOAD CAPACITANCE (pF)

RISE TIME

AND

ALL

TIME

(10%

90%)

100

150

200

250

FALL TIME

CLKOUT (CLKOUT DRIVER), V

DDEXT

(MAX)

= 3.65V, TEMPERATURE = 85°C

LOAD CAPACITANCE (pF)

RISE TIME

AND

ALL

TIME

(10%

90%)

100

150

200

250

FALL TIME

Figure 47. Typical Output Delay or Hold for Driver C at V

DDEXT

MIN

Figure 48. Typical Output Delay or Hold for Driver C at V

DDEXT

MAX

PF9 (33 MHz DRIVER), V

DDEXT

(MIN)

= 2.25V, TEMPERATURE = 85°C

LOAD CAPACITANCE (pF)

RISE TIME

AND

ALL

TIME

(10%

90%)

100

150

200

250

FALL TIME

PF9 (33 MHz DRIVER), V

DDEXT

(MAX)

= 3.65V, TEMPERATURE = 85°C

LOAD CAPACITANCE (pF)

RISE TIME

AND

ALL

TIME

(10%

90%)

100

150

200

250

FALL TIME

ADSP-BF538/ADSP-BF538F

Preliminary Technical Data

Rev. PrD

Page 49 of 56

May 2006

Figure 49. Typical Output Delay or Hold for Driver D at V

DDEXT

MIN

Figure 50. Typical Output Delay or Hold for Driver D at V

DDEXT

MAX

SCK (66 MHz DRIVER), V

DDEXT

(MIN)

= 2.25V, TEMPERATURE = 85°C

LOAD CAPACITANCE (pF)

RISE TIME

AND

ALL

TIME

(10%

90%)

100

150

200

250

FALL TIME

SCK (66 MHz DRIVER), V

DDEXT

(MAX)

= 3.65V, TEMPERATURE = 85°C

LOAD CAPACITANCE (pF)

RISE TIME

AND

ALL

TIME

(10%

90%)

100

150

200

250

FALL TIME

Figure 51. Typical Output Delay or Hold for Driver E at V

DDEXT

MIN

Figure 52. Typical Output Delay or Hold for Driver E at V

DDEXT

MAX

PH0 V

DDEXT

(MAX)

= 3.65V, TEMPERATURE = 85°C

LOAD CAPACITANCE (pF)

RISE TIME

AND

ALL

TIME

(10%

90%)

100

150

200

250

FALL TIME

PH0 V

DDEXT

(MAX)

= 3.65V, TEMPERATURE = 85°C

LOAD CAPACITANCE (pF)

RISE TIME

AND

ALL

TIME

(10%

90%)

100

150

200

250

FALL TIME

Rev. PrD

Page 50 of 56

May 2006

ADSP-BF538/ADSP-BF538F

Preliminary Technical Data

THERMAL CHARACTERISTICS

To determine the junction temperature on the application
printed circuit board use:

where:

= Junction temperature ( C)

CASE

= Case temperature ( C) measured by customer at top

center of package.

= From

Table 36

= Power dissipation (see

Power Dissipation on Page 46

for

the method to calculate P

)

Values of

are provided for package comparison and printed

circuit board design considerations.

can be used for a first

order approximation of T

by the equation:

where:

= Ambient temperature ( C)

Values of

are provided for package comparison and printed

circuit board design considerations when an external heatsink is
required.

Values of

are provided for package comparison and printed

circuit board design considerations.

Table 36

, airflow measurements comply with JEDEC stan-

dards JESD51-2 and JESD51-6, and the junction-to-board
measurement complies with JESD51-8. The junction-to-case
measurement complies with MIL-STD-883 (Method 1012.1).
All measurements use a 2S2P JEDEC test board.

Table 36. Thermal Characteristics 316-ball BGA

Parameter

Condition

Typical

Unit

0 linear m/s air flow

TBD

C/W

JMA

1 linear m/s air flow

TBD

C/W

JMA

2 linear m/s air flow

TBD

C/W

TBD

C/W

TBD

C/W

0 linear m/s air flow

TBD

C/W

CASE

(

)

(

)

Rev. PrD

Page 52 of 56

May 2006

ADSP-BF538/ADSP-BF538F

Preliminary Technical Data

Table 37. 316-Ball Mini-BGA Pin Assignment (Numerically by Pin Number)

Ball No. Signal

GND

SPI2SEL

GND

J12

GND

M19

ABE0

GND

TCK

PF10

SPI2SS

GND

J13

GND

M20

ABE1

VDDEXT

GND

PF11

MOSI2

F10

GND

J14

GND

TFS0

VDDEXT

DATA15

PPI_CLK

C10

MISO2

F11

GND

J18

AMS0

DR0PRI

VDDEXT

DATA13

PPI0

C11

SCK2

F12

GND

J19

AMS2

GND

T10

VDDEXT

DATA11

PPI2

C12

VDDINT F13

GND

J20

SA10

VDDEXT T11

VDDEXT

DATA9

PF15

C13

SPI1SEL

F14

GND

RFS1

GND

T12

VDDINT

DATA7

PF13

C14

MISO1

F18

DT3PRI

K2 TMR2

GND

T13

VDDINT

DATA5

VDDRTC

C15

SPI1SS

F19

PC4 K3

VDDEXT N10

GND

T14

VDDINT

DATA3

A10

RTXO

C16

MOSI1

F20

PC8

GND

N11

GND

T18

RFS3

W10

DATA1

A11

RTXI

C17

SCK1

SCK0

GND

N12

GND

T19

ADDR7

W11

RSCK2

A12

GND

C18

GND

MOSI0

GND

N13

GND

T20

ADDR8

W12

DR2PRI

A13

CLKIN

C19

PC6

DT0SEC

K10

GND

N14

VDDINT U1

TRST

W13

DT2PRI

A14

XTAL

C20

SCKE

GND

K11

GND

N18

DT3SEC

TMS

W14

RX2

A15

GND

PF4

GND

K12

GND

N19

ADDR1

GND

W15

TX2

A16

D2 PF5

GND

K13

GND

N20

ADDR2

VDDEXT

W16

ADDR18

A17

GND

DT1SEC

G10

GND

K14

GND

TSCK0

VDDEXT

W17

ADDR15

A18

GPW

GND

G11

GND

K18

AMS3

P2 RFS0

VDDEXT

W18

ADDR13

A19

VROUT1

GND

G12

GND

K19

AMS1

GND

U10

VDDEXT

W19

GND

A20

GND

G13

GND

K20

AOE

VDDEXT U11

VDDEXT

W20

ADDR14

PF8

D10

GND

G14

GND

RSCK1

GND

U12

VDDINT

GND

D11

GND

G18

TMR1

GND

U13

VDDINT

TDO

PF9

D12

GND

G19

CLKOUT L3

GND

P10

GND

U14

VDDINT

DATA14

PF3

D13

GND

G20

SRAS

GND

P11

GND

U18

RSCK3

DATA12

PPI1

D14

GND

DT1PRI

GND

P12

GND

U19

ADDR9

DATA10

PPI3

D18

GND

TSCK1

GND

P13

GND

U20

ADDR10

DATA8

PF14

D19

PC7

DR1SEC

L10

GND

P14

VDDINT V1

TDI

DATA6

PF12

D20

SMS

GND

L11

GND

P18

DR3SEC

GND

DATA4

SCL0

PF1

GND

L12

GND

P19

ADDR3

GND

DATA2

B10

SDA0

PF2

GND

L13

GND

P20

ADDR4

BMODE1 Y10

DATA0

B11

CANRX

GND

H10

GND

L14

GND

TX0

BMODE0 Y11

RFS2

B12

CANTX

GND

H11

GND

L18

TSCK3

RSCK0

GND

Y12

TSCK2

B13

NMI

GND

H12

GND

L19

ARE

GND

VDDEXT

Y13

TFS2

B14

RESET

GND

H13

GND

L20

AWE

VDDEXT V8

VDDEXT

Y14

FRESET

B15

VDDEXT

E10

GND

H14

GND

DT0PRI

GND

VDDEXT

Y15

SCL1

B16

GND

E11

GND

H18

FCE

TMR0

GND

V10

VDDEXT

Y16

SDA1

B17

PC9

E12

GND

H19

SCAS

GND

R10

GND

V11

VDDEXT

Y17

ADDR19

B18

GND

E13

GND

H20

SWE

VDDEXT R11

GND

V12

VDDINT

Y18

ADDR17

B19

GND

E14

GND

TFS1

GND

R12

GND

V13

DR2SEC

Y19

ADDR16

B20

VROUT0

E18

GND

DR1PRI

GND

R13

GND

V14

Y20

GND

PF6

E19

PC5

DR0SEC

M10

GND

R14

VDDINT V15

BGH

PF7

E20

ARDY

GND

M11

GND

R18

DR3PRI

V16

DT2SEC

GND

PF0

GND

M12

GND

R19

ADDR5

V17

GND

F2 MISO0

GND

M13

GND

R20

ADDR6

V18

GND

RX1

GND

J10

GND

M14

VDDINT T1

RX0

V19

ADDR11

TX1

GND

J11

GND

M18

TFS3

EMU

V20

ADDR12

ADSP-BF538/ADSP-BF538F

Preliminary Technical Data

Rev. PrD

Page 53 of 56

May 2006

Table 38. 316-Ball Mini-BGA Pin Assignment (Alphabetically by Signal)

Signal

Ball No. Signal

Ball No. Signal Ball No. Signal Ball No. Signal

Ball No. Signal

Ball No.

ABE0

M19

DATA2

GND

K11

GND

V17

RFS0

P2 TX0

ABE1

M20

DATA3

GND

K12

GND

V18

RFS1

TX1

ADDR1

N19

DATA4

GND

K13

GND

RFS2

Y11

TX2

W15

ADDR10

U20

DATA5

GND

L13

GND

W19

RFS3

T18

VDDEXT K3

ADDR11

V19

DATA6

GND

L14

GND

RSCK0

VDDEXT B15

ADDR12

V20

DATA7

GND

F10

GND

Y20

RSCK1

VDDEXT T8

ADDR13

W18

DATA8

GND

F11

GND

A15

RSCK2

W11

VDDEXT T9

ADDR14

W20

DATA9

GND

F12

GND

B16

RSCK3

U18

VDDEXT T10

ADDR15

W17

DR0PRI

GND

F13

GND

M10

GND

A17

RTXI

A11

VDDEXT T11

ADDR16

Y19

DR0SEC J3

GND

F14

GND

M11

GPW

A18

RTXO

A10

VDDEXT U7

ADDR17

Y18

DR1PRI

GND

M12

MISO0

F2 RX0

VDDEXT U8

ADDR18

W16

DR1SEC H3

GND

M13

MISO1

C14

RX1

VDDEXT U9

ADDR19

Y17

DR2PRI

W12

GND

MISO2

C10

RX2

W14

VDDEXT U10

ADDR2

N20

DR2SEC V13

GND

E10

GND

K14

MOSI0

SA10

J20

VDDEXT U11

ADDR3

P19

DR3PRI

R18

GND

E11

GND

MOSI1

C16

SCAS

H19

VDDEXT V7

ADDR4

P20

DR3SEC P18

GND

E12

GND

MOSI2

SCK0

VDDEXT M7

ADDR5

R19

DT0PRI

GND

E13

GND

A16

SCK1

C17

VDDEXT N7

ADDR6

R20

DT0SEC G3

GND

E14

GND

NMI

B13

SCK2

C11

VDDEXT P7

ADDR7

T19

DT1PRI

GND

E18

GND

L10

PC4

F19

SCKE

C20

VDDEXT R7

ADDR8

T20

DT1SEC D3

GND

L11

PC5

E19

SCL0

VDDEXT T7

ADDR9

U19

DT2PRI

W13

GND

L12

PC6

C19

SCL1

Y15

VDDEXT V8

AMS0

J18

DT2SEC V16

GND

G10

GND

PC7

D19

SDA0

B10

VDDEXT V9

AMS1

K19

DT3PRI

F18

GND

G11

GND

PC8

F20

SDA1

Y16

VDDEXT V10

AMS2

J19

DT3SEC N18

GND

G12

GND

N10

PC9

C17

SMS

D20

VDDEXT V11

AMS3

K18

EMU

GND

G13

GND

N11

PF0

SPI1SEL C13

VDDINT C12

AOE

K20

FCE

H18

GND

G14

GND

N12

PF1

SPI1SS

C15

VDDINT M14

ARDY

E20

FRESET

Y14

GND

N13

PF10

SPI2SEL C7

VDDINT N14

ARE

L19

GND

PF11

SPI2SS

VDDINT P14

AWE

L20

GND

A12

GND

PF12

SRAS

G20

VDDINT R14

V14

GND

A20

GND

H10

GND

PF13

SWE

H20

VDDINT T12

BGH

V15

GND

H11

GND

P10

PF14

TCK

VDDINT T13

BMODE0

GND

B18

GND

H12

GND

P11

PF15

TDI

VDDINT T14

BMODE1

GND

B19

GND

H13

GND

P12

PF2

TDO

VDDINT U12

G18

GND

H14

GND

P13

PF3

TFS0

VDDINT U13

CANRX

B11

GND

PF4

TFS1

VDDINT U14

CANTX

B12

GND

C18

GND

PF5

D2 TFS2

Y13

VDDINT V12

CLKIN

A13

GND

PF6

TFS3

M18

VDDRTC A9

CLKOUT

G19

GND

J10

GND

R10

PF7

TMR0

VROUT0 B20

DATA0

Y10

GND

J11

GND

R11

PF8

TMR1

VROUT1 A19

DATA1

W10

GND

D10

GND

J12

GND

R12

PF9

TMR2

K2 XTAL

A14

DATA10

GND

D11

GND

J13

GND

R13

PPI_CLK

TMS

DATA11

GND

D12

GND

J14

GND

PPI0

TRST

DATA12

GND

D13

GND

PPI1

TSCK0

DATA13

GND

D14

GND

PPI2

TSCK1

DATA14

GND

D18

GND

PPI3

TSCK2

Y12

DATA15

GND

K10

GND

RESET

B14

TSCK3

L18

ADSP-BF538/ADSP-BF538F

Preliminary Technical Data

Rev. PrD

Page 55 of 56

May 2006

SURFACE MOUNT DESIGN

Table 39

is provided as an aid to PCB design. For industry-

standard design recommendations, refer to IPC-7351,
Generic Requirements for Surface Mount Design and Land Pat-
tern Standard.

ORDERING GUIDE

Table 39. BGA Data for Use with Surface Mount Design

Package

Ball Attach Type

Solder Mask
Opening

Ball Pad Size

316-Ball Mini Ball Grid Array
(BC-316)

Solder Mask Defined 0.40 mm diameter 0.50 mm diameter

Model

Z = Pb-free part.

Temperature
Range

Referenced temperature is ambient temperature.

Instruction
Rate (Max)

Flash
Memory

Operating Voltage
(Nominal)

Package Description

Package
Option

ADSP-BF538BBCZ-4A

40ºC to +85ºC 400 MHz