REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
ADP3300
High Accuracy anyCAP
®
50 mA Low Dropout Linear Regulator
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000
FUNCTIONAL BLOCK DIAGRAM
Q2
THERMAL
PROTECTION
Gm
Q1
CC
BANDGAP
REF
DRIVER
R1
R2
ADP3300
OUT
IN
ERR
SD
GND
FEATURES
High Accuracy (Over Line and Load Regulations
at 25 C): 0.8%
Ultralow Dropout Voltage: 80 mV Typical @ 50 mA
Requires Only C
O
= 0.47 F for Stability
anyCAPTM = Stable with All Types of Capacitors
(Including MLCC)
Current and Thermal Limiting
Low Noise
Dropout Detector
Low Shutdown Current: 1 A
3.0 V to 12 V Supply Range
40 C to +85 C Ambient Temperature Range
Several Fixed Voltage Options
Ultrasmall SOT-23 6-Lead Package
Excellent Line and Load Regulations
APPLICATIONS
Cellular Telephones
Notebook, Palmtop Computers
Battery Powered Systems
PCMCIA Regulators
Bar Code Scanners
Camcorders, Cameras
ADP3300-5
3
1
6
2
NR
OUT
IN
4
R1
330k
E
OUT
C2
0.47 F
V
OUT
= +5V
ON
OFF
GND
C1
0.47 F
V
IN
5
Figure 1. Typical Application Circuit
GENERAL DESCRIPTION
The ADP3300 is a member of the ADP330x family of precision
low dropout anyCAPTM voltage regulators. The ADP3300
stands out from conventional LDOs with a novel architecture
and an enhanced process. Its patented design requires only a
0.47
µF output capacitor for stability. This device is stable with
any capacitor, regardless of its ESR (Equivalent Series Resistance)
value, including ceramic types (MLCC) for space restricted appli-
cations. The ADP3300 achieves exceptional accuracy of
±0.8%
at room temperature and
±1.4% overall accuracy over tempera-
ture, line and load regulations. The dropout voltage of the
ADP3300 is only 80 mV (typical) at 50 mA.
The ADP3300 operates with a wide input voltage range from
3.0 V to 12 V and delivers a load current in excess of 50 mA. It
features an error flag that signals when the device is about to
lose regulation or when the short circuit or thermal overload
protection is activated. Other features include shutdown and
optional noise reduction capabilities. The ADP330x anyCAPTM
anyCAP is a registered trademark of Analog Devices Inc.
LDO family offers a wide range of output voltages and output
current levels from 50 mA to 200 mA:
ADP3301 (100 mA)
ADP3302 (100 mA, Dual Output)
ADP3303 (200 mA)
2
REV. A
ADP3300SPECIFICATIONS
Parameter
Symbol
Conditions
Min
Typ
Max
Units
OUTPUT VOLTAGE
V
OUT
V
IN
= V
OUT(NOM)
+0.3 V to 12 V
ACCURACY
I
L
= 0.1 mA to 50 mA
T
A
= +25
°C
0.8
+0.8
%
V
IN
= V
OUT(NOM)
+0.3 V to 12 V
I
L
= 0.1 mA to 50 mA
1.4
+1.4
%
LINE REGULATION
V
O
V
IN
= V
OUT(NOM)
+0.3 V to 12 V
V
IN
T
A
= +25
°C
0.02
mV/V
LOAD REGULATION
V
O
I
L
= 0.1 mA to 50 mA
I
L
T
A
= +25
°C
0.06
mV/mA
GROUND CURRENT
I
GND
I
L
= 50 mA
0.55
1.7
mA
I
L
= 0.1 mA
0.19
0.3
mA
GROUND CURRENT
I
GND
V
IN
= 2.5 V
IN DROPOUT
I
L
= 0.1 mA
0.6
1.2
mA
DROPOUT VOLTAGE
V
DROP
V
OUT
= 98% of V
OUT(NOM)
I
L
= 50 mA
0.08
0.17
V
I
L
= 10 mA
0.025
0.07
V
I
L
= 1 mA
0.004
0.03
V
SHUTDOWN THRESHOLD
V
THSD
ON
2.0
0.75
V
OFF
0.75
0.3
V
SHUTDOWN PIN
I
SDIN
0 < V
SD
5 V
1
µA
INPUT CURRENT
5 < V
SD
12 V @ V
IN
= 12 V
22
µA
GROUND CURRENT IN
I
Q
V
SD
= 0, V
IN
= 12 V
SHUTDOWN MODE
T
A
= +25
°C
0.005
1
µA
V
SD
= 0, V
IN
= 12 V
T
A
= +85
°C
0.01
3
µA
OUTPUT CURRENT IN
I
OSD
T
A
= +25
°C @ V
IN
= 12 V
2
µA
SHUTDOWN MODE
T
A
= +85
°C @ V
IN
= 12 V
4
µA
ERROR PIN OUTPUT
LEAKAGE
I
EL
V
EO
= 5 V
13
µA
ERROR PIN OUTPUT
"LOW" VOLTAGE
V
EOL
I
SINK
= 400
µA
0.12
0.3
V
PEAK LOAD CURRENT
I
LDPK
V
IN
= V
OUT(NOM)
+ 1 V
100
mA
OUTPUT NOISE
V
NOISE
f = 10 Hz100 kHz
@ 5 V OUTPUT
C
NR
= 0
100
µV
rms
C
NR
= 10 nF, C
L
= 10
µF
30
µV
rms
NOTE
Ambient temperature of +85
°C corresponds to a typical junction temperature of +125°C under typical full load test conditions.
Specifications subject to change without notice.
(@ T
A
= 40 C to +85 C, V
IN
= 7 V, C
IN
= 0.47 F, C
OUT
= 0.47 F, unless otherwise
noted)
ADP3300
3
REV. A
ABSOLUTE MAXIMUM RATINGS*
Input Supply Voltage . . . . . . . . . . . . . . . . . . . . 0.3 V to +16 V
Shutdown Input Voltage . . . . . . . . . . . . . . . . . 0.3 V to +16 V
Error Flag Output Voltage . . . . . . . . . . . . . . . . 0.3 V to +16 V
Noise Bypass Pin Voltage . . . . . . . . . . . . . . . . . 0.3 V to +5 V
Power Dissipation . . . . . . . . . . . . . . . . . . . . Internally Limited
Operating Ambient Temperature Range . . . . 55
°C to +125°C
Operating Junction Temperature Range . . . . 55
°C to +125°C
JA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
°C
JC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
°C
Storage Temperature Range . . . . . . . . . . . . . 65
°C to +150°C
Lead Temperature Range (Soldering 10 sec) . . . . . . . . +300
°C
Vapor Phase (60 sec ) . . . . . . . . . . . . . . . . . . . . . . . . +215
°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . +220
°C
*This is a stress rating only; operation beyond these limits can cause the device to
be permanently damaged.
PIN FUNCTION DESCRIPTIONS
Pin
Mnemonic
Function
1
GND
Ground Pin.
2
NR
Noise Reduction Pin. Used for further
reduction of the output noise (see text for
details). No connection if not used.
3
SD
Active Low Shutdown Pin. Connect to
ground to disable the regulator output.
When shutdown is not used, this pin should
be connected to the input pin.
4
OUT
Output of the Regulator, fixed 2.7, 3.0, 3.2,
3.3 or 5 volts output voltage. Bypass to
ground with a 0.47
µF or larger capacitor.
5
IN
Regulator Input.
6
ERR
Open Collector Output which goes low to
indicate that the output is about to go out
of regulation.
PIN CONFIGURATION
1
2
3
6
5
4
TOP VIEW
(Not to Scale)
OUT
NR
GND
IN
ERR
SD
ADP3300
Model
Voltage Output
Package Description
Package Options
Branding Information
ADP3300ART-2.7
2.7 V
Surface Mount
SOT-23-6
LAB
ADP3300ART-3
3.0 V
Surface Mount
SOT-23-6
LBB
ADP3300ART-3.2
3.2 V
Surface Mount
SOT-23-6
LCB
ADP3300ART-3.3
3.3 V
Surface Mount
SOT-23-6
LDB
ADP3300ART-5
5.0 V
Surface Mount
SOT-23-6
LEB
Contact the factory for the availability of other output voltage options.
ORDERING GUIDE
WARNING!
ESD SENSITIVE DEVICE
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADP3300 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
OUTPUT VOLTAGE Volts
OUTPUT LOAD mA
3.202
3.195
0
80
8
16
24
32
40
48
56
64
72
3.201
3.200
3.199
3.198
3.197
3.196
V
OUT
= 3.2V
V
IN
= 7V
Figure 3. Output Voltage vs. Load
Current
TEMPERATURE C
OUTPUT VOLTAGE
%
0.2
0.4
45 25
135
5
15
35
75
95
115
55
0.1
0.0
0.1
0.2
0.3
I
L
= 0 50mA
Figure 6. Output Voltage Variation %
vs. Temperature
INPUT VOLTAGE Volts
5
0
0
3
0
4
3
2
4
2
1
3
2
1
1
INPUT/OUTPUT VOLTAGE
Volts
R
L
= 33
V
OUT
= 3.2V
R
L
= 64
Figure 9. Power-Up/Power-Down
4
REV. A
INPUT VOLTAGE Volts
OUTPUT VOLTAGE
Volts
3.202
3.199
3.196
3.3
14
4
5
6
7
8
9
10 11 12 13
3.201
3.200
3.198
3.197
I
L
= 0mA
I
L
= 10mA
I
L
= 50mA
V
OUT
= 3.2V
Figure 2. Line Regulation Output
Voltage vs. Supply Voltage
OUTPUT LOAD mA
820
GROUND CURRENT
µA
690
170
0
80
20
40
60
560
430
300
I
L
= 0 TO 80mA
V
IN
= 7V
Figure 5. Quiescent Current vs. Load
Current
OUTPUT LOAD mA
120
96
0
80
20
40
60
72
48
24
0
INPUT/OUTPUT VOLTAGE
mV
Figure 8. Dropout Voltage vs. Output
Current
\
INPUT VOLTAGE Volts
800
640
0
0
12.0
1.2 2.4 3.6 4.8 6.0 7.2 8.4 9.6 10.8
480
320
GROUND CURRENT
A
160
V
OUT
= 3.2V
I
L
= 0mA
Figure 4. Quiescent Current vs.
Supply Voltage
TEMPERATURE C
700
0
45 25
600
400
300
200
100
500
15
35
55
75
95 115 135
5
V
IN
= 7V
GROUND CURRENT
A
I
L
= 50mA
I
L
= 0mA
Figure 7. Quiescent Current vs.
Temperature
TIME µs
0
0
100
200
2.0
V
SD
= V
IN
C
L
= 0.47µF
R
L
= 66
V
OUT
= 3.3V
1.0
3.0
4.0
5.0
6.0
7.0
8.0
20
INPUT/OUTPUT VOLTAGE
Volts
40 60
80
120 140 160 180
V
IN
V
OUT
Figure 10. Power-Up Overshoot
ADP3300Typical Performance Characteristics
ADP3300
5
REV. A
TIME µs
Volts
3.220
3.180
0
200
20
40
60
80 100 120 140 160 180
3.210
3.200
7.5
7.0
3.190
R
L
= 64
C
L
= 0.47µF
V
OUT
= 3.2V
Figure 12. Line Transient Response
TIME sec
200
0
0
5
1
2
3
4
150
100
3.0
0
50
mA
I
OUT
V
OUT
= 3.0V
Volts
V
OUT
V
IN
= 7V
Figure 15. Short Circuit Current
FREQUENCY Hz
RIPPLE REJECTION
dB
0
100
10
100
10M
1k
10k
100k
1M
10
60
70
80
90
20
30
50
40
a. 0.47µF, R
L
= 33k
b. 0.47µF, R
L
= 64
c. 4.7µF, R
L
= 33k
d. 4.7µF, R
L
= 64
b d
a c
b
d
a
c
V
OUT
= 3.3V
Figure 18. Power Supply Ripple
Rejection
TIME µs
Volts
3.220
3.180
0
200
20
40
60
80 100 120 140 160 180
3.210
3.200
7.5
7.0
3.190
R
L
= 3.2k
C
L
= 0.47µF
V
IN
V
OUT
= 3.2V
Figure 11. Line Transient Response
TIME µs
Volts
3.220
3.190
0
1000
200
400
600
800
3.205
3.200
50
1
3.195
V
OUT
= 3.2V
C
L
= 4.7µF
mA
I
OUT
= 50mA
1mA
Figure 14. Load Transient
TIME µs
2
0
0
100
20
40
60
80
1
0
4
3
3
V
OUT
= 3.2V
R
L
= 64
C
L
= 0.47µF
Volts
3.2V
V
Volts
Figure 17. Turn Off
TIME µs
Volts
3.220
3.190
0
1000
200
400
600
800
3.205
3.200
50
1
3.195
V
OUT
= 3.2V
C
L
= 0.47µF
mA
I
OUT
= 50mA
1mA
Figure 13. Load Transient
TIME s
2
0
0
100
20
40
60
80
1
0
4
3
+3
V
OUT
= 3.2V
R
L
= 64
Volts
V
OUT
C
L
= 0.47µF
3.2V
C
L
= 4.7µF
V
+3V
Figure 16. Turn On
FREQUENCY Hz
VOLTAGE NOISE SPECTRAL DENSITY
µV/ Hz
10
1
0.01
100
1k
100k
10k
0.1
0.47µF BYPASS
PIN 5 TO PIN 1
VOUT = 3.3V, C
L
= 0.47µF,
I
L
= 1mA, C
NR
= 0
VOUT = 5V, C
L
= 0.47µF,
I
L
= 1mA, C
NR
= 0
VOUT = 2.7-5.0V, C
L
= 0.47µF,
I
L
= 1mA, C
NR
= 10nF
VOUT = 2.7-5.0V, C
L
= 0.47µF,
I
L
= 1mA, C
NR
= 10nF
Figure 19. Output Noise Density
ADP3300
6
REV. A
THEORY OF OPERATION
The new anyCAPTM LDO ADP3300 uses a single control loop
for regulation and reference functions. The output voltage is
sensed by a resistive voltage divider consisting of R1 and R2
which is varied to provide the available output voltage option.
Feedback is taken from this network by way of a series diode
(D1) and a second resistor divider (R3 and R4) to the input of
an amplifier.
Gm
PTAT
V
OS
R4
R3
D1
R1
ATTENUATION
(V
BANDGAP
/V
OUT
)
R2
(a)
COMPENSATION
CAPACITOR
NONINVERTING
WIDEBAND
DRIVER
Q1
INPUT
C
LOAD
OUTPUT
ADP3300
R
LOAD
PTAT
CURRENT
Figure 20. Functional Block Diagram
A very high gain error amplifier is used to control this loop. The
amplifier is constructed in such a way that at equilibrium it
produces a large, temperature proportional input "offset voltage"
that is repeatable and very well controlled. The temperature-
proportional offset voltage is combined with the complimentary
diode voltage to form a "virtual bandgap" voltage, implicit in
the network, although it never appears explicitly in the circuit.
Ultimately, this patented design makes it possible to control the
loop with only one amplifier. This technique also improves the
noise characteristics of the amplifier by providing more flexibil-
ity on the trade-off of noise sources that leads to a low noise design.
The R1, R2 divider is chosen in the same ratio as the bandgap
voltage to the output voltage. Although the R1, R2 resistor
divider is loaded by the diode D1 and a second divider consist-
ing of R3 and R4, the values are chosen to produce a tempera-
ture stable output. This unique arrangement specifically corrects
for the loading of the divider so that the error resulting from
base current loading in conventional circuits is avoided.
The patented amplifier controls a new and unique noninverting
driver that drives the pass transistor, Q1. The use of this special
noninverting driver enables the frequency compensation to
include the load capacitor in a pole splitting arrangement to
achieve reduced sensitivity to the value, type and ESR of the
load capacitance.
Most LDOs place strict requirements on the range of ESR
values for the output capacitor because they are difficult to
stabilize due to the uncertainty of load capacitance and resis-
tance. Moreover, the ESR value, required to keep conventional
LDOs stable, changes depending on load and temperature.
These ESR limitations make designing with LDOs more
difficult because of their unclear specifications and extreme
variations over temperature.
This is no longer true with the ADP3300 anyCAPTM LDO. It
can be used with virtually any capacitor, with no constraint on
the minimum ESR. The innovative design allows the circuit to
be stable with just a small 0.47
µF capacitor on the output.
Additional advantages of the pole splitting scheme include superior
line noise rejection and very high regulator gain, which leads to
excellent line and load regulation. An impressive
±1.4% accuracy is
guaranteed over line, load and temperature.
Additional features of the circuit include current limit, thermal
shutdown and noise reduction. Compared to the standard
solutions that give warning after the output has lost regula-
tion, the ADP3300 provides improved system performance by
enabling the
ERR pin to give warning before the device loses
regulation.
As the chip's temperature rises above 165
°C, the circuit
activates a soft thermal shutdown, indicated by a signal low
on the
ERR pin, to reduce the current to a safe level.
To reduce the noise gain of the loop, the node of the main
divider network (a) is made available at the noise reduction (NR)
pin, which can be bypassed with a small capacitor (10 nF100 nF).
APPLICATION INFORMATION
Capacitor Selection: anyCAPTM
Output Capacitors: as with any micropower device, output
transient response is a function of the output capacitance. The
ADP3300 is stable with a wide range of capacitor values, types
and ESR (anyCAPTM). A capacitor as low as 0.47
µF is all that is
needed for stability. However, larger capacitors can be used if
high output current surges are anticipated. The ADP3300 is
stable with extremely low ESR capacitors (ESR
0), such as
multilayer ceramic capacitors (MLCC) or OSCON.
Input Bypass Capacitor: an input bypass capacitor is not
required; however, for applications where the input source is
high impedance or far from the input pins, a bypass capacitor is
recommended. Connecting a 0.47
µF capacitor from the input
to ground reduces the circuit's sensitivity to PC board layout. If
a bigger output capacitor is used, the input capacitor should be
1
µF minimum.
Noise Reduction
A noise reduction capacitor (C
NR
) can be used to further reduce
the noise by 6 dB10 dB (Figure 21). Low leakage capacitors in
the 10 nF100 nF range provide the best performance. For load
current less than 200
µA, a 4.7 µF output capacitor provides the
lowest noise and the best overall performance. Since the noise
reduction pin (NR) is internally connected to a high impedance
node, any connection to this node should be carefully done to
avoid noise pickup from external sources. The pad connected to
this pin should be as small as possible. Long PC board traces
are not recommended.
IN
OUT
GND
ADP3300-5
NR
+
6
1
2
3
4
5
ON
OFF
+
C2
4.7 F
330k
E
OUT
C1
1.0 F
V
OUT
= +5V
V
IN
C
NR
10nF
Figure 21. Noise Reduction Circuit
ADP3300
7
REV. A
Thermal Overload Protection
The ADP3300 is protected against damage due to excessive
power dissipation by its thermal overload protection circuit,
which limits the die temperature to a maximum of 165
°C.
Under extreme conditions (i.e., high ambient temperature and
high power dissipation), where die temperature starts to rise
above 165
°C, the output current is reduced until die tempera-
ture has dropped to a safe level. Output current is restored when
the die temperature is reduced.
Current and thermal limit protections are intended to protect
the device against accidental overload conditions. For normal
operation, device power dissipation should be externally limited
so that junction temperatures will not exceed 125
°C.
Calculating Junction Temperature
Device power dissipation is calculated as follows:
PD = (V
IN
V
OUT
) I
LOAD
+ (V
IN
) I
GND
Where I
LOAD
and I
GND
are load current and ground current, V
IN
and V
OUT
are input and output voltages respectively.
Assuming I
LOAD
= 50 mA, I
GND
= 0.5 mA, V
IN
= 8 V and
V
OUT
= 3.3 V, device power dissipation is:
PD = (8 3.3) 0.05 + 8
× 0.5 mA = 0.239 W
T = T
J
T
A
= PD
×
JA
= 0.239
× 165 = 39.4
°C
With a maximum junction temperature of 125
°C, this yields a
maximum ambient temperature of 85
°C.
Printed Circuit Board Layout Consideration
Surface mount components rely on the conductive traces or
pads to transfer heat away from the device. Appropriate PC
board layout techniques should be used to remove heat from the
immediate vicinity of the package.
The following general guidelines will be helpful when designing
a board layout:
1. PC board traces with larger cross section areas will remove
more heat. For optimum results, use PC boards with thicker
copper and wider traces.
2. Increase the surface area exposed to open air so heat can be
removed by convection or forced air flow.
3. Do not use solder mask or silkscreen on the heat dissipating
traces because it will increase the junction to ambient thermal
resistance of the package.
Shutdown Mode
Applying a TTL high signal to the shutdown pin or tying it to
the input pin will turn the output ON. Pulling the shutdown pin
down to 0.3 V or below, or tying it to ground, will turn the
output OFF. In shutdown mode, quiescent current is reduced
to less than 1
µA.
Error Flag Dropout Detector
The ADP3300 will maintain its output voltage over a wide
range of load, input voltage and temperature conditions. If the
output is about to lose regulation, for example, by reducing the
supply voltage below the combined regulated output and dropout
voltages, the
ERR pin will be activated. The ERR output is an
open collector that will be driven low.
Once set, the
ERRor flag's hysteresis will keep the output low
until a small margin of operating range is restored either by
raising the supply voltage or reducing the load.
APPLICATION CIRCUITS
Crossover Switch
The circuit in Figure 22 shows that two ADP3300s can be used
to form a mixed supply voltage system. The output switches
between two different levels selected by an external digital input.
Output voltages can be any combination of voltages from the
Ordering Guide.
ADP3300-5.0
OUT
IN
GND
OUTPUT SELECT
5.0V
0V
C1
1.0 F
ADP3300-3.3
OUT
IN
GND
C2
0.47 F
V
OUT
= 5V/3.3V
V
IN
= 5.5V TO 12V
Figure 22. Crossover Switch
Higher Output Current
If higher current is needed, an appropriate pass transistor can be
used, as in Figure 23, to increase the output current to 1 A.
V
IN
= 6V TO 8V
V
OUT
= 5V @ 1A
MJE253*
C2
10 F
C1
47 F
R1
50
*AAVID531002 HEAT SINK IS USED
IN
OUT
GND
ADP3300-5
Figure 23. High Output Current Linear Regulator
ADP3300
8
REV. A
C0013207/00 (rev .A)
PRINTED IN U.S.A.
6-Lead Surface Mount Package
(SOT-23)
0.122 (3.10)
0.106 (2.70)
PIN 1
0.071 (1.80)
0.059 (1.50)
0.118 (3.00)
0.098 (2.50)
0.075 (1.90)
BSC
0.037 (0.95) BSC
1
3
4
5
6
2
0.009 (0.23)
0.003 (0.08)
0.022 (0.55)
0.014 (0.35)
10
°
0
°
0.020 (0.50)
0.010 (0.25)
0.059 (0.15)
0.000 (0.00)
0.051 (1.30)
0.035 (0.90)
SEATING
PLANE
0.057 (1.45)
0.035 (0.90)
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
D1
1N5817
C2
100µF
10V
L1
6.8 H
R1
120
ADP3300-5
IN
OUT
GND
C3
2.2 F
5V @ 50mA
C1
100 F
10V
ADP3000-ADJ
I
LIM
V
IN
SW1
GND
SW2
FB
V
IN
= 2.5V TO 3.5V
R2
30.1k
1%
Q1
2N3906
Q2
2N3906
R4
274k
R3
124k
1%
Figure 24. Constant Dropout Post Regulator
Constant Dropout Post Regulator
The circuit in Figure 24 provides high precision with low dropout
for any regulated output voltage. It significantly reduces the
ripple from a switching regulator while providing a constant
dropout voltage, which limits the power dissipation of the
LDO to 15 mW. The ADP3000 used in this circuit is a
switching regulator in the step-up configuration.
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