Dual Bootstrapped 12 V MOSFET

Driver with Output Disable

ADP3118

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700

www.analog.com

Fax: 781.461.3113

FEATURES

Optimized for low gate charge MOSFETs
All-in-one synchronous buck driver
Bootstrapped high-side drive
One PWM signal generates both drives
Anticross-conduction protection circuitry
Output disable control turns off both MOSFETs

to float output per Intel® VRM 10 specification

APPLICATIONS

Multiphase desktop CPU supplies
Single-supply synchronous buck converters

GENERAL DESCRIPTION

The ADP3118 is a dual high voltage MOSFET driver optimized
for driving two N-channel MOSFETs, which are the two switches
in a nonisolated synchronous buck power converter. Each of the
drivers is capable of driving a 3000 pF load with a 25 ns
propagation delay and a 25 ns transition time. One of the drivers
can be bootstrapped and is designed to handle the high voltage
slew rate associated with floating high-side gate drivers. The
ADP3118 includes overlapping drive protection to prevent
shoot-through current in the external MOSFETs.

The OD pin shuts off both the high-side and the low-side
MOSFETs to prevent rapid output capacitor discharge during
system shutdown.

The ADP3118 is specified over the commercial temperature
range of 0°C to 85°C and is available in 8-lead SOIC package.

SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM

ADP3118

VCC

BST

DRVH

DRVL

PGND

DELAY

VCC

DELAY

CMP

CONTROL

LOGIC

BST

BST1

BST2

12V

INDUCTOR

05452-

001

Figure 1.

Flex-ModeTM is Protected by U.S. Patent 6683441

ADP3118

Rev. 0 | Page 2 of 16

TABLE OF CONTENTS

Specifications..................................................................................... 3

Absolute Maximum Ratings............................................................ 4

ESD Caution.................................................................................. 4

Pin Configuration and Function Descriptions............................. 5

Timing Characteristics..................................................................... 6

Typical Performance Characteristics ............................................. 7

Theory of Operation ........................................................................ 9

Low-Side Driver............................................................................ 9

High-Side Driver .......................................................................... 9

Overlap Protection Circuit.......................................................... 9

Application Information................................................................ 10

Supply Capacitor Selection ....................................................... 10

Bootstrap Circuit........................................................................ 10

MOSFET Selection..................................................................... 10

High-Side (Control) MOSFETs................................................ 10

Low-Side (Synchronous) MOSFETs ........................................ 11

PC Board Layout Considerations............................................. 11

Outline Dimensions ....................................................................... 13

Ordering Guide .......................................................................... 13

REVISION HISTORY

4/05

Revision 0: Initial Version

ADP3118

Rev. 0 | Page 3 of 16

SPECIFICATIONS

= 12 V, BST = 4 V to 26 V, T

= 0°C to 85°C, unless otherwise noted.

Table 1.

Parameter Symbol

Conditions

Min

Typ

Max

Unit

PWM INPUT

Input Voltage High

2.0

Input Voltage Low

0.8

Input Current

-1

µA

Hysteresis

250

OD INPUT

Input Voltage High

2.0

Input Voltage Low

0.8

Input Current

-1

µA

Hysteresis

250

Propagation Delay Times

pdlOD

See Figure 3

pdhOD

See Figure 3

HIGH-SIDE DRIVER

Output Resistance, Sourcing Current

BST - SW = 12 V

2.2

3.5

Output Resistance, Sinking Current

BST - SW = 12 V

1.0

2.5

Output Resistance, Unbiased

BST - SW = 0 V

Transition Times

rDRVH

BST - SW = 12 V, C

LOAD

= 3 nF, see Figure 4

fDRVH

BST - SW = 12 V, C

LOAD

= 3 nF, see Figure 4

Propagation Delay Times

pdhDRVH

BST - SW = 12 V, C

LOAD

= 3 nF, see Figure 4

pdlDRVH

BST - SW = 12 V, C

LOAD

= 3 nF, see Figure 4

SW Pull-Down Resistance

SW to PGND

LOW-SIDE DRIVER

Output Resistance, Sourcing Current

2.0

3.2

Output Resistance, Sinking Current

1.0

2.5

Output Resistance, Unbiased

VCC = PGND

Transition Times

rDRVL

LOAD

= 3 nF, see Figure 4

fDRVL

LOAD

= 3 nF, see Figure 4

Propagation Delay Times

pdhDRVL

LOAD

= 3 nF, see Figure 4

pdlDRVL

LOAD

= 3 nF, see Figure 4

Timeout Delay

SW = 5 V

110

190

SW = PGND

150

SUPPLY

Supply Voltage Range

4.15

13.2

Supply Current

SYS

BST = 12 V, IN = 0 V

UVLO Voltage

VCC rising

1.5

3.0

Hysteresis

350

All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC) methods.

For propagation delays, t

pdh

refers to the specified signal going high, and t

pdl

refers to it going low.

ADP3118

Rev. 0 | Page 4 of 16

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

VCC

-0.3 V to +15 V

BST

-0.3 V to VCC +15 V

BST to SW

-0.3 V to +15 V

-5 V to +15 V

<200 ns

-10 V to +25 V

DRVH

SW - 0.3 V to BST + 0.3 V

<200 ns

SW - 2 V to BST + 0.3 V

DRVL

-0.3 V to VCC + 0.3 V

<200 ns

-2 V to VCC + 0.3 V

IN, OD

-0.3 V to 6.5 V

, SOIC

2-Layer Board

123°C/W

4-Layer Board

90°C/W

Operating Ambient Temperature

Range

0°C to 85°C

Junction Temperature Range

0°C to 150°C

Storage Temperature Range

-65°C to +150°C

Lead Temperature Range

Soldering (10 sec)

300°C

Vapor Phase (60 sec)

215°C

Infrared (15 sec)

260°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

Unless otherwise specified, all voltages are referenced to PGND.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degrada-
tion or loss of functionality.

ADP3118

Rev. 0 | Page 5 of 16

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

BST

VCC

DRVH

PGND

DRVL

ADP3118

TOP VIEW

(Not to Scale)

05452-002

Figure 2. 8-Lead SOIC Pin Configuration

Table 3. Pin Function Descriptions

Pin No.

Mnemonic

Description

1 BST

Upper MOSFET Floating Bootstrap Supply. A capacitor connected between the BST and SW pins holds this
bootstrapped voltage for the high-side MOSFET as it is switched.

2 IN

Logic Level PWM Input. This pin has primary control of the driver outputs. In normal operation, pulling this pin
low turns on the low-side driver; pulling it high turns on the high-side driver.

Output Disable. When low, this pin disables normal operation, forcing DRVH and DRVL low.

VCC

Input Supply. This pin should be bypassed to PGND with ~1 µF ceramic capacitor.

DRVL

Synchronous Rectifier Drive. Output drive for the lower (synchronous rectifier) MOSFET.

PGND

Power Ground. Should be closely connected to the source of the lower MOSFET.

7 SW

This pin is connected to the buck-switching node, close to the upper MOSFET's source. It is the floating return
for the upper MOSFET drive signal. It is also used to monitor the switched voltage to prevent turn-on of the
lower MOSFET until the voltage is below ~1 V.

DRVH

Buck Drive. Output drive for the upper (buck) MOSFET.

ADP3118

Rev. 0 | Page 7 of 16

TYPICAL PERFORMANCE CHARACTERISTICS

05452-006

DRVH

DRVL

Figure 5. DRVH Rise and DRVL Fall Times

LOAD

= 6 nF for DRVL, C

LOAD

= 2 nF for DRVH

05452-007

DRVH

DRVL

Figure 6. DRVH Fall and DRVL Rise Times

LOAD

= 6 nF for DRVL, C

LOAD

= 2 nF for DRVH

125

05452-008

JUNCTION TEMPERATURE (

I
SE TIM

(

100

DRVL

DRVH

VCC = 12V

LOAD

= 3nF

Figure 7. DRVH and DRVL Rise Times vs. Temperature

125

05452-009

JUNCTION TEMPERATURE (

FALL TIME (ns)

100

DRVL

DRVH

VCC = 12V

LOAD

= 3nF

Figure 8. DRVH and DRVL Fall Times vs. Temperature

2.0

5.0

05452-010

LOAD CAPACITANCE (nF)

I
SE TIM

(

2.5

3.0

3.5

4.0

4.5

= 25

VCC = 12V

DRVH

DRVL

Figure 9. DRVH and DRVL Rise Times vs. Load Capacitance

2.0

5.0

05452-011

LOAD CAPACITANCE (nF)

FALL TIME (ns)

2.5

3.0

3.5

4.0

4.5

VCC = 12V

= 25

DRVH

DRVL

Figure 10. DRVH and DRVL Fall Times vs. Load Capacitance

ADP3118

Rev. 0 | Page 9 of 16

THEORY OF OPERATION

The ADP3118 is a dual-MOSFET driver optimized for driving
two N-channel MOSFETs in a synchronous buck converter
topology. A single PWM input signal is all that is required to
properly drive the high-side and the low-side MOSFETs. Each
driver is capable of driving a 3 nF load at speeds up to 500 kHz.

A more detailed description of the ADP3118 and its features
follows. See Figure 1.

LOW-SIDE DRIVER

The low-side driver is designed to drive a ground-referenced
N-channel MOSFET. The bias to the low-side driver is
internally connected to the VCC supply and PGND.

When the driver is enabled, the driver's output is 180° out of
phase with the PWM input. When the ADP3118 is disabled,
the low-side gate is held low.

HIGH-SIDE DRIVER

The high-side driver is designed to drive a floating N-channel
MOSFET. The bias voltage for the high-side driver is developed
by an external bootstrap supply circuit, which is connected
between the BST and SW pins.

The bootstrap circuit comprises a diode, D1, and bootstrap
capacitor, C

BST1

. C

BST2

and R

BST

are included to reduce the high-

side gate drive voltage and to limit the switch node slew rate
(referred to as a Boot-Snap circuit, see the Application
Information section for more details). When the ADP3118 is
starting up, the SW pin is at ground, so the bootstrap capacitor
charges up to VCC through D1. When the PWM input goes
high, the high-side driver begins to turn on the high-side
MOSFET, Q1, by pulling charge out of C

BST1

and C

BST2

. As Q1

turns on, the SW pin rises up to V

, forcing the BST pin to V

+ V

C (BST)

, which is enough gate-to-source voltage to hold Q1 on.

To complete the cycle, Q1 is switched off by pulling the gate
down to the voltage at the SW pin. When the low-side
MOSFET, Q2, turns on, the SW pin is pulled to ground. This
allows the bootstrap capacitor to charge up to VCC again.

The high-side driver's output is in phase with the PWM input.
When the driver is disabled, the high-side gate is held low.

OVERLAP PROTECTION CIRCUIT

The overlap protection circuit prevents both of the main power
switches, Q1 and Q2, from being on at the same time. This is
done to prevent shoot-through currents from flowing through
both power switches and the associated losses that can occur
during their on/off transitions. The overlap protection circuit
accomplishes this by adaptively controlling the delay from the
Q1 turn off to the Q2 turn on, and by internally setting the
delay from the Q2 turn off to the Q1 turn on.

To prevent the overlap of the gate drives during the Q1 turn off
and the Q2 turn on, the overlap circuit monitors the voltage at
the SW pin. When the PWM input signal goes low, Q1 begins
to turn off (after propagation delay). Before Q2 can turn on, the
overlap protection circuit makes sure that SW has first gone
high and then waits for the voltage at the SW pin to fall from
V

to 1 V. Once the voltage on the SW pin falls to 1 V, Q2

begins turn on. If the SW pin has not gone high first, the Q2
turn on is delayed by a fixed 150 ns. By waiting for the voltage
on the SW pin to reach 1 V or for the fixed delay time, the
overlap protection circuit ensures that Q1 is off before Q2 turns
on, regardless of variations in temperature, supply voltage, input
pulse width, gate charge, and drive current. If SW does not go
below 1 V after 190 ns, DRVL turns on. This can occur if the
current flowing in the output inductor is negative and is flowing
through the high-side MOSFET body diode.

ADP3118

Rev. 0 | Page 10 of 16

APPLICATION INFORMATION

SUPPLY CAPACITOR SELECTION

For the supply input (V

) of the ADP3118, a local bypass

capacitor is recommended to reduce the noise and to supply
some of the peak currents drawn. Use a 4.7 µF, low ESR
capacitor. Multilayer ceramic chip (MLCC) capacitors provide
the best combination of low ESR and small size. Keep the
ceramic capacitor as close as possible to the ADP3118.

BOOTSTRAP CIRCUIT

The bootstrap circuit uses a charge storage capacitor (C

BST

)

and a diode, as shown in Figure 1. These components can be
selected after the high-side MOSFET is chosen. The bootstrap
capacitor must have a voltage rating that can handle twice the
maximum supply voltage. A minimum 50 V rating is
recommended. The capacitor values are determined by:

GATE

BST2

BST1

(1)

GATE

BST2

BST1

(2)

where:
Q

GATE

is the total gate charge of the high-side MOSFET at V

GATE

is the desired gate drive voltage (usually in the range of 5 V

to 10 V, 7 V being typical).
V

is the voltage drop across D1.

Rearranging Equations 1 and 2 to solve for C

BST1

yields

GATE

BST1

= 10

BST2

can then be found by rearranging Equation 1

BST

GATE

BST2

For example, an NTD60N02 has a total gate charge of about
12 nC at V

GATE

= 7 V. Using V

= 12 V and V

= 1 V, one finds

BST1

= 12 nF and C

BST2

= 6.8 nF. Good quality ceramic capacitors

should be used.

BST

is used for slew-rate limiting to minimize the ringing at the

switch node. It also provides peak current limiting through D1.
An R

BST

value of 1.5 to 2.2 is a good choice. The resistor

needs to be able to handle at least 250 mW due to the peak
currents that flow through it.

A small-signal diode can be used for the bootstrap diode due
to the ample gate drive voltage supplied by V

. The bootstrap

diode must have a minimum 15 V rating to withstand the
maximum supply voltage. The average forward current can
be estimated by

MAX

GATE

AVG

)

(

(3)

where

MAX

is the maximum switching frequency of the

controller. The peak surge current rating should be calculated
using

BST

PEAK

)

(

(4)

MOSFET SELECTION

When interfacing the ADP3118 to external MOSFETs, there are
a few considerations that the designer should be aware of. These
help to make a more robust design that minimizes stresses on
both the driver and the MOSFETs. These stresses include
exceeding the short-time duration voltage ratings on the driver
pins as well as the external MOSFET.

It is also highly recommended to use the Boot-Snap circuit to
improve the interaction of the driver with the characteristics of
the MOSFETs. If a simple bootstrap arrangement is used, make
sure to include a proper snubber network on the SW node.

HIGH-SIDE (CONTROL) MOSFETS

The high-side MOSFET is usually selected to be high speed to
minimize switching losses (see the

ADP3186

ADP3188

data

sheet for Flex-Mode controller details). This usually implies a
low gate resistance and low input capacitance/charge device.
Yet, a significant source lead inductance can also exist. This
depends mainly on the MOSFET package; it is best to contact
the MOSFET vendor for this information.

The ADP3118 DRVH output impedance and the input resistance
of the MOSFETs determine the rate of charge delivery to the
gate's internal capacitance. This determines the speed at which
the MOSFETs turn on and off. However, due to potentially large
currents flowing in the MOSFETs at the on and off times (this
current is usually larger at turn off due to ramping up of the out-
put current in the output inductor), the source lead inductance
generates a significant voltage when the high-side MOSFETs
switch off. This creates a significant drain-source voltage spike
across the internal die of the MOSFETs and can lead to a
catastrophic avalanche. The mechanisms involved in this
avalanche condition can be referenced in literature from the
MOSFET suppliers.

ADP3118

Rev. 0 | Page 11 of 16

The MOSFET vendor should provide a maximum voltage slew
rate at drain current rating such that this can be designed around.
Once you have this specification, determine the maximum
current you expect to see in the MOSFET. This can be done
with the following equation:

(

)

OUT

MAX

OUT

MAX

phase

per

)

(

(5)

where:
D

MAX

is determined for the VR controller being used with

the driver. This current is divided roughly equally between
MOSFETs if more than one is used (assume a worst-case
mismatch of 30% for design margin).
L

OUT

is the output inductor value.

When producing your design, there is no exact method for
calculating the dV/dt due to the parasitic effects in the external
MOSFETs as well as the PCB. However, it can be measured to
determine if it is safe. If it appears that the dV/dt is too fast, an
optional gate resistor can be added between DRVH and the
high-side MOSFETs. This resistor slows down the dV/dt, but it
increases the switching losses in the high-side MOSFETs. The
ADP3118 has been optimally designed with an internal drive
impedance that works with most MOSFETs to switch them
efficiently yet minimizes dV/dt. However, some high speed
MOSFETs may require this external gate resistor depending on
the currents being switched in the MOSFET.

LOW-SIDE (SYNCHRONOUS) MOSFETS

The low-side MOSFETs are usually selected to have a low on
resistance to minimize conduction losses. This usually implies a
large input gate capacitance and gate charge. The first concern is
to make sure the power delivery from the ADP3118's DRVL
does not exceed the thermal rating of the driver (see the

ADP3186

ADP3188

data sheet for Flex-Mode controller

details).

The next concern for the low-side MOSFETs is based on
preventing them from inadvertently being switched on when
the high-side MOSFET turns on. This occurs due to the drain-
gate (Miller, also specified as C

rss

) capacitance of the MOSFET.

When the drain of the low-side MOSFET is switched to VCC by
the high-side turning on (at a rate dV/dt), the internal gate of
the low-side MOSFET is pulled up by an amount roughly equal
to V

× (C

rss

iss

). It is important to make sure this does not put

the MOSFET into conduction.

Another consideration is the nonoverlap circuitry of the
ADP3118, which attempts to minimize the nonoverlap period.
During the state of the high-side turning off to low-side turning
on, the SW pin is monitored (as well as the conditions of SW
prior to switching) to adequately prevent overlap.

However, during the low-side turn off to high-side turn on,
the SW pin does not contain information for determining the

proper switching time, so the state of the DRVL pin is moni-
tored to go below one sixth of V

. A delay is then added. Due

to the Miller capacitance and internal delays of the low-side
MOSFET gate, one must ensure that the Miller to input capaci-
tance ratio is low enough and that the low-side MOSFET internal
delays are not so large as to allow accidental turn on of the low-
side when the high-side turns on.

Contact sales for an updated list of recommended low-side
MOSFETs.

PC BOARD LAYOUT CONSIDERATIONS

Use the following general guidelines when designing printed
circuit boards.

Trace out the high current paths and use short, wide
(>20 mil) traces to make these connections.

Minimize trace inductance between DRVH and DRVL
outputs and MOSFET gates.

Connect the PGND pin of the ADP3118 as closely as
possible to the source of the lower MOSFET.

Locate the V

bypass capacitor as close as possible to the

VCC and PGND pins.

Use vias to other layers when possible to maximize thermal
conduction away from the IC.

The circuit in Figure 15 shows how four drivers can be
combined with the ADP3188 to form a total power conversion
solution for generating V

CC (CORE)

for an Intel CPU that is VRD

10.x-compliant.

Figure 14 shows an example of the typical land patterns based
on the guidelines given previously. For more detailed layout
guidelines for a complete CPU voltage regulator subsystem,
refer to the PC Board Layout Considerations section of the

ADP3188

data sheet.

05452-015

BST2

BST1

BST

VCC

Figure 14. External Component Placement Example

ADP3118

Rev. 0 | Page 12 of 16

1N4148

C19

Q13

NTD60N02

Q15

NTD110N02

Q16

NTD110N02

C16

8nF

C17

ADP

3118

DRV

320nH/

100k

, 5

C20

12nF

1N4148

C15

NTD60N02

Q11

NTD110N02

Q12

NTD110N02

C14

8nF

C13

ADP

3118

DRV

320nH/

C16

12nF

1N4148

C11

NTD60N02

NTD110N02

C10

8nF

ADP

3118

DRV

1N4148

320nH/

C12

12nF

1N4148

NTD60N02

NTD110N02

8nF

ADP

3118

DRV

320nH/

12nF

C24

CC I

CKE

CC (CO

)

8375V

 1.

95A TDC,

119A P

CC (CO

) RTN

560

F/4V

SEPC

SER

IES

ACH

ADP

3188

VID

BRT

COM

RAM

ADJ

GND

COM

SSU

ILIMIT

158k

84.

470pF

35.

12.

21k

5nF

22pF

560pF

C22

1nF

150k

C23

1nF

C21

1nF

GOOD

NABL

LDY

39nF

LDY

470k

137k

357k

100

+ C1

370nH

18A

2700

F/1

6
V

MV-

X SER

IES

12V

05452-

016

SW1

SW2

SW3

SW4

NOT

1. FOR

ESC

I
PTION

OF OPTION

MPON

TS, SEE TH

E A

3188 TH

EOR

OF OPER

ION

SEC

TION

R1 10

Figure 15. VRD 10-Compliant Power Supply Circuit

ADP3118

Rev. 0 | Page 13 of 16

OUTLINE DIMENSIONS

0.25 (0.0098)
0.17 (0.0067)

1.27 (0.0500)
0.40 (0.0157)

0.50 (0.0196)
0.25 (0.0099)

45°

8°
0°

1.75 (0.0688)
1.35 (0.0532)

SEATING

PLANE

0.25 (0.0098)
0.10 (0.0040)

5.00 (0.1968)
4.80 (0.1890)

4.00 (0.1574)
3.80 (0.1497)

1.27 (0.0500)

BSC

6.20 (0.2440)
5.80 (0.2284)

0.51 (0.0201)
0.31 (0.0122)

COPLANARITY

0.10

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

COMPLIANT TO JEDEC STANDARDS MS-012-AA

Figure 16. 8-Lead Standard Small Outline Package [SOIC_N]

Narrow Body

(R-8)

Dimensions shown in millimeters (inches)

ORDERING GUIDE

Model

Temperature
Range

Package Description

Package
Option

Quantity
per Reel

ADP3118JRZ

0°C to 85°C

8-Lead Standard Small Outline Package (SOIC_N)

R-8

N/A

ADP3118JRZ-RL

0°C to 85°C

8-Lead Standard Small Outline Package(SOIC_N)

R-8

2500

Z = Pb-free part.

Part Number ADP3118

Document Outline