Document Outline
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- GENERAL DESCRIPTION
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- OUTPUT AND TIMING SPECIFICATIONS
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- LOSS-OF-SIGNAL (LOS) DETECTOR
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- Using the Reference Clock to Lock onto Data
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- Transmission Lines
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- Choosing AC Coupling Capacitors
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Continuous Rate 10 Mb/s to 1.25 Gb/s Clock and
Data Recovery IC with Integrated Limiting Amp
ADN2813
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
© 2005 Analog Devices, Inc. All rights reserved.
FEATURES
Serial data input: 10 Mb/s to 1.25 Gb/s
Exceeds SONET requirements for jitter transfer/
generation/tolerance
Quantizer sensitivity: 3.3 mV typ
Adjustable slice level: ±95 mV
Patented clock recovery architecture
Loss-of-signal (LOS) detect range: 2.3 mV to 19 mV
Independent slice level adjust and LOS detector
No reference clock required
Loss-of-lock indicator
I
2
C® interface to access optional features
Single-supply operation: 3.3 V
Low power: 450 mW typ
5 mm × 5 mm 32-lead LFCSP, Pb free
APPLICATIONS
SONET OC-1/-3/-12 and all associated FEC rates
Fibre Channel, GbE, HDTVs
WDM transponders
Regenerators/repeaters
Test equipment
Broadband cross-connects and routers
GENERAL DESCRIPTION
The ADN2813 provides the receiver functions of quantization,
signal level detect, and clock and data recovery for continuous
data rates from 10 Mb/s to 1.25 Gb/s. The ADN2813 automati-
cally locks to all data rates without the need for an external
reference clock or programming. All SONET jitter requirements
are met, including jitter transfer, jitter generation, and jitter
tolerance. All specifications are quoted for -40°C to +85°C
ambient temperature, unless otherwise noted.
This device, together with a PIN diode and a TIA preamplifier,
can implement a highly integrated, low cost, low power fiber
optic receiver.
The receiver front-end, loss-of-signal (LOS) detector circuit
indicates when the input signal level has fallen below a user-
adjustable threshold. The LOS detect circuit has hysteresis to
prevent chatter at the output.
The ADN2813 is available in a compact 5 mm × 5 mm,
32-lead LFCSP.
FUNCTIONAL BLOCK DIAGRAM
2
04951-
0-
001
SLICEP/N
LOL
DATAOUTP/N
LOS
THRADJ
CLKOUTP/N
ADN2813
2
VCC
VEE
CF1
CF2
PIN
NIN
VREF
QUANTIZER
VCO
PHASE
SHIFTER
PHASE
DETECT
FREQUENCY
DETECT
LOS
DETECT
DATA
RE-TIMING
LOOP
FILTER
LOOP
FILTER
REFCLKP/N
(OPTIONAL)
2
Figure 1.
ADN2813
Rev. 0 | Page 2 of 28
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Jitter Specifications....................................................................... 4
Output and Timing Specifications ............................................. 5
Absolute Maximum Ratings............................................................ 6
Thermal Characteristics .............................................................. 6
ESD Caution.................................................................................. 6
Timing Characteristics..................................................................... 7
Pin Configuration and Function Descriptions............................. 8
Typical Performance Characteristics ............................................. 9
I
2
C Interface Timing and Internal Register Description ........... 10
Terminology .................................................................................... 12
Jitter Specifications ......................................................................... 13
Theory of Operation ...................................................................... 14
Functional Description.................................................................. 16
Frequency Acquisition............................................................... 16
Limiting Amplifier ..................................................................... 16
Slice Adjust.................................................................................. 16
Loss-of-Signal (LOS) Detector ................................................. 16
Lock Detector Operation .......................................................... 16
Harmonic Detector .................................................................... 17
SQUELCH Mode........................................................................ 18
I
2
C Interface ................................................................................ 18
Reference Clock (Optional) ...................................................... 18
Applications Information .............................................................. 21
PCB Design Guidelines ............................................................. 21
DC-Coupled Application .......................................................... 23
Coarse Data Rate Readback Look-Up Table............................... 24
Outline Dimensions ....................................................................... 26
Ordering Guide .......................................................................... 26
REVISION HISTORY
9/05--Revision 0: Initial Version
ADN2813
Rev. 0 | Page 3 of 28
SPECIFICATIONS
T
A
= T
MIN
to T
MAX
, VCC = V
MIN
to V
MAX
, VEE = 0 V, C
F
= 0.47 F, SLICEP = SLICEN = VEE, input data pattern: PRBS 2
23
- 1,
unless otherwise noted.
Table 1.
Parameter Conditions
Min
Typ
Max
Unit
QUANTIZER--DC
CHARACTERISTICS
Input Voltage Range
@ PIN or NIN, dc-coupled
1.8
2.8
V
Peak-to-Peak Differential Input
PIN - NIN
2.0
V
Input Common-Mode Level
DC-coupled (see Figure 27, Figure 28, and Figure 29) 2.3 2.5 2.8 V
Differential Input Sensitivity
2
23
- 1 PRBS, ac-coupled,
1
BER = 1 × 10
10
6 3.3
mV
p-p
Input
Offset
500
V
Input RMS Noise
BER = 1 × 10
10
290
V
rms
QUANTIZER--AC
CHARACTERISTICS
Data Rate
10
1250
Mb/s
S11
@ 2.5 GHz
-15
dB
Input
Resistance
Differential
100
Input
Capacitance
0.65
pF
QUANTIZER--SLICE
ADJUSTMENT
Gain
SLICEP SLICEN = ±0.5 V
0.10
0.11
0.13
V/V
Differential Control Voltage Input
SLICEP SLICEN
-0.95
+0.95
V
Control Voltage Range
DC level @ SLICEP or SLICEN
VEE
0.95
V
Slice
Threshold
Offset
1
mV
LOSS-OF-SIGNAL (LOS) DETECT
Loss-of-Signal Detect Range (see Figure 6) R
THRESH
= 0
14
16.5
19
mV
R
THRESH
= 100 k
2.3
3.5
4.7
mV
Hysteresis
(Electrical)
GbE
R
THRESH
= 0
6.4
7.2
8.0
dB
R
THRESH
= 100 k
4.6
6.2
7.8
dB
OC-1
R
THRESH
= 0
5.5
6.6
7.7
dB
R
THRESH
= 10 k
3.1
5.4
7.7
dB
LOS Assert Time
DC-coupled
2
500
ns
LOS Deassert Time
DC-coupled
2
400
ns
LOSS-OF-LOCK (LOL) DETECT
VCO Frequency Error for LOL Assert
With respect to nominal
1000
ppm
VCO Frequency Error for LOL Deassert
With respect to nominal
250
ppm
LOL Response Time
10 Mb/s
5
ms
OC-12
200
s
GbE
200
s
ACQUISITION
TIME
Lock-to-Data
Mode
GbE
1.5
ms
OC-12
2.0
ms
OC-3
3.4
ms
OC-1
9.8
ms
10
Mb/s
40.0
ms
Optional Lock to REFCLK Mode
20.0
ms
DATA RATE READBACK ACCURACY
Coarse Readback
See Table 13
10
%
Fine Readback
In addition to REFCLK accuracy
Data rate 20 Mb/s
200
ppm
Data rate > 20 Mb/s
100
ppm
ADN2813
Rev. 0 | Page 4 of 28
Parameter Conditions
Min
Typ
Max
Unit
POWER SUPPLY VOLTAGE
3.0
3.3
3.6
V
POWER SUPPLY CURRENT
Locked to 1.25 Gb/s
139
155
mA
OPERATING TEMPERATURE RANGE
40
+85
°C
1
PIN and NIN should be differentially driven and ac-coupled for optimum sensitivity.
2
When ac-coupled, the LOS assert and deassert times are dominated by the RC time constant of the ac coupling capacitor and the 50 input termination of the
ADN2813 input stage.
JITTER SPECIFICATIONS
T
A
= T
MIN
to T
MAX
, VCC = V
MIN
to V
MAX
, VEE = 0 V, C
F
= 0.47 F, SLICEP = SLICEN = VEE, input data pattern: PRBS 2
23
- 1,
unless otherwise noted.
Table 2.
Parameter Conditions
Min
Typ
Max
Unit
PHASE-LOCKED
LOOP
CHARACTERISTICS
Jitter Transfer BW
OC-12
75
130
kHz
OC-3
26
42
kHz
Jitter Peaking
OC-12
0
0.03
dB
OC-3
0
0.03
dB
Jitter Generation
OC-12, 12 kHz to 5 MHz
0.001
0.003
UI rms
0.011
0.026
UI
p-p
OC-3, 12 kHz to 1.3 MHz
0.001
0.002
UI rms
0.005
0.010
UI
p-p
Jitter Tolerance
1 GbE, IEEE 802.3
637 kHz
0.749
UI p-p
OC-12,
2
23
- 1 PRBS
30
Hz
1
100
UI
p-p
300
Hz
1
44
UI
p-p
25 kHz
2.5
UI p-p
250
kHz
1
1.0
UI
p-p
OC-3,
2
23
- 1 PRBS
30
Hz
1
50
UI
p-p
300
Hz
1
23.5
UI
p-p
6500 Hz
3.5
UI p-p
65
kHz
1
1.0
UI
p-p
1
Jitter tolerance of the ADN2813 at these jitter frequencies is better than what the test equipment is able to measure.
ADN2813
Rev. 0 | Page 5 of 28
OUTPUT AND TIMING SPECIFICATIONS
Table 3.
Parameter Conditions
Min
Typ
Max
Unit
LVDS OUTPUT CHARACTERISTICS
(CLKOUTP/CLKOUTN, DATAOUTP/DATAOUTN)
Output Voltage High
V
OH
(see Figure 3), 655 Mb/s
1475
mV
Output Voltage Low
V
OL
(see Figure 3), 655 Mb/s
925
mV
Differential Output Swing
V
OD
(see Figure 3), 655 Mb/s
250
320
400
mV
Differential Output Swing
V
OD
(see Figure 3), 1.25 Gb/s
240
300
400
Output Offset Voltage
V
OS
(see Figure 3) 1125
1200
1275
mV
Output Impedance
Differential
100
LVDS Outputs Timing
GbE
Rise Time
20% to 80%
115
220
ps
Fall Time
80% to 20%
115
220
ps
Setup Time
T
S
(see Figure 2), GbE
360
400
440
ps
Hold Time
T
H
(see Figure 2), GbE
360
400
440
ps
I
2
C INTERFACE DC CHARACTERISTICS
LVCMOS
Input High Voltage
V
IH
0.7 VCC
V
Input Low Voltage
V
IL
0.3
VCC
V
Input Current
V
IN
= 0.1 VCC or V
IN
= 0.9 VCC
-10.0
+10.0
A
Output Low Voltage
V
OL
, I
OL
= 3.0 mA
0.4
V
I
2
C INTERFACE TIMING
See Figure 11
SCK Clock Frequency
400
kHz
SCK Pulse Width High
t
HIGH
600
ns
SCK Pulse Width Low
t
LOW
1300
ns
Start Condition Hold Time
t
HD;STA
600
ns
Start Condition Setup Time
t
SU;STA
600
ns
Data Setup Time
t
SU;DAT
100
ns
Data Hold Time
t
HD;DAT
300
ns
SCK/SDA Rise/Fall Time
T
R
/T
F
20 + 0.1 Cb
1
300
ns
Stop Condition Setup Time
t
SU;STO
600
ns
Bus Free Time Between a Stop and a Start
t
BUF
1300
ns
REFCLK CHARACTERISTICS
Optional lock to REFCLK mode
Input Voltage Range
@ REFCLKP or REFCLKN
V
IL
0
V
V
IH
VCC
V
Minimum Differential Input Drive
100
mV p-p
Reference Frequency
10
160
MHz
Required Accuracy
100
ppm
LVTTL DC INPUT CHARACTERISTICS
Input High Voltage
V
IH
2.0
V
Input Low Voltage
V
IL
0.8
V
Input High Current
I
IH
, V
IN
= 2.4 V
5
A
Input Low Current
I
IL
, V
IN
= 0.4 V
-5
A
LVTTL DC OUTPUT CHARACTERISTICS
Output High Voltage
V
OH
, I
OH
= -2.0 mA
2.4
V
Output Low Voltage
V
OL
, I
OL
= 2.0 mA
0.4
V
1
C
b
= total capacitance of one bus line in pF. If mixed with Hs mode devices, faster fall times are allowed.
ADN2813
Rev. 0 | Page 6 of 28
ABSOLUTE MAXIMUM RATINGS
T
A
= T
MIN
to T
MAX
, VCC = V
MIN
to V
MAX
, VEE = 0 V, C
F
=
0.47 F, SLICEP = SLICEN = VEE, unless otherwise noted.
Table 4.
Parameter Rating
Supply Voltage (VCC)
4.2 V
Minimum Input Voltage (All Inputs)
VEE - 0.4 V
Maximum Input Voltage (All Inputs)
VCC + 0.4 V
Maximum Junction Temperature
125°C
Storage Temperature Range
-65°C to +150°C
Stress above those listed under Absolute Maximum Ratings may
cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL CHARACTERISTICS
Thermal Resistance
32-LFCSP, 4-layer board with exposed paddle soldered to VEE,
JA
= 28°C/W.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
ADN2813
Rev. 0 | Page 7 of 28
TIMING CHARACTERISTICS
04951-0-002
CLKOUTP
DATAOUTP/N
T
S
T
H
Figure 2. Output Timing
04951-0-032
|V
OD
|
V
OH
DIFFERENTIAL CLKOUTP/N, DATAOUTP/N
V
OS
V
OL
Figure 3. Differential Output Specifications
04951-
0-
033
SIMPLIFIED LVDS
OUTPUT STAGE
R
LOAD
100
100
5mA
5mA
V
DIFF
Figure 4. Differential Output Stage
ADN2813
Rev. 0 | Page 8 of 28
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
04951-0-004
TEST1 1
VCC 2
VREF 3
PIN 1
INDICATOR
TOP VIEW
(Not to Scale)
24 VCC
23 VEE
22 LOS
21 SDA
32 T
EST
2
20 SCK
19 SADDR5
18 VCC
17 VEE
THRADJ 9
RE
FCLKP
1
0
RE
FCLKN 11
V
CC 12
VEE 13
CF
2 14
CF
1 15
LO
L 1
6
NIN 4
PIN 5
SLICEP 6
SLICEN 7
VEE 8
31 VCC
30 VEE
29 DATAO
UTP
28 DATAO
UTN
27 SQUEL
C
H
26 CLKO
UTP
25 CLKO
UTN
ADN2813*
* THERE IS AN EXPOSED PAD ON THE BOTTOM OF
THE PACKAGE THAT MUST BE CONNECTED TO GND.
Figure 5. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
Mnemonic
Type
1
Description
1
TEST1
Connect to VCC.
2
VCC
P
Power for Limiting Amplifier, LOS.
3
VREF
AO
Internal VREF Voltage. Decouple to GND with a 0.1 F capacitor.
4
NIN
AI
Differential Data Input. CML.
5
PIN
AI
Differential Data Input. CML.
6
SLICEP
AI
Differential Slice Level Adjust Input.
7
SLICEN
AI
Differential Slice Level Adjust Input.
8
VEE
P
GND for Limiting Amplifier, LOS.
9
THRADJ
AI
LOS Threshold Setting Resistor.
10
REFCLKP
DI
Differential REFCLK Input. 10 MHz to 160 MHz.
11
REFCLKN
DI
Differential REFCLK Input. 10 MHz to 160 MHz.
12
VCC
P
VCO Power.
13 VEE
P
VCO
GND.
14
CF2
AO
Frequency Loop Capacitor.
15
CF1
AO
Frequency Loop Capacitor.
16 LOL
DO
Loss-of-Lock
Indicator. LVTTL active high.
17
VEE
P
FLL Detector GND.
18
VCC
P
FLL Detector Power.
19
SADDR5
DI
Slave Address Bit 5.
20 SCK
DI
I
2
C Clock Input.
21 SDA
DI
I
2
C Data Input.
22
LOS
DO
Loss-of-Signal Detect Output. Active high. LVTTL.
23
VEE
P
Output Buffer, I
2
C GND.
24
VCC
P
Output Buffer, I
2
C Power.
25
CLKOUTN
DO
Differential Recovered Clock Output. LVDS.
26
CLKOUTP
DO
Differential Recovered Clock Output. LVDS.
27
SQUELCH DI Disable
Clock
and
Data Outputs. Active high. LVTTL.
28
DATAOUTN
DO
Differential Recovered Data Output. LVDS.
29
DATAOUTP
DO
Differential Recovered Data Output. LVDS.
30
VEE
P
Phase Detector, Phase Shifter GND.
31
VCC
P
Phase Detector, Phase Shifter Power.
32
TEST2
Connect to VCC.
Exposed Pad
Pad
P
Connect to GND.
1
Type: P = power, AI = analog input, AO = analog output, DI = digital input, DO = digital output.
ADN2813
Rev. 0 | Page 9 of 28
TYPICAL PERFORMANCE CHARACTERISTICS
04951-0-005
16
14
12
1
10
100
R
TH
(
)
1k
10k
100k
10
8
6
4
2
TRIP POINT (mV p-p)
Figure 6. LOS Comparator Trip Point Programming
ADN2813
Rev. 0 | Page 10 of 28
I
2
C INTERFACE TIMING AND INTERNAL REGISTER DESCRIPTION
04951-0-007
1
A5
0
0
0
0
0
X
MSB = 1 SET BY
PIN 19
0 = WR
1 = RD
SLAVE ADDRESS [6...0]
R/W
CTRL.
Figure 7. Slave Address Configuration
04951-0-008
S SLAVE ADDR, LSB = 0 (WR) A(S)
A(S)
A(S)
DATA
SUB ADDR
A(S) P
DATA
Figure 8. I
2
C Write Data Transfer
04951-0-009
S
S = START BIT
P = STOP BIT
A(S) = ACKNOWLEDGE BY SLAVE
A(M) = ACKNOWLEDGE BY MASTER
A(M) = LACK OF ACKNOWLEDGE BY MASTER
S
SLAVE ADDR, LSB = 0 (WR)
SLAVE ADDR, LSB = 1 (RD)
A(S)
A(S)
SUB ADDR
A(S) DATA A(M)
DATA
P
A(M)
Figure 9. I
2
C Read Data Transfer
04951-0-010
START BIT
S
STOP BIT
P
ACK
ACK
WR
ACK
D0
D7
A0
A7
A5
A6
SLADDR[4...0]
SLAVE ADDRESS
SUB ADDRESS
DATA
SUB ADDR[6...1]
DATA[6...1]
SCK
SDA
Figure 10. I
2
C Data Transfer Timing
04951-0-011
t
BUF
SDA
S
S
SCK
t
F
t
LOW
t
R
t
F
t
HD;STA
t
HD;DAT
t
SU;DAT
t
HIGH
t
SU;STA
t
SU;STO
t
HD;STA
t
R
P
S
Figure 11. I
2
C Port Timing Diagram
ADN2813
Rev. 0 | Page 11 of 28
Table 6. Internal Register Map
1
Reg.
Name R/W Address D7
D6
D5
D4 D3
D2
D1
D0
FREQ0 R
0x0
MSB
LSB
FREQ1 R
0x1
MSB
LSB
FREQ2 R
0x2
0
MSB
LSB
RATE R 0x3
COARSE_RD[8]
MSB
Coarse
Data Rate Readback
COARSE_RD[1]
MISC R 0x4
x
x
LOS
Status
Static
LOL
LOL
Status
Data Rate
Measure
Complete
x COARSE_RD[0]
LSB
CTRLA W 0x8
F
REF
Range
Data Rate/DIV_F
REF
Ratio
Measure
Data Rate
Lock to
Reference
CTRLB W 0x9
Config.
LOL
Reset
MISC[4]
System
Reset
0
Reset
MISC[2]
0 0
0
CTRLC W 0x11
0
0
0
0
0
Config.
LOS
SQUELCH
Mode
Output Boost
1
All writeable registers default to 0x00.
Table 7. Miscellaneous Register, MISC
LOS Status
Static LOL
LOL Status
Data Rate Measurement
Complete
Coarse Rate
Readback LSB
D7 D6 D5
D4
D3
D2
D1 D0
x
x
0 = No loss of signal
0 = Waiting for next LOL
0 = Locked
0 = Measuring data rate
x
COARSE_RD[0]
1 = Loss of signal
1 = Static LOL until reset
1 = Acquiring
1 = Measurement complete
Table 8. Control Register, CTRLA
1
F
REF
Range
Data Rate/Div_F
REF
Ratio
Measure Data Rate
Lock to Reference
D7 D6
D5 D4 D3 D2
D1
D0
0
0
10 MHz to 20 MHz
0
0
0
0
1
Set to 1 to measure data rate
0 = Lock to input data
0
1
20 MHz to 40 MHz
0
0
0
1
2
1 = Lock to reference clock
1
0
40 MHz to 80 MHz
0
0
1
0
4
1 1 80
MHz
to
160
MHz
n
2
n
1 0 0 0 256
1
Where DIV_F
REF
is the divided down reference referred to the 10 MHz to 20 MHz band (see the Reference Clock (Optional) section).
Table 9. Control Register, CTRLB
Config LOL
Reset MISC[4]
System Reset
Reset MISC[2]
D7
D6
D5
D4 D3
D2 D1 D0
0 = LOL pin normal operation
1 = LOL pin is static LOL
Write a 1 followed by
0 to reset MISC[4]
Write a 1 followed by 0
to reset ADN2813
Set
to 0
Write a 1 followed by 0
to reset MISC[2]
Set
to 0
Set
to 0
Set
to 0
Table 10. Control Register, CTRLC
Config. LOS
SQUELCH Mode
Output Boost
D7 D6 D5 D4 D3 D2
D1
D0
0 = Active high LOS
0 = SQUELCH CLK and DATA
0 = Default output swing
Set to 0
Set to 0
Set to 0
Set to 0
Set to 0
1 = Active low LOS
1 = SQUELCH CLK or DATA
1 = Boost output swing
ADN2813
Rev. 0 | Page 12 of 28
TERMINOLOGY
Input Sensitivity and Input Overdrive
Sensitivity and overdrive specifications for the quantizer involve
offset voltage, gain, and noise. The relationship between the
logic output of the quantizer and the analog voltage input is
shown in Figure 12. For sufficiently large positive input voltage,
the output is always Logic 1, and similarly for negative inputs,
the output is always Logic 0. However, the transitions between
output Logic 1 and output Logic 0 are not at precisely defined
input voltage levels but occur over a range of input voltages.
Within this range of input voltages, the output may be either 1
or 0, or it may even fail to attain a valid logic state. The width of
this zone is determined by the input voltage noise of the
quantizer. The center of the zone is the quantizer input offset
voltage. Input overdrive is the magnitude of signal required to
guarantee the correct logic level with 1 × 10
-10
confidence level.
04951-0-012
NOISE
OUTPUT
INPUT (V p-p)
OFFSET
OVERDRIVE
SENSITIVITY
(2
×
OVERDRIVE)
1
0
Figure 12. Input Sensitivity and Input Overdrive
Single-Ended vs. Differential
AC coupling is typically used to drive the inputs to the
quantizer. The inputs are internally dc biased to a common-
mode potential of ~2.5 V. Driving the ADN2813 single-ended
and observing the quantizer input with an oscilloscope probe at
the point indicated in Figure 13 shows a binary signal with an
average value equal to the common-mode potential and
instantaneous values both above and below the average value. It
is convenient to measure the peak-to-peak amplitude of this
signal and call the minimum required value the quantizer
sensitivity. Referring to Figure 13, because both positive and
negative offsets need to be accommodated, the sensitivity is
twice the overdrive. The ADN2813 quantizer typically has
3.3 mV p-p sensitivity.
04951-0-013
SCOPE
PROBE
PIN
50
3k
2.5V
50
VREF
ADN2813
QUANTIZER
+
10mV p-p
VREF
Figure 13. Single-Ended Sensitivity Measurement
Driving the ADN2813 differentially (see Figure 14), sensitivity
seems to improve from observing the quantizer input with an
oscilloscope probe. This is an illusion caused by the use of a
single-ended probe. A 5 mV p-p signal appears to drive the
ADN2813 quantizer. However, the single-ended probe
measures only half the signal. The true quantizer input signal is
twice this value, because the other quantizer input is a
complementary signal to the signal being observed.
04951-0-014
SCOPE
PROBE
PIN
50
3k
2.5V
50
VREF
QUANTIZER
+
NIN
5mV p-p
VREF
5mV p-p
VREF
Figure 14. Differential Sensitivity Measurement
LOS Response Time
LOS response time is the delay between removal of the input
signal and indication of loss of signal (LOS) at the LOS output,
Pin 22. When the inputs are dc-coupled, the LOS assert time of
the ADN2813 is 500 ns typical and the deassert time is 400 ns
typical. In practice, the time constant produced by the ac
coupling at the quantizer input and the 50 on-chip input
termination determines the LOS response time.
ADN2813
Rev. 0 | Page 13 of 28
JITTER SPECIFICATIONS
The ADN2813 CDR is designed to achieve the best bit-
error-rate (BER) performance and to exceed the jitter
transfer, generation, and tolerance specifications proposed
for SONET/SDH equipment defined in the Telcordia
Technologies specification.
Jitter is the dynamic displacement of digital signal edges from
their long-term average positions, measured in unit intervals
(UI), where 1 UI = 1 bit period. Jitter on the input data can
cause dynamic phase errors on the recovered clock sampling
edge. Jitter on the recovered clock causes jitter on the
retimed data.
The following sections briefly summarize the specifications of
jitter generation, transfer, and tolerance in accordance with the
Telcordia document (GR-253-CORE, Issue 3, September 2000)
for the optical interface at the equipment level and the ADN2813
performance with respect to those specifications.
Jitter Generation
The jitter generation specification limits the amount of jitter
that can be generated by the device with no jitter and wander
applied at the input. For SONET devices, the jitter generated
must be less than 0.01 UI rms and must be less than 0.1 UI p-p.
Jitter Transfer
The jitter transfer function is the ratio of the jitter on the output
signal to the jitter applied on the input signal vs. the frequency.
This parameter measures the limited amount of the jitter on an
input signal that can be transferred to the output signal (see
Figure 15).
04951-0-015
0.1
ACCEPTABLE
RANGE
f
C
JITTER FREQUENCY (kHz)
SLOPE = 20dB/DECADE
JITTER GAIN (dB)
Figure 15. Jitter Transfer Curve
Jitter Tolerance
The jitter tolerance is defined as the peak-to-peak amplitude of
the sinusoidal jitter applied on the input signal, which causes a
1 dB power penalty. This is a stress test intended to ensure that
no additional penalty is incurred under the operating conditions
(see Figure 16).
04951-0-016
15.00
1.50
0.15
f
0
f
1
f
2
f
3
f
4
JITTER FREQUENCY (kHz)
SLOPE = 20dB/DECADE
INPUT JITTER AMPLITUDE (UI p-p)
Figure 16. SONET Jitter Tolerance Mask
ADN2813
Rev. 0 | Page 14 of 28
THEORY OF OPERATION
The ADN2813 is a delay- and phase-locked loop circuit for
clock recovery and data retiming from an NRZ encoded data
stream. The phase of the input data signal is tracked by two
separate feedback loops that share a common control voltage. A
high speed delay-locked loop path uses a voltage controlled
phase shifter to track the high frequency components of input
jitter. A separate phase control loop, comprised of the VCO,
tracks the low frequency components of input jitter. The initial
frequency of the VCO is set by yet a third loop, which compares
the VCO frequency with the input data frequency and sets the
coarse tuning voltage. The jitter tracking phase-locked loop
controls the VCO by the fine-tuning control.
The delay and phase loops together track the phase of the input
data signal. For example, when the clock lags input data, the
phase detector drives the VCO to a higher frequency and
increases the delay through the phase shifter; both of these
actions serve to reduce the phase error between the clock and
data. The faster clock picks up phase, while the delayed data
loses phase. Because the loop filter is an integrator, the static
phase error is driven to zero.
Another view of the circuit is that the phase shifter implements
the zero required for frequency compensation of a second-order
phase-locked loop, and this zero is placed in the feedback path
and, thus, does not appear in the closed-loop transfer function.
Jitter peaking in a conventional second-order phase-locked loop
is caused by the presence of this zero in the closed-loop transfer
function. Because this circuit has no zero in the closed-loop
transfer, jitter peaking is minimized.
The delay and phase loops together simultaneously provide
wideband jitter accommodation and narrow-band jitter
filtering. The linearized block diagram in Figure 17 shows that
the jitter transfer function, Z(s)/X(s), is a second-order low-pass
providing excellent filtering. Note that the jitter transfer has no
zero, unlike an ordinary second-order phase-locked loop. This
means that the main PLL loop has virtually zero jitter peaking
(see Figure 18). This makes this circuit ideal for signal regen-
erator applications where jitter peaking in a cascade of
regenerators can contribute to hazardous jitter accumulation.
The error transfer, e(s)/X(s), has the same high-pass form as an
ordinary phase-locked loop. This transfer function is free to be
optimized to give excellent wideband jitter accommodation,
because the jitter transfer function, Z(s)/X(s), provides the
narrow-band jitter filtering.
04951-0-017
X(s)
Z(s)
RECOVERED
CLOCK
e(s)
INPUT
DATA
d/sc
psh
o/s
1/n
d = PHASE DETECTOR GAIN
o = VCO GAIN
c = LOOP INTEGRATOR
psh = PHASE SHIFTER GAIN
n = DIVIDE RATIO
=
1
cn
do
s
2
+
n psh
o
s
+ 1
Z(s)
X(s)
JITTER TRANSFER FUNCTION
=
s
2
s
2
d psh
c
s
+
+
do
cn
e(s)
X(s)
TRACKING ERROR TRANSFER FUNCTION
Figure 17. ADN2813 PLL/DLL Architecture
ADN2813
Z(s)
X(s)
04951-0-018
FREQUENCY (kHz)
JITTER PEAKING
IN ORDINARY PLL
JITTER GAIN (
d
B)
o
n psh
d psh
c
Figure 18. ADN2813 Jitter Response vs. Conventional PLL
The delay and phase loops contribute to overall jitter accom-
modation. At low frequencies of input jitter on the data signal,
the integrator in the loop filter provides high gain to track large
jitter amplitudes with small phase error. In this case, the VCO is
frequency modulated, and jitter is tracked as in an ordinary
phase-locked loop. The amount of low frequency jitter that can
be tracked is a function of the VCO tuning range. A wider
tuning range gives larger accommodation of low frequency
jitter. The internal loop control voltage remains small for small
phase errors; therefore, the phase shifter remains close to the
center of its range and thus contributes little to the low
frequency jitter accommodation.
ADN2813
Rev. 0 | Page 15 of 28
At medium jitter frequencies, the gain and tuning range of the
VCO are not large enough to track input jitter. In this case, the
VCO control voltage becomes large and saturates, and the VCO
frequency dwells at one extreme of its tuning range or at the
other. The size of the VCO tuning range, therefore, has only a
small effect on the jitter accommodation. The delay-locked loop
control voltage is now larger, and therefore the phase shifter
takes on the burden of tracking the input jitter. The phase
shifter range, in UI, can be seen as a broad plateau on the jitter
tolerance curve. The phase shifter has a minimum range of 2 UI
at all data rates.
The gain of the loop integrator is small for high jitter
frequencies; therefore, larger phase differences are needed to
make the loop control voltage large enough to tune the range of
the phase shifter. Large phase errors at high jitter frequencies
cannot be tolerated. In this region, the gain of the integrator
determines the jitter accommodation. Because the gain of the
loop integrator declines linearly with frequency, jitter accom-
modation is lower with higher jitter frequency. At the highest
frequencies, the loop gain is very small, and little tuning of the
phase shifter can be expected. In this case, jitter accommodation is
determined by the eye opening of the input data, the static
phase error, and the residual loop jitter generation. The jitter
accommodation is roughly 0.5 UI in this region. The corner
frequency between the declining slope and the flat region is
the closed loop bandwidth of the delay-locked loop, which is
roughly 1.5 MHz at 1.25 Gb/s.
ADN2813
Rev. 0 | Page 16 of 28
FUNCTIONAL DESCRIPTION
FREQUENCY ACQUISITION
The ADN2813 acquires frequency from the data over a range of
data frequencies from 10 Mb/s to 1.25 Gb/s. The lock detector
circuit compares the frequency of the VCO and the frequency
of the incoming data. When these frequencies differ by more
than 1000 ppm, LOL is asserted. This initiates a frequency
acquisition cycle. The VCO frequency is reset to the bottom of
its range, which is 10 MHz. The frequency detector then
compares this VCO frequency and the incoming data frequency
and increments the VCO frequency, if necessary. Initially, the
VCO frequency is incremented in large steps to aid fast acquisi-
tion. As the VCO frequency approaches the data frequency, the
step size is reduced until the VCO frequency is within 250 ppm
of the data frequency, at which point LOL is deasserted.
Once LOL is deasserted, the frequency-locked loop is turned
off. The PLL/DLL pulls in the VCO frequency the rest of the
way until the VCO frequency equals the data frequency.
The frequency loop requires a single external capacitor between
CF1 and CF2, Pin 14 and Pin 15. A 0.47 F ± 20%, X7R ceramic
chip capacitor with < 10 nA leakage current is recommended.
Leakage current of the capacitor can be calculated by dividing
the maximum voltage across the 0.47 F capacitor, ~3 V, by the
insulation resistance of the capacitor. The insulation resistance
of the 0.47 F capacitor should be greater than 300 M.
LIMITING AMPLIFIER
The limiting amplifier has differential inputs (PIN/NIN),
which are internally terminated with 50 to an on-chip voltage
reference (VREF = 2.5 V typically). The inputs are typically
ac-coupled externally, although dc coupling is possible as long
as the input common-mode voltage remains above 2.5 V (see
Figure 27 to Figure 29 in the Applications Information section).
Input offset is factory trimmed to achieve better than 3.3 mV
typical sensitivity with minimal drift. The limiting amplifier can
be driven differentially or single-ended.
SLICE ADJUST
The quantizer slicing level can be offset by ±100 mV to mitigate
the effect of amplified spontaneous emission (ASE) noise or
duty cycle distortion by applying a differential voltage input of
up to ±0.95 V to SLICEP/SLICEN inputs. If no adjustment of
the slice level is needed, SLICEP/SLICEN should be tied to
VEE. The gain of the slice adjustment is ~0.11 V/V.
LOSS-OF-SIGNAL (LOS) DETECTOR
The receiver front-end LOS detector circuit detects when the
input signal level has fallen below a user-adjustable threshold.
The threshold is set with a single external resistor from Pin 9,
THRADJ, to VEE. The LOS comparator trip point vs. the
resistor value is illustrated in Figure 6. If the input level to the
ADN2813 drops below the programmed LOS threshold, the
output of the LOS detector, LOS Pin 22, is asserted to a Logic 1.
The LOS detector's response time is ~500 ns by design but is
dominated by the RC time constant in ac-coupled applications.
The LOS pin defaults to active high. However, by setting
Bit CTRLC[2] to 1, the LOS pin is configured as active low.
There is typically 6 dB of electrical hysteresis designed into the
LOS detector to prevent chatter on the LOS pin. If the input
level drops below the programmed LOS threshold causing the
LOS pin to assert, the LOS pin is not deasserted until the input
level has increased to 6 dB (2×) above the LOS threshold (see
Figure 19).
04951-0-019
HYSTERESIS
LOS OUTPUT
INPUT LEVEL
LOS THRESHOLD
t
INPUT VOLTAGE (V
DIFF
)
Figure 19. LOS Detector Hysteresis
The LOS detector and the SLICE level adjust can be used
simultaneously on the ADN2813. This means that any offset
added to the input signal by the SLICE adjust pins does not
affect the LOS detector's measurement of the absolute input
level.
LOCK DETECTOR OPERATION
The lock detector on the ADN2813 has three modes of
operation: normal mode, REFCLK mode, and static LOL mode.
Normal Mode
In normal mode, the ADN2813 is a continuous rate CDR that
locks onto any data rate from 10 Mb/s to 1.25 Gb/s without the
use of a reference clock as an acquisition aid. In this mode, the
lock detector monitors the frequency difference between the
VCO and the input data frequency and deasserts the loss-of-
lock signal, which appears on Pin 16, LOL, when the VCO is
within 250 ppm of the data frequency. This enables the D/PLL,
which pulls the VCO frequency in the remaining amount and
ADN2813
Rev. 0 | Page 17 of 28
acquires phase lock. Once locked, if the input frequency error
exceeds 1000 ppm (0.1%), the loss-of-lock signal is reasserted
and control returns to the frequency loop, which begins a new
frequency acquisition starting at the lowest point in the VCO
operating range, 10 MHz. The LOL pin remains asserted until
the VCO locks onto a valid input data stream to within 250
ppm frequency error. This hysteresis is shown in Figure 20.
04951-0-020
LOL
0
250
250
1000
f
VCO
ERROR
(ppm)
1000
1
Figure 20. Transfer Function of LOL
LOL Detector Operation Using a Reference Clock
In REFCLK mode, a reference clock is used as an acquisition aid
to lock the ADN2813 VCO. Lock-to-reference mode is enabled
by setting CTRLA[0] to 1. The user also needs to write to
the CTRLA[7:6] and CTRLA[5:2] bits to set the reference
frequency range and the divide ratio of the data rate with
respect to the reference frequency. For more details, see the
Reference Clock (Optional) section. In this mode, the lock
detector monitors the difference in frequency between the
divided down VCO and the divided down reference clock. The
loss-of-lock signal, which appears on Pin 16, LOL, is deasserted
when the VCO is within 250 ppm of the desired frequency. This
enables the D/PLL, which pulls the VCO frequency in the
remaining amount with respect to the input data and acquires
phase lock. Once locked, if the input frequency error exceeds
1000 ppm (0.1%), the loss-of-lock signal is reasserted and
control returns to the frequency loop, which reacquires with
respect to the reference clock. The LOL pin remains asserted
until the VCO frequency is within 250 ppm of the desired
frequency. This hysteresis is shown in Figure 20.
Static LOL Mode
The ADN2813 implements a static LOL feature, which indicates
if a loss-of-lock condition has ever occurred and remains
asserted, even if the ADN2813 regains lock, until the static LOL
bit is manually reset. The I
2
C register bit, MISC[4], is the static
LOL bit. If there is ever an occurrence of a loss-of-lock
condition, this bit is internally asserted to logic high. The
MISC[4] bit remains high even after the ADN2813 has
reacquired lock to a new data rate. This bit can be reset by
writing a 1 followed by 0 to I
2
C Register Bit CTRLB[6]. Once
reset, the MISC[4] bit remains deasserted until another loss-of-
lock condition occurs.
Writing a 1 to I
2
C Register Bit CTRLB[7] causes the LOL pin,
Pin 16, to become a static LOL indicator. In this mode, the
LOL pin mirrors the contents of the MISC[4] bit and has
the functionality described in the previous paragraph. The
CTRLB[7] bit defaults to 0. In this mode, the LOL pin operates
in the normal operating mode, that is, it is asserted only when
the ADN2813 is in acquisition mode and deasserts when the
ADN2813 has reacquired lock.
HARMONIC DETECTOR
The ADN2813 provides a harmonic detector, which detects
whether or not the input data has changed to a lower harmonic
of the data rate that the VCO is currently locked onto. For
example, if the input data instantaneously changes from OC-12,
622.08 Mb/s to an OC-3, 155.52 Mb/s bit stream, this could be
perceived as a valid OC-12 bit stream, because the OC-3 data
pattern is exactly 4× slower than the OC-12 pattern. Therefore,
if the change in data rate is instantaneous, a 101 pattern at OC-3
would be perceived by the ADN2813 as a 111100001111 pattern
at OC-12. If the change to a lower harmonic is instantaneous, a
typical CDR could remain locked at the higher data rate.
The ADN2813 implements a harmonic detector that automati-
cally identifies whether or not the input data has switched to a
lower harmonic of the data rate that the VCO is currently
locked onto. When a harmonic is identified, the LOL pin is
asserted and a new frequency acquisition is initiated. The
ADN2813 automatically locks onto the new data rate, and the
LOL pin is deasserted.
However, the harmonic detector does not detect higher
harmonics of the data rate. If the input data rate switches to a
higher harmonic of the data rate, then the VCO is currently
locked onto, the VCO loses lock, the LOL pin is asserted, and a
new frequency acquisition is initiated. The ADN2813
automatically locks onto the new data rate.
The time to detect lock to harmonic is
2
16
× (T
d
/)
where:
1/T
d
is the new data rate. For example, if the data rate is
switched from OC-12 to OC-3, then T
d
= 1/155.52 MHz.
is the data transition density. Most coding schemes seek to
ensure that = 0.5, for example, PRBS, 8B/10B.
When the ADN2813 is placed in lock-to-reference mode, the
harmonic detector is disabled.
ADN2813
Rev. 0 | Page 18 of 28
SQUELCH MODE
Two SQUELCH modes are available with the ADN2813.
SQUELCH DATAOUT and CLKOUT mode is selected when
CTRLC[1] = 0 (default mode). In this mode, when the
SQUELCH input, Pin 27, is driven to a TTL high state, both
the clock and data outputs are set to the zero state to suppress
downstream processing. If the SQUELCH function is not
required, Pin 27 should be tied to VEE.
SQUELCH DATAOUT or CLKOUT mode is selected when
CTRLC[1] is 1. In this mode, when the SQUELCH input is
driven to a high state, the DATAOUTN/DATA OUTP pins are
squelched. When the SQUELCH input is driven to a low state,
the CLKOUT pins are squelched. This is especially useful in
repeater applications, where the recovered clock may not be
needed.
I
2
C INTERFACE
The ADN2813 supports a 2-wire, I
2
C-compatible serial bus
driving multiple peripherals. Two inputs, serial data (SDA) and
serial clock (SCK), carry information between any devices
connected to the bus. Each slave device is recognized by a
unique address. The ADN2813 has two possible 7-bit slave
addresses for both read and write operations. The MSB of the
7-bit slave address is factory programmed to 1. B5 of the slave
address is set by Pin 19, SADDR5. Slave Address Bits [4:0] are
defaulted to all 0s. The slave address consists of the 7 MSBs of
an 8-bit word. The LSB of the word either sets a read or write
operation (see Figure 7). Logic 1 corresponds to a read
operation, while Logic 0 corresponds to a write operation.
To control the device on the bus, the following protocol must be
followed. First, the master initiates a data transfer by establish-
ing a start condition, defined by a high-to-low transition on
SDA while SCK remains high. This indicates that an address/
data stream follows. All peripherals respond to the start
condition and shift the next eight bits (the 7-bit address and
the R/W bit). The bits are transferred from MSB to LSB. The
peripheral that recognizes the transmitted address responds by
pulling the data line low during the ninth clock pulse. This is
known as an acknowledge bit. All other devices withdraw from
the bus at this point and maintain an idle condition. The idle
condition is where the device monitors the SDA and SCK lines
waiting for the start condition and correct transmitted address.
The R/W bit determines the direction of the data. Logic 0 on
the LSB of the first byte means that the master writes
information to the peripheral. Logic 1 on the LSB of the
first byte means that the master reads information from the
peripheral.
The ADN2813 acts as a standard slave device on the bus.
The data on the SDA pin is eight bits long, supporting the
7-bit addresses, plus the R/W bit. The ADN2813 has eight
subaddresses to enable the user-accessible internal registers
(see Table 6 through Table 10). It, therefore, interprets the first
byte as the device address and the second byte as the starting
subaddress. Auto-increment mode is supported, allowing data
to be read from or written to the starting subaddress and each
subsequent address without manually addressing the subsequent
subaddress. A data transfer is always terminated by a stop
condition. The user can also access any unique subaddress
register on a one-by-one basis without updating all registers.
Stop and start conditions can be detected at any stage of the
data transfer. If these conditions are asserted out of sequence
with normal read and write operations, they cause an immediate
jump to the idle condition. During a given SCK high period, the
user should issue one start condition, one stop condition, or a
single stop condition followed by a single start condition. If an
invalid subaddress is issued by the user, the ADN2813 does not
issue an acknowledge and returns to the idle condition. If the
user exceeds the highest subaddress while reading back in
auto-increment mode, then the highest subaddress register
contents continue to be output until the master device
issues a no acknowledge. This indicates the end of a read. In a
no acknowledge condition, the SDATA line is not pulled low
on the ninth pulse. See Figure 8 and Figure 9 for sample read
and write data transfers and Figure 10 for a more detailed
timing diagram.
REFERENCE CLOCK (OPTIONAL)
A reference clock is not required to perform clock and data
recovery with the ADN2813. However, support for an optional
reference clock is provided. The reference clock can be driven
differentially or single-ended. If the reference clock is not being
used, then REFCLKP should be tied to VCC, and REFCLKN
can be left floating or tied to VEE (the inputs are internally
terminated to VCC/2). See Figure 21 through Figure 23 for
sample configurations.
The REFCLK input buffer accepts any differential signal with a
peak-to-peak differential amplitude of greater than 100 mV (for
example, LVPECL or LVDS) or a standard single-ended, low
voltage TTL input, providing maximum system flexibility.
Phase noise and duty cycle of the reference clock are not
critical, and 100 ppm accuracy is sufficient.
ADN2813
Rev. 0 | Page 19 of 28
04951-0-021
100k
VCC/2
100k
ADN2813
REFCLKP
10
11
REFCLKN
BUFFER
Figure 21. Differential REFCLK Configuration
04951-0-022
100k
VCC/2
100k
ADN2813
REFCLKP
OUT
REFCLKN
BUFFER
VCC
CLK
OSC
Figure 22. Single-Ended REFCLK Configuration
04951-0-023
100k
VCC/2
100k
ADN2813
REFCLKP
10
11
NC
REFCLKN
BUFFER
VCC
Figure 23. No REFCLK Configuration
The two uses of the reference clock are mutually exclusive. The
reference clock can be used either as an acquisition aid for the
ADN2813 to lock onto data or to measure the frequency of the
incoming data to within 0.01%. (There is the capability to
measure the data rate to approximately ±10% without the use of
a reference clock.) The modes are mutually exclusive because, in
the first use, the user knows exactly what the data rate is and
wants to force the part to lock onto only that data rate; in the
second use, the user does not know what the data rate is and
wants to measure it.
Lock-to-reference mode is enabled by writing a 1 to I
2
C Register
Bit CTRLA[0]. Fine data rate readback mode is enabled by
writing a 1 to I
2
C Register Bit CTRLA[1]. Writing a 1 to both
of these bits at the same time causes an indeterminate state and
is not supported.
Using the Reference Clock to Lock onto Data
In this mode, the ADN2813 locks onto a frequency derived
from the reference clock according to
Data Rate/2
CTRLA[5:2]
= REFCLK/2
CTRLA[7:6]
The user must know exactly what the data rate is and provide a
reference clock that is a function of this rate. The ADN2813 can
still be used as a continuous rate device in this configuration,
provided that the user has the ability to provide a reference clock
that has a variable frequency (see Application Note AN-632).
The reference clock can be anywhere between 10 MHz and
160 MHz. By default, the ADN2813 expects a reference clock of
between 10 MHz and 20 MHz. If it is between 20 MHz and
40 MHz, 40 MHz and 80 MHz, or 80 MHz and 160 MHz, the
user needs to configure the ADN2813 to use the correct
reference frequency range by setting two bits of the CTRLA
register, CTRLA[7:6].
Table 11. CTRLA Settings
CTRLA[7:6] Range
(MHz) CTRLA[5:2] Ratio
00
10 to 20
0000
1
01
20 to 40
0001
2
10
40 to 80
n
2
n
11
80 to 160
1000
256
The user can specify a fixed integer multiple of the reference
clock to lock onto using CTRLA[5:2], where CTRLA should be
set to the data rate/DIV_F
REF
, where DIV_F
REF
represents the
divided-down reference referred to the 10 MHz to 20 MHz
band. For example, if the reference clock frequency is
38.88 MHz and the input data rate is 622.08 Mb/s, CTRLA[7:6]
is set to [01] to give a divided-down reference clock of
19.44 MHz. CTRLA[5:2] is set to [0101], that is, 5, because
622.08 Mb/s/19.44 MHz = 2
5
In this mode, if the ADN2813 loses lock for any reason, it relocks
onto the reference clock and continues to output a stable clock.
While the ADN2813 is operating in lock-to-reference mode, if
the user ever changes the reference frequency, the F
REF
range
(CTRLA[7:6]) or the F
REF
ratio (CTRLA[5:2]), this must be
followed by writing a 0 to 1 transition into the CTRLA[0] bit to
initiate a new lock-to-reference command.
Using the Reference Clock to Measure Data Frequency
The user can also provide a reference clock to measure the
recovered data frequency. In this case, the user provides a
reference clock, and the ADN2813 compares the frequency of
the incoming data to the incoming reference clock and returns a
ratio of the two frequencies to 0.01% (100 ppm). The accuracy
error of the reference clock is added to the accuracy of the
ADN2813 data rate measurement. For example, if a 100 ppm
accuracy reference clock is used, the total accuracy of the
measurement is within 200 ppm.
ADN2813
Rev. 0 | Page 20 of 28
For example, if the reference clock frequency is 32 MHz,
SEL_RATE = 1, since the CTRLA[7:6] setting is [01], because
the reference frequency falls into the 20 MHz to 40 MHz range.
Assume for this example that the input data rate is 1.25 Gb/s
(GbE). After following Step 1 through Step 4, the value that is
read back on FREQ[22:0] = 0x138800, which is equal to
1.28 × 10
6
. Plugging this value into the equation yields
The reference clock can range from 10 MHz and 160 MHz.
The ADN2813 expects a reference clock between 10 MHz
and 20 MHz by default. If it is between 20 MHz and 40 MHz,
40 MHz and 80 MHz, or 80 MHz and 160 MHz, the user needs
to configure the ADN2813 to use the correct reference
frequency range by setting two bits of the CTRLA register,
CTRLA[7:6]. Using the reference clock to determine the
frequency of the incoming data does not affect the manner in
which the part locks onto data. In this mode, the reference clock
is used only to determine the frequency of the data. For this
reason, the user does not need to know the data rate to use the
reference clock in this manner.
128e6 × 32e6/2
(14 + 1)
= 1.25 Gb/s
If subsequent frequency measurements are required, CTRLA[1]
should remain set to 1. It does not need to be reset. The
measurement process is reset by writing a 1 followed by a 0 to
CTRLB[3]. This initiates a new data rate measurement. Follow
Step 2 through Step 4 to read back the new data rate.
Prior to reading back the data rate using the reference clock, the
CTRLA[7:6] bits must be set to the appropriate frequency range
with respect to the reference clock being used. A fine data rate
readback is then executed as follows:
Note that a data rate readback is valid only if LOL is low. If LOL
is high, the data rate readback is invalid.
Additional Features Available via the I
2
C Interface
Coarse Data Rate Readback
1.
Write a 1 to CTRLA[1]. This enables the fine data rate
measurement capability of the ADN2813. This bit is level
sensitive and does not need to be reset to perform
subsequent frequency measurements.
The data rate can be read back over the I
2
C interface to
approximately ±10% without the need of an external reference
clock. A 9-bit register, COARSE_RD[8:0], can be read back
when LOL is deasserted. The eight MSBs of this register are the
contents of the RATE[7:0] register. The LSB of the
COARSE_RD register is Bit MISC[0].
2.
Reset MISC[2] by writing a 1 followed by a 0 to CTRLB[3].
This initiates a new data rate measurement.
3.
Read back MISC[2]. If it is 0, the measurement is not
complete. If it is 1, the measurement is complete and the
data rate can be read back on FREQ[22:0]. The time for a
data rate measurement is typically 80 ms.
Table 13 provides coarse data rate readback to within ±10%.
LOS Configuration
The LOS detector output, Pin 22, can be configured to be either
active high or active low. If CTRLC[2] is set to Logic 0 (default),
the LOS pin is active high when a loss-of-signal condition is
detected. Writing a 1 to CTRLC[2] configures the LOS pin to be
active low when a loss-of-signal condition is detected.
4.
Read back the data rate from FREQ2[6:0], FREQ1[7:0],
and FREQ0[7:0].
The data rate can be determined by
[
]
(
)
)
_
(
/
..
RATE
SEL
REFCLK
DATARATE
f
FREQ
f
+
×
=
14
2
0
22
System Reset
where:
A frequency acquisition can be initiated by writing a 1 followed
by a 0 to the I
2
C Register Bit CTRLB[5]. This initiates a new
frequency acquisition while keeping the ADN2813 in the
operating mode that it was previously programmed to in
Registers CTRL[A], CTRL[B], and CTRL[C].
FREQ[22:0] is the reading from FREQ2[6:0] MSByte,
FREQ1[7:0], and FREQ0[7:0] LSByte (see Table 12).
f
DATARATE
is the data rate (Mb/s).
f
REFCLK
is the REFCLK frequency (MHz).
SEL_RATE is the setting from CTRLA[7:6].
Table 12.
D22 D21...D17
D16 D15 D14...D9
D8 D7 D6...D1
D0
FREQ2[6:0] FREQ1[7:0]
FREQ0[7:0]
ADN2813
Rev. 0 | Page 21 of 28
APPLICATIONS INFORMATION
PCB DESIGN GUIDELINES
Proper RF PCB design techniques must be used for optimal
performance.
Power Supply Connections and Ground Planes
Use of one low impedance ground plane is recommended. The
VEE pins should be soldered directly to the ground plane to
reduce series inductance. If the ground plane is an internal
plane and connections to the ground plane are made through
vias, multiple vias can be used in parallel to reduce the series
inductance, especially on Pin 23, which is the ground return for
the output buffers. The exposed pad should be connected to the
GND plane using plugged vias so that solder does not leak
through the vias during reflow.
Use of a 22 F electrolytic capacitor between VCC and VEE is
recommended at the location where the 3.3 V supply enters the
PCB. When using 0.1 F and 1 nF ceramic chip capacitors, they
should be placed between the IC power supply VCC and VEE,
as close as possible to the ADN2813 VCC pins.
If connections to the supply and ground are made through
vias, the use of multiple vias in parallel helps to reduce series
inductance, especially on Pin 24, which supplies power to the
high speed CLKOUTP/CLKOUTN and DATAOUTP/
DATAOUTN output buffers. Refer to Figure 24 for the
recommended connections.
By using adjacent power supply and GND planes, excellent high
frequency decoupling can be realized by using close spacing
between the planes. This capacitance is given by
( )
pF
0.88
r
A/d
C
PLANE
=
where:
r
is the dielectric constant of the PCB material.
A is the area of the overlap of power and GND planes (cm
2
).
d is the separation between planes (mm).
For FR-4,
r
= 4.4 mm and 0.25 mm spacing, C ~15 pF/cm
2
.
50
TRANSMISSION LINES
DATAOUTP
DATAOUTN
CLKOUTP
CLKOUTN
0.1
F
22
F
1nF
0.1
F
0.1
F
0.1
F
0.1
F
0.47
F ±20%
>300M
INSULATION RESISTANCE
1nF
1nF
1nF
0.1
F
1nF
+
VCC
50
50
C
IN
TIA
VCC
R
TH
VCC
NC
C
C
I
2
C CONTROLLER
I
2
C CONTROLLER
VCC
VCC
04951-
0-
031
1
TEST1
2
VCC
3
VREF
4
NIN
5
PIN
6
SLICEP
7
SLICEN
8
VEE
24
VCC
23
VEE
22
LOS
21
SDA
20
SCK
19
SADDR5
18
VCC
17
VEE
9
T
H
R
A
D
J
1
0
R
E
F
C
L
K
P
1
1
R
E
F
C
L
K
N
1
2
V
C
C
1
3
V
E
E
1
4
C
F
2
1
5
C
F
1
1
6
L
O
L
3
2
T
E
S
T
2
3
1
V
C
C
3
0
V
E
E
2
9
D
A
T
A
O
U
T
P
2
8
D
A
T
A
O
U
T
N
2
7
S
Q
U
E
L
C
H
2
6
C
L
K
O
U
T
P
2
5
C
L
K
O
U
T
N
EXPOSED PAD
TIED OFF TO
VEE PLANE
WITH VIAS
Figure 24. Typical ADN2813 Applications Circuit
ADN2813
Rev. 0 | Page 22 of 28
Transmission Lines
Use of 50 transmission lines is required for all high frequency
input and output signals to minimize reflections: PIN, NIN,
CLKOUTP, CLKOUTN, DATAOUTP, and DATAOUTN (also
REFCLKP and REFCLKN, if a high frequency reference clock is
used, such as 155 MHz). It is also necessary for the PIN/NIN
input traces to be matched in length, and the CLKOUTP/
CLKOUTN and DATAOUTP/DATAOUTN output traces to be
matched in length to avoid skew between the differential traces.
The high speed inputs, PIN and NIN, are internally terminated
with 50 to an internal reference voltage (see Figure 25).
A 0.1 F is recommended between VREF, Pin 3, and GND to
provide an ac ground for the inputs.
As with any high speed, mixed-signal design, take care to keep
all high speed digital traces away from sensitive analog nodes.
04951-
0-
026
C
IN
C
IN
50
0.1
F
50
3k
NIN
PIN
ADN2813
2.5V
VREF
50
50
TIA
VCC
Figure 25. ADN2813 AC-Coupled Input Configuration
Soldering Guidelines for Lead Frame Chip Scale Package
The lands on the 32-lead LFCSP are rectangular. The printed
circuit board (PCB) pad for these should be 0.1 mm longer than
the package land length and 0.05 mm wider than the package
land width. The land should be centered on the pad. This
ensures that the solder joint size is maximized. The bottom of
the chip scale package has a central exposed pad. The pad on
the PCB should be at least as large as this exposed pad. The user
must connect the exposed pad to VEE using plugged vias so
that solder does not leak through the vias during reflow. This
ensures a solid connection from the exposed pad to VEE.
Choosing AC Coupling Capacitors
AC coupling capacitors at the input (PIN, NIN) and output
(DATAOUTP, DATAOUTN) of the ADN2813 must be chosen
such that the device works properly over the full range of data
rates used in the application. When choosing the capacitors, the
time constant formed with the two 50 resistors in the signal
path must be considered. When a large number of consecutive
identical digits (CIDs) are applied, the capacitor voltage can
droop due to baseline wander (see Figure 26), causing pattern-
dependent jitter (PDJ).
The user must determine how much droop is tolerable and
choose an ac coupling capacitor based on that amount of droop.
The amount of PDJ can then be approximated based on the
capacitor selection. The actual capacitor value selection can
require some trade-offs between droop and PDJ.
For example, assuming 2% droop can be tolerated, then the
maximum differential droop is 4%. Normalizing to V p-p:
Droop = V = 0.04 V = 0.5 V p-p (1 - e
t/
); therefore, = 12t
where:
is the RC time constant (C is the ac coupling capacitor,
R = 100 seen by C).
t is the total discharge time, which is equal to nT.
n is the number of CIDs.
T is the bit period.
The capacitor value can then be calculated by combining the
equations for and t:
C = 12nT/R
Once the capacitor value is selected, the PDJ can be
approximated as
PDJ
pspp
= 0.5t
r
(1 - e
(-nT/RC)
)/0.6
where:
PDJ
pspp
is the amount of pattern-dependent jitter allowed;
< 0.01 UI p-p typical.
t
r
is the rise time, which is equal to 0.22/BW, where BW ~ 0.7
(bit rate).
Note that this expression for t
r
is accurate only for the inputs.
The output rise time for the ADN2813 is ~100 ps regardless of
data rate.
ADN2813
Rev. 0 | Page 23 of 28
04951-
0-
027
50
50
PIN
V
REF
NIN
C
IN
C
OUT
C
OUT
V1
C
IN
V1b
V2
V2b
TIA
LIMAMP
CDR
+
VCC
DATAOUTP
DATAOUTN
1
V1
V1b
V2
V2b
V
DIFF
2
3
4
VREF
VTH
ADN2813
V
DIFF
= V2V2b
VTH = ADN2813 QUANTIZER THRESHOLD
NOTES:
1. DURING DATA PATTERNS WITH HIGH TRANSITION DENSITY, DIFFERENTIAL DC VOLTAGE AT V1 AND V2 IS ZERO.
2. WHEN THE OUTPUT OF THE TIA GOES TO CID, V1 AND V1b ARE DRIVEN TO DIFFERENT DC LEVELS. V2 AND V2b DISCHARGE TO THE
VREF LEVEL, WHICH EFFECTIVELY INTRODUCES A DIFFERENTIAL DC OFFSET ACROSS THE AC COUPLING CAPACITORS.
3. WHEN THE BURST OF DATA STARTS AGAIN, THE DIFFERENTIAL DC OFFSET ACROSS THE AC COUPLING CAPACITORS IS APPLIED TO
THE INPUT LEVELS CAUSING A DC SHIFT IN THE DIFFERENTIAL INPUT. THIS SHIFT IS LARGE ENOUGH SUCH THAT ONE OF THE STATES,
EITHER HIGH OR LOW DEPENDING ON THE LEVELS OF V1 AND V1b WHEN THE TIA WENT TO CID, IS CANCELED OUT. THE QUANTIZER
DOES NOT RECOGNIZE THIS AS A VALID STATE.
4. THE DC OFFSET SLOWLY DISCHARGES UNTIL THE DIFFERENTIAL INPUT VOLTAGE EXCEEDS THE SENSITIVITY OF THE ADN2813. THE
QUANTIZER CAN RECOGNIZE BOTH HIGH AND LOW STATES AT THIS POINT.
Figure 26. Example of Baseline Wander
DC-COUPLED APPLICATION
The inputs to the ADN2813 can also be dc-coupled. This may
be necessary in burst mode applications, where there are long
periods of CIDs, and baseline wander cannot be tolerated. If the
inputs to the ADN2813 are dc-coupled, care must be taken not
to violate the input range and common-mode level require-
ments of the ADN2813 (see Figure 27 through Figure 29). If dc
coupling is required, and the output levels of the TIA do not
adhere to the levels shown in Figure 28, then level shifting
and/or an attenuator must be between the TIA outputs and the
ADN2813 inputs.
04951-
0-
028
50
0.1
F
50
3k
NIN
PIN
ADN2813
2.5V
VREF
50
50
TIA
VCC
Figure 27. DC-Coupled Application
04951-0-029
PIN
INPUT (V)
V p-p = PIN NIN = 2
×
V
SE
= 10mV AT SENSITIVITY
V
SE
= 5mV MIN
V
CM
= 2.3V MIN
(DC-COUPLED)
NIN
Figure 28. Minimum Allowed DC-Coupled Input Levels
04951-0-030
PIN
INPUT (V)
V p-p = PIN NIN = 2
×
V
SE
= 2.0V MAX
V
SE
= 1.0V MAX
V
CM
= 2.3V
(DC-COUPLED)
NIN
Figure 29. Maximum Allowed DC-Coupled Input Levels
ADN2813
Rev. 0 | Page 24 of 28
COARSE DATA RATE READBACK LOOK-UP TABLE
Code is the 9-bit value read back from COARSE_RD[8:0].
Table 13. Look-Up Table
Code F
MID
0 5.3745e+06
1 5.3741e+06
2 5.4793e+06
3 5.5912e+06
4 5.7111e+06
5 5.8391e+06
6 5.9760e+06
7 6.1215e+06
8 6.2780e+06
9 6.4565e+06
10 6.6391e+06
11 6.8372e+06
12 7.0520e+06
13 7.2868e+06
14 7.5424e+06
15 7.8220e+06
16 7.6663e+06
17 7.6659e+06
18 7.8217e+06
19 7.9880e+06
20 8.1667e+06
21 8.3570e+06
22 8.5616e+06
23 8.7805e+06
24 9.0166e+06
25 9.2849e+06
26 9.5608e+06
27 9.8591e+06
28 1.0183e+07
29 1.0535e+07
30 1.0918e+07
31 1.1332e+07
32 1.0749e+07
33 1.0748e+07
34 1.0959e+07
35 1.1182e+07
36 1.1422e+07
37 1.1678e+07
38 1.1952e+07
39 1.2243e+07
40 1.2556e+07
41 1.2913e+07
42 1.3278e+07
43 1.3674e+07
44 1.4104e+07
45 1.4574e+07
46 1.5085e+07
47 1.5644e+07
Code F
MID
48 1.5333e+07
49 1.5332e+07
50 1.5643e+07
51 1.5976e+07
52 1.6333e+07
53 1.6714e+07
54 1.7123e+07
55 1.7561e+07
56 1.8033e+07
57 1.8570e+07
58 1.9122e+07
59 1.9718e+07
60 2.0367e+07
61 2.1070e+07
62 2.1835e+07
63 2.2664e+07
64 2.1498e+07
65 2.1496e+07
66 2.1917e+07
67 2.2365e+07
68 2.2844e+07
69 2.3357e+07
70 2.3904e+07
71 2.4486e+07
72 2.5112e+07
73 2.5826e+07
74 2.6556e+07
75 2.7349e+07
76 2.8208e+07
77 2.9147e+07
78 3.0170e+07
79 3.1288e+07
80 3.0665e+07
81 3.0664e+07
82 3.1287e+07
83 3.1952e+07
84 3.2667e+07
85 3.3428e+07
86 3.4246e+07
87 3.5122e+07
88 3.6066e+07
89 3.7140e+07
90 3.8243e+07
91 3.9436e+07
92 4.0733e+07
93 4.2140e+07
94 4.3671e+07
95 4.5328e+07
Code F
MID
96 4.2996e+07
97 4.2993e+07
98 4.3834e+07
99 4.4729e+07
100 4.5688e+07
101 4.6713e+07
102 4.7808e+07
103 4.8972e+07
104 5.0224e+07
105 5.1652e+07
106 5.3113e+07
107 5.4698e+07
108 5.6416e+07
109 5.8295e+07
110 6.0339e+07
111 6.2576e+07
112 6.1331e+07
113 6.1328e+07
114 6.2574e+07
115 6.3904e+07
116 6.5334e+07
117 6.6856e+07
118 6.8493e+07
119 7.0244e+07
120 7.2133e+07
121 7.4279e+07
122 7.6486e+07
123 7.8872e+07
124 8.1467e+07
125 8.4279e+07
126 8.7341e+07
127 9.0657e+07
128 8.5991e+07
129 8.5986e+07
130 8.7668e+07
131 8.9458e+07
132 9.1377e+07
133 9.3426e+07
134 9.5616e+07
135 9.7944e+07
136 1.0045e+08
137 1.0330e+08
138 1.0623e+08
139 1.0940e+08
140 1.1283e+08
141 1.1659e+08
142 1.2068e+08
143 1.2515e+08
Code F
MID
144 1.2266e+08
145 1.2266e+08
146 1.2515e+08
147 1.2781e+08
148 1.3067e+08
149 1.3371e+08
150 1.3699e+08
151 1.4049e+08
152 1.4427e+08
153 1.4856e+08
154 1.5297e+08
155 1.5774e+08
156 1.6293e+08
157 1.6856e+08
158 1.7468e+08
159 1.8131e+08
160 1.7198e+08
161 1.7197e+08
162 1.7534e+08
163 1.7892e+08
164 1.8275e+08
165 1.8685e+08
166 1.9123e+08
167 1.9589e+08
168 2.0089e+08
169 2.0661e+08
170 2.1245e+08
171 2.1879e+08
172 2.2566e+08
173 2.3318e+08
174 2.4136e+08
175 2.5030e+08
176 2.4532e+08
177 2.4531e+08
178 2.5029e+08
179 2.5562e+08
180 2.6134e+08
181 2.6742e+08
182 2.7397e+08
183 2.8098e+08
184 2.8853e+08
185 2.9712e+08
186 3.0594e+08
187 3.1549e+08
188 3.2587e+08
189 3.3712e+08
190 3.4936e+08
191 3.6263e+08
ADN2813
Rev. 0 | Page 25 of 28
Code F
MID
192 3.4397e+08
193 3.4394e+08
194 3.5067e+08
195 3.5783e+08
196 3.6551e+08
197 3.7370e+08
198 3.8247e+08
199 3.9177e+08
200 4.0179e+08
201 4.1322e+08
202 4.2490e+08
203 4.3758e+08
204 4.5133e+08
205 4.6636e+08
206 4.8272e+08
207 5.0061e+08
Code F
MID
208 4.9064e+08
209 4.9062e+08
210 5.0059e+08
211 5.1123e+08
212 5.2267e+08
213 5.3485e+08
214 5.4794e+08
215 5.6195e+08
216 5.7706e+08
217 5.9423e+08
218 6.1189e+08
219 6.3098e+08
220 6.5173e+08
221 6.7423e+08
222 6.9873e+08
223 7.2525e+08
Code F
MID
224 6.8793e+08
225 6.8789e+08
226 7.0135e+08
227 7.1567e+08
228 7.3102e+08
229 7.4741e+08
230 7.6493e+08
231 7.8355e+08
232 8.0358e+08
233 8.2643e+08
234 8.4981e+08
235 8.7516e+08
236 9.0266e+08
237 9.3272e+08
238 9.6543e+08
239 1.0012e+09
Code F
MID
240 9.8129e+08
241 9.8124e+08
242 1.0012e+09
243 1.0225e+09
244 1.0453e+09
245 1.0697e+09
246 1.0959e+09
247 1.1239e+09
248 1.1541e+09
249 1.1885e+09
250 1.2238e+09
251 1.2620e+09
252 1.3035e+09
253 1.3485e+09
254 1.3975e+09
255 1.4505e+09
ADN2813
Rev. 0 | Page 26 of 28
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2
0.30
0.23
0.18
0.20 REF
0.80 MAX
0.65 TYP
0.05 MAX
0.02 NOM
12° MAX
1.00
0.85
0.80
SEATING
PLANE
COPLANARITY
0.08
1
32
8
9
25
24
16
17
0.50
0.40
0.30
3.50 REF
0.50
BSC
PIN 1
INDICATOR
TOP
VIEW
5.00
BSC SQ
4.75
BSC SQ
3.45
3.30 SQ
3.15
PIN 1
INDICATOR
0.60 MAX
0.60 MAX
0.25 MIN
EXPOSED
PAD
(BOTTOM VIEW)
Figure 30. 32-Lead Frame Chip Scale Package [LFCSP_VQ]
5 mm × 5 mm Body, Very Thin Quad
(CP-32-3)
Dimensions shown in millimeters
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
ADN2813ACPZ
1
-40°C to 85°C
32-Lead LFCSP_VQ
CP-32-3
ADN2813ACPZ-500RL7
1
-40°C to 85°C
32-Lead LFCSP_VQ, Tape-Reel, 500 Pieces
CP-32-3
ADN2813ACPZ-RL7
1
-40°C to 85°C
32-Lead LFCSP_VQ, Tape-Reel, 1,500 Pieces
CP-32-3
EVAL-ADN2813EB
Evaluation
Board
1
Z = Pb-free part.
ADN2813
Rev. 0 | Page 27 of 28
NOTES
ADN2813
Rev. 0 | Page 28 of 28
T
NOTES
Purchase of licensed I
2
C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I
2
C
Patent Rights to use these components in an I
2
C system, provided that the system conforms to the I
2
C Standard Specification as defined by Philips.
© 2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D0495109/05(0)
TTT
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