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Part Number ADD8709

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18-Channel Gamma Buffer
with Regulator
ADD8709
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703
© 2004 Analog Devices, Inc. All rights reserved.
FEATURES
Integrated voltage regulator
Upper/lower buffers swing to V
DD
/GND
Single-supply operation: 7.5 V to 16.5 V
Continuous current drive: 15 mA
High peak output current: 150 mA
Low offset voltage: 15 mV max
Output voltage stable under transient load conditions
APPLICATIONS
TFT LCD monitor panels
TFT LCD TV panels
GENERAL DESCRIPTION
The ADD8709 is an 18-channel gamma reference for use in
high-resolution TFT LCD monitor and TV panels. The output
buffers feature low offset voltage and high current drive under
transient load conditions to provide a more accurate and stable
gamma curve. Two channels swing to V
DD
and two channels
swing to GND, increasing the overall range of the curve. An
on-board voltage regulator is available for external applications.
Here again, external component costs are reduced and the
quality of the gray scale is increased.
The ADD8709 is specified over the temperature range of
­40°C to +100°C and comes in a robust, low profile quad
flat package.
FUNCTIONAL BLOCK DIAGRAM
18
18
V
REG
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
04715-
0
-
001
Figure 1. 48-Lead LQFP
ADD8709
Rev. 0 | Page 2 of 16
TABLE OF CONTENTS
Electrical Characteristics ................................................................. 3
Absolute Maximum Ratings............................................................ 4
Pin Configuration and Function Descriptions............................. 5
Typical Applications Circuit............................................................ 7
Typical Performance Characteristics ............................................. 8
Application Notes ........................................................................... 12
Maximum Power Dissipation ................................................... 12
Operating Temperature Range ................................................. 12
Outline Dimensions ....................................................................... 13
Ordering Guide........................................................................... 14
REVISION HISTORY
7/04--Revision 0: Initial Version
ADD8709
Rev. 0 | Page 3 of 16
ELECTRICAL CHARACTERISTICS
7.5 V V
DD
16 V, T
A
@ 25°C, unless otherwise noted.
Table 1.
Parameter Symbol
Conditions
Min
Typ
Max
Unit
ALL DEVICES
POWER SUPPLY
Supply Voltage
V
S
7.5
16
V
Supply Current
I
SYS
No load
10.5
15
mA
­20°C T
A
+105°C
17
mA
VOLTAGE REGULATOR
Dropout Voltage
V
DO
I
L
= 100 µA
100
150
mV
I
L
= 5 mA
310
350
mV
Line Regulation
REG
LINE
V
IN
= 8.5 V to 16.5 V, V
OUT
= 8 V
0.01
0.20
%/V
Load Regulation
REG
LOAD
I
O
= 100 µA to 10 mA
0.02
0.10
%/mA
Load Current
I
O
5
mA
Thermal Regulation
REG
THERMAL
0.005
%/W
GAMMA BUFFERS
POWER SUPPLY
Power Supply Rejection Ratio
PSRR
V
DD
= 7 V to 17 V, ­20°C T
A
+105°C
68
90
dB
INPUT CHARACTERISTICS
Offset Voltage
V
OS
5
15
mV
Offset Voltage Drift
V
OS
/T
­20°C T
A
+105°C
20
µV/°C
Input Bias Current
I
B
0.5
1.1
µA
­20°C T
A
+105°C
1.5
µA
Input Voltage Range
0
V
DD
V
Input Impedance
Z
IN
400
k
Input Capacitance
C
IN
1
pF
OUTPUT CHARACTERISTICS
Output Performance (V1, V8, V9, V18)
V
OUT
1
I
L
= 20 mA, V
DD
= 16 V
15
mV
Output Performance (V2 to V7, V10 to V17)
V
OUT
1
I
L
= 5 mA, V
DD
= 16 V
5
mV
DYNAMIC PERFORMANCE
Slew Rate
SR
R
L
= 10 k, C
L
= 200 pF
4
6
V/µs
Bandwidth
BW
­3 dB, R
L
= 10 k, C
L
= 200 pF
4.5
MHz
Settling Time to 0.1%
t
S
1 V, R
L
= 10 k, C
L
= 200 pF
1.1
µs
Phase Margin
o
R
L
= 10 k, C
L
= 200 pF
55
Degrees
1
V
OUT
is the shift from the desired output voltage under the specified current load.





ADD8709
Rev. 0 | Page 4 of 16
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
Supply Voltage (V
DD
) 18
V
Input Voltage
­0.5 V to V
DD
Storage Temperature Range
­65°C to +150°C
Operating Temperature Range
1
-40°C to +100°C
Junction Temperature Range
­65°C to +150°C
Lead Temperature Range (Soldering, 60 sec)
300°C
ESD Tolerance (HBM)
±2000 V
ESD Tolerance (MM)
±150 V
Table 3. Package Characteristics
Package Type
JA
Unit
LQFP (ST)
74.57
°C/W
1
See
section.
Application Notes
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may
affect device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
ADD8709
Rev. 0 | Page 5 of 16
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
04715-0-002
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
V
OUT
10
V
OUT
9
V
OUT
8
V
OUT
7
V
DD
GND
V
OUT
6
V
OUT
5
V
OUT
4
V
OUT
3
V
OUT
2
V
OUT
1
V
IN
10
V
IN
9
V
IN
8
V
IN
7
V
IN
6
V
IN
5
V
IN
4
V
IN
3
V
IN
2
V
IN
1
GND
V
DD
V
DD
GND
V
OUT
1
8
V
OUT
1
7
V
OUT
1
6
V
OUT
1
5
V
OUT
1
4
V
OUT
1
3
V
DD
GND
V
OUT
1
2
V
OUT
11
1
2
3
4
5
6
7
8
9
10
11
12
REG
FB
GND
V
DD
REG
OUT
V
IN
18
V
IN
17
V
IN
16
V
IN
15
V
IN
14
V
IN
13
V
IN
12
V
IN
11
ADD8709
TOP VIEW
(Not to Scale)
PIN 1
IDENTIFIER
Figure 2. 48-Lead Low Profile Quad Flat Package (ST-48)
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
Name
Description
1 REG
FB
Regulator Feedback
Compares a percentage of the regulator output to the internal voltage reference. Internal
resistors are used to program the desired regulator output voltage.
2
GND
Ground
Ground. Nominally 0 V.
3 V
DD
Supply
Supply voltage or source voltage. Nominally 16 V.
4 REG
OUT
Regulator Output
Provides a regulated output voltage for use as a reference for additional external gamma
channels.
5 V
IN
18
6 V
IN
17
7 V
IN
16
8 V
IN
15
9 V
IN
14
10 V
IN
13
11 V
IN
12
12 V
IN
11
13 V
IN
10
14 V
IN
9
15 V
IN
8
16 V
IN
7
17 V
IN
6
18 V
IN
5
19 V
IN
4
20 V
IN
3
21 V
IN
2
22 V
IN
1
Input Buffer
input.
23
GND
Ground
Ground. Nominally 0 V.
24 V
DD
Supply
Supply voltage. Nominally 16 V.
25 V
OUT
1
26 V
OUT
2
Output
Buffer output. Designed to have higher sink than source capability.
ADD8709
Rev. 0 | Page 6 of 16
Pin No.
Mnemonic
Name
Description
27 V
OUT
3
28 V
OUT
4
29 V
OUT
5
30 V
OUT
6
Output Buffer
output.
31
GND
Ground
Ground. Nominally 0 V.
32 V
DD
Supply
Supply voltage. Nominally 16 V.
33 V
OUT
7
34 V
OUT
8
35 V
OUT
9
36 V
OUT
10
37 V
OUT
11
38 V
OUT
12
Output Buffer
output.
39
GND
Ground
Ground. Nominally 0 V.
40 V
DD
Supply
Supply voltage. Nominally 16 V.
41 V
OUT
13
42 V
OUT
14
43 V
OUT
15
44 V
OUT
16
Output Buffer
output.
45 V
OUT
17
46 V
OUT
18
Output
Buffer output. Designed to have higher source than sink capability.
47
GND
Ground
Ground. Nominally 0 V.
48 V
DD
Supply
Supply voltage. Nominally 16 V.
ADD8709
Rev. 0 | Page 7 of 16
TYPICAL APPLICATIONS CIRCUIT
04715-0-004
18
GAMMA 18
V
OUT
18
REG
IN
17
GAMMA 17
V
OUT
17
16
GAMMA 16
V
OUT
16
15
GAMMA 15
V
OUT
15
4
GAMMA 4
V
OUT
4
3
GAMMA 3
V
OUT
3
2
GAMMA 2
V
OUT
2
1
GAMMA 1
V
OUT
1
V
IN
1
COLUMN DRIVER
GAMMA BUFFERS
*EXTERNAL RESISTORS
TO SET GAMMA
VOLTAGES
ADD8709
GND
VOLTAGE
REGULATOR
V
DD
V
FB
V
REG
GND
REG
FB
REG
OUT
V
IN
18
V
IN
17
V
IN
16
V
IN
15
V
IN
2
V
IN
3
V
IN
4
Figure 3.
ADD8709
Rev. 0 | Page 8 of 16
14
8
6
2
04715-0-007
SUPPLY VOLTAGE (V)
S
U
P
P
L
Y
CURRE
NT (mA)
TYPICAL PERFORMANCE CHARACTERISTICS
0
18
4
16
10
12
0
1
2
3
4
5
6
7
8
9
10
11
12
30
0
5
10
15
20
25
0.1
100
10
1.0
04712-0-035
LOAD CURRENT (mA)
OUTP
UT V
O
LTAGE
E
RROR (mV
)
CH1 SOURCE
CH1 SINK
CH2 SOURCE
CH2 SINK
Figure 4. Supply Current vs. Supply Voltage
­20
120
60
40
0
04715-0-008
TEMPERATURE (
°
C)
S
U
P
P
L
Y
CURRE
NT (mA)
20
80
100
10.4
10.5
10.6
10.7
10.8
10.9
11.0
Figure 5. Supply Current vs. Temperature
20
­35
­30
­25
­20
­15
­10
­5
0
5
10
15
­20 ­10 0
10 20 30 40 50 60 70 80 90 100 110 120
04715-0-009
TEMPERATURE (
°
C)
OUTP
UT V
O
LTAGE
E
RROR (mV
)
I
SINK
= 25mA I
SINK
= 15mA
I
SINK
= 5mA
I
LOAD
= 0mA
I
SOURCE
= 25mA
I
SOURCE
= 15mA I
SOURCE
= 5mA
Figure 6. Output Voltage Error vs. Temperature
Figure 7. Output Voltage Error vs. Load Current
30
0
5
10
15
20
25
0.1
100
10
1.0
04712-0-036
LOAD CURRENT (mA)
OUTP
UT V
O
LTAGE
E
RROR (mV
)
CH3 SOURCE
CH3 SINK
CH9 SOURCE
CH9 SINK
Figure 8. Output Voltage Error vs. Load Current
30
0
5
10
15
20
25
0.1
100
10
1.0
04712-0-037
LOAD CURRENT (mA)
OUTP
UT V
O
LTAGE
E
RROR (mV
)
CH10 SOURCE
CH10 SINK
CH16 SOURCE
CH16 SINK
Figure 9. Output Voltage Error vs. Load Current
ADD8709
Rev. 0 | Page 9 of 16
30
0
5
10
15
20
25
0.1
100
10
1.0
04712-0-038
LOAD CURRENT (mA)
OUTP
UT V
O
LTAGE
E
RROR (mV
)
CH17 SOURCE
CH17 SINK
CH18 SOURCE
CH18 SINK
Figure 10. Output Voltage Error vs. Load Current
80
70
60
50
40
30
20
10
0
­25 ­21 ­17 ­13 ­9
­5
­1
3
19
23
7
11
15
04712-0-013
OUTPUT VOLTAGE ERROR (mV)
NUMBE
R OF AMP
L
IFIE
RS
Figure 11. Output Voltage Error/Gamma 1 and 2
120
100
80
60
40
20
0
­50 ­42 ­34 ­26 ­18 ­10 ­2
6
38
46
14
22
30
04712-0-014
OUTPUT VOLTAGE ERROR (mV)
NUMBE
R OF AMP
L
IFIE
RS
Figure 12. Output Voltage Error/Gamma 3 to 9
80
70
60
50
40
30
20
10
0
­100 ­80
­60
­40
­20
0
20
40
60
80
100
04712-0-016
OUTPUT VOLTAGE ERROR (mV)
NUMBE
R OF AMP
L
IFIE
RS
Figure 13. Output Voltage Error/Gamma 10 to 16
25
5
10
15
20
0
­100 ­80
­60
­40
­20
0
20
40
60
80
100
04712-0-015
OUTPUT VOLTAGE ERROR (mV)
NUMBE
R OF AMP
L
IFIE
RS
Figure 14. Output Voltage Error/Gamma 17 and 18
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17
04712-0-017
INPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
I
LOAD
= 0mA
I
LOAD
= 5mA
I
LOAD
= 10mA
Figure 15. Dropout Characteristics
ADD8709
Rev. 0 | Page 10 of 16
1000
900
800
700
600
500
400
300
200
100
0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
20
19
18
17
04712-0-018
OUTPUT CURRENT (mA)
D
R
O
POU
T
VOLTA
GE (
m
V)
Figure 16. Dropout Voltage vs. Output Current
800
750
700
650
600
550
500
450
400
350
300
250
200
150
100
50
0
­25 ­15 ­5
5
15 25 35 45 55 65 75 85 95 105 115
04712-0-019
TEMPERATURE (
°
C)
D
R
O
POU
T
VOLTA
G
E (
m
V)
10mA
5mA
0mA
Figure 17. Dropout Voltage vs. Temperature
14.5
14.4
14.3
14.2
14.1
14.0
13.9
13.8
13.7
13.6
0
2
4
6
8
10
12
14
16
18
20
04712-0-020
LOAD CURRENT (mA)
REGULATOR OUTPUT (V)
­20
°
C
0
°
C
+25
°
C
+55
°
C
+85
°
C
+95
°
C
+105
°
C
Figure 18. Regulator Output vs. I
LOAD
Over Temperature
14.45
14.40
14.35
14.30
14.25
14.20
­20 ­10
0
10
20
30
40
50
60
70
80
90 100 110
04712-0-021
TEMPERATURE (
°
C)
RE
GULATOR OUTP
UT (V
)
10mA
5mA
0mA
Figure 19. Regulator Output vs. Temperature
04712-0-022
TIME (100
µ
s/DIV)
INPUT VOLTAGE (V)
OUTP
UT V
O
LTAGE
CHANGE
(mV
)
17
18
15
16
400
200
0
­200
­400
14
C
LOAD
= 1
µ
F
Figure 20. Regulator Line Transient Response
04712-0-023
TIME (100
µ
s/DIV)
LOAD CURRE
NT (mA)
OUTP
UT V
O
LTAGE
CHANGE
(mV
)
0.1
­40
­20
0
20
40
5
C
LOAD
= 1
µ
F
Figure 21. Regulator Load Transient Response
ADD8709
Rev. 0 | Page 11 of 16
11
10
9
8
7
6
5
4
3
2
1
0
­200
1800
1600
1400
1200
1000
800
600
400
200
0
04712-0-012
TIME (ns)
AMP
L
ITUDE
(V
)
10V PULSE
120pF
10nF
1nF
520pF
320pF
Figure 22. Transient Load Response vs. Capacitive Loading
20
10
0
­10
­20
­30
100k
1M
10M
100M
04712-0-030
FREQUENCY (Hz)
GAIN (
d
B)
100pF
340pF
540pF
1040pF
50pF
Figure 23. Frequency Response vs. Capacitive Loading
10
­40
­30
­20
­10
0
100k
100M
10M
1M
04712-0-033
FREQUENCY (Hz)
GAIN (
d
B)
150
1k
2k
10k
GAMMA 1-9
Figure 24. Frequency Response vs. Resistive Loading
10
­40
­30
­20
­10
0
100k
100M
10M
1M
04712-0-032
FREQUENCY (Hz)
GAIN (
d
B)
150
1k
2k
10k
GAMMA 10-18
Figure 25. Frequency Response vs. Resistive Loading
10
­50
­40
­30
­20
­10
0
100k
100M
10M
1M
04712-0-034
FREQUENCY (Hz)
GAIN (
d
B)
150
1k
2k
10k
V
DD
= 16V
V
COM
Figure 26. Frequency Response vs. Resistive Loading
ADD8709
Rev. 0 | Page 12 of 16
APPLICATION NOTES
MAXIMUM POWER DISSIPATION
The maximum safe power dissipation in the ADD8709 package
is limited by the associated rise in junction temperature (T
J
)
on the die. At approximately 150°C, the glass transition temper-
ature, the properties of the plastic change. Even temporarily
exceeding this temperature limit may change the stresses that
the package exerts on the die, permanently shifting the para-
metric performance of the ADD8709. Exceeding a junction
temperature of 175°C for an extended period can result in
changes in the silicon devices, potentially causing failure.
OPERATING TEMPERATURE RANGE
The maximum junction temperature is as follows:
T
J
= T
AMB MAX
+
JA
× W
MAX
where:
T
AMB MAX
= maximum ambient temperature specified on the data
sheet.
JA
= junction-to-ambient thermal resistance, in °C/watt.
W
MAX
= maximum power dissipated in the device, in watts.
For the ADD8709, W
MAX
can be calculated with the following
equation:
W
MAX
= V
DD
× I
SYS
+ V
OUT
× I
OUT
+ V
DO
× I
O
where:
V
DD
× I
SYS
= nominal system power requirements
V
OUT
× I
OUT
= amplifier load power dissipation
V
DO
× I
O
= regulator load power dissipation
Example 1
The estimated power consumption of the ADD8709 in extreme
cases is as follows:
V
DD
× I
SYS
= 15 V × 15 mA
V
OUT
× I
OUT
= (8 V × 5 mA/channel) × 18 channels
V
DO
× I
O
= 0.6 V × 5 mA
W
MAX
= (15 V × 15 mA) + (8 V × 5 mA/channel ×
18 channel) + (0.6 V × 5 mA) = 0.948 W
JA
= 74.57°C/W, T
AMB MAX
= 45°C
T
J
= 45°C + (74.57°C/W) × (0.948 W) = 115.7°C
Here, 150°C is the maximum junction temperature that is
guaranteed before the part breaks down, while 125°C is the
maximum process limit. Because T
J
is < 150°C and < 125°C,
this example demonstrates a condition where the part should
perform within process limits.
ADD8709
Rev. 0 | Page 13 of 16
OUTLINE DIMENSIONS
TOP VIEW
(PINS DOWN)
1
12
13
25
24
36
37
48
0.27
0.22
0.17
0.50
BSC
7.00
BSC SQ
SEATING
PLANE
1.60
MAX
0.75
0.60
0.45
VIEW A
9.00 BSC
SQ
PIN 1
0.20
0.09
1.45
1.40
1.35
0.08 MAX
COPLANARITY
VIEW A
ROTATED 90
°
CCW
SEATING
PLANE
10°
6°
2°
7°
3.5°
0°
0.15
0.05
COMPLIANT TO JEDEC STANDARDS MS-026BBC
Figure 27. 48-Lead Low Profile Quad Flat Package
(ST-48)
Dimensions shown in millimeters
ADD8709
Rev. 0 | Page 14 of 16
ORDERING GUIDE
Model
1
Temperature Range
Package Description
Package Option
ADD8709ASTZ-REEL
2
­40°C to +100°C
48-Lead Low Profile Quad Flat Package
ST-48
ADD8709ASTZ-REEL7
2
­40°C to +100°C
48-Lead Low Profile Quad Flat Package
ST-48
1
Available in reels only.
2
Z = Pb-free part.
ADD8709
Rev. 0 | Page 15 of 16
NOTES
ADD8709
Rev. 0 | Page 16 of 16
NOTES
© 2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04715­0­7/04(0)