Rail-to-Rail, Very Fast, 2.5 V to 5.5 V,

Single-Supply CML Comparators

Preliminary Technical Data

ADCMP606/ADCMP607

Rev. PrA

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700

www.analog.com

Fax: 781.461.3113

FEATURES

10 mV sensitivity rail to rail at V

= 2.5 V

Input common-mode voltage from -0.2 V to V

+ 0.2 V

CML-compatible output stage
1 ns propagation delay
50 mW at 2.5 V
Shutdown pin (ADCMP607 only)
Single-pin control for programmable hysteresis and latch

(ADCMP607 only)

Power supply rejection > 60 dB
-40°C to +125°C operation

APPLICATIONS

High speed instrumentation
Clock and data signal restoration
Logic level shifting or translation
Pulse spectroscopy
High speed line receivers
Threshold detection
Peak and zero-crossing detectors
High speed trigger circuitry
Pulse-width modulators
Current-/voltage-controlled oscillators
Automatic test equipment (ATE)

FUNCTIONAL BLOCK DIAGRAM

NONINVERTING

INPUT

INVERTING

INPUT

INPUT (ADCMP607 Only)

CCI

CCO

(ADCMP607 Only)

Q OUTPUT

LE/HYS INPUT (ADCMP607 Only)

ADCMP606/

ADCMP607

CML

Figure 1.

PIN 1
INDICATOR

CCO

CCI

9 V

8 LE/HYS

7 S

1
2

1
1

1
0

TOP VIEW

(Not to Scale)

ADCMP607

0
03

Figure 2.LFCSP Pin Configuration

GENERAL DESCRIPTION

The ADCMP606/ADCMP607 are very fast comparators
fabricated on Analog Devices' proprietary XFCB2 process.
These comparators are exceptionally versatile and easy to use.
Features include an input range from V

- 0.5 V to V

+ 0.5 V,

low noise CML-compatible output drivers, and TTL-/CMOS-
compatible latch inputs with adjustable hysteresis and/or
shutdown inputs.

The device offers 1 ns propagation delay with 2 ps RMS random
jitter (RJ). Overdrive and slew rate dispersion are typically less
than 50 ps.

A flexible power supply scheme allows the devices to operate
with a single +2.5 V positive supply and a -0.5 V to +3.0 V
input signal range up to a +5.5 V positive supply with a -0.5 V

to +6 V input signal range. The ADCMP607 features split
input/output supplies with no sequencing restrictions to support
a wide input signal range with independent output level control
and power savings.

The CML-compatible output stage is fully back-matched for
superior performance. The comparator input stage offers robust
protection against large input overdrive, and the outputs do not
phase reverse when the valid input signal range is exceeded. On
the ADCMP607, high speed latch and programmable hysteresis
features are also provided with a unique single-pin control option.

The ADCMP606 is available in a 6-lead SC70 package, and the
ADCMP607 is available in a 12-lead LSCFP package.

ADCMP606/ADCMP607

Preliminary Technical Data

Rev. PrA | Page 2 of 16

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Electrical Characteristics ................................................................. 3

Absolute Maximum Ratings............................................................ 5

Thermal Resistance ...................................................................... 5

ESD Caution.................................................................................. 5

Pin Configuration and Function Descriptions............................. 6

Typical Performance Characteristics ............................................. 7

Application Information...................................................................9

Power/Ground Layout and Bypassing........................................9

CML-Compatible Output Stage ..................................................9

Using/Disabling the Latch Feature..............................................9

Optimizing Performance........................................................... 10

Comparator Propagation Delay Dispersion ........................... 10

Comparator Hysteresis .............................................................. 10

Crossover Bias Point .................................................................. 11

Minimum Input Slew Rate Requirement ................................ 11

Typical Application Circuits ......................................................... 12

Timing Information ....................................................................... 13

REVISION HISTORY

3/06--Revision PrA: Preliminary Version

Preliminary Technical Data

ADCMP606/ADCMP607

Rev. PrA | Page 3 of 16

ELECTRICAL CHARACTERISTICS

CCI

= V

CCO

= 3.0 V, T

= 25°C, unless otherwise noted.

Table 1.

Parameter Symbol

Conditions

Min

Typ

Max

Unit

INPUT

CHARACTERISTICS

Voltage Range

, V

= 2.5 V to 5.5 V

-0.5

+ 0.5 V

Common-Mode Range

= 2.5 V to 5.5 V

-0.2

+ 0.2 V

Differential Voltage

= 2.5 V to 5.5 V

Offset Voltage

-5.0

+5.0 mV

Bias Current

, I

-5.0 ±2 +5.0 A

Offset

Current

2.0

2.0 A

Capacitance C

, C

TBD

Resistance, Differential Mode

0.1 V to V

100

Resistance, Common Mode

-0.5 V to V

+ 0.5 V

100

Active Gain

CCI

= 2.5 V, V

CCO

= 2.5 V,

= -0.2 V to 2.7 V

Common-Mode Rejection

CMRR

CCI

= 5.5 V, V

CCO

= 5.5 V,

= -0.2 V to 5.7 V

Hysteresis

HYS

0.1

LATCH ENABLE PIN CHARACTERISTICS

(ADCMP606 Only)

Hysteresis is shut off

2.0

Latch

mode

guaranteed

-0.2 +0.4 +0.8 V

= V

0.2

= 0.4 V

-0.2

HYSTERESIS

MODE

AND

TIMING

Hysteresis Mode Bias Voltage

Current sink 0 A

1.145

1.25

1.35

Minimum Resistor Value

Hysteresis = 16 mV

150

Latch Setup Time

= 100 mV

Latch Hold Time

= 100 mV

Latch-to-Output Delay

PLOH

, t

PLOL

= 100 mV

Latch Minimum Pulse Width

= 100 mV

SHUTDOWN PIN CHARACTERISTICS

(ADCMP607 Only)

Comparator is operating

2.0

CCO

Shutdown

guaranteed

-0.2 +0.4 +0.6 V

= V

0.3

= 0 V

-0.3

Sleep Time

< 500 A

Wake-Up Time

= 10 mV, output valid

DC OUTPUT CHARACTERISTICS

CCO

= 2.5 V to 5.5 V

Output Voltage High Level

RI = 50 , V

CCO

= 2.5 V

- 0.1

+ 0.1

Output Voltage Low Level

RI = 50 , V

CCO

= 2.5 V

- 0.35

- 0.5

Minimum Output Low Level

(ADCMP607)

CCI

= 2.5 V, T

= -40°C

(internal termination only)

TBD

ADCMP606/ADCMP607

Preliminary Technical Data

Rev. PrA | Page 4 of 16

Parameter Symbol

Conditions

Min

Typ

Max

Unit

PERFORMANCE

Propagation Delay

= 2.5 V to 5.5 V,

= 5 mV

= 2.5 V to 5.5 V,

= 200 mV

Propagation Delay Skew--Rising to

Falling Transition

= 5 mV

Overdrive Dispersion

10 mV < V

< 2.5 V

TBD

5 mV < V

< 2.5 V

TBD

Slew Rate Dispersion

0.05 V/ns to 2.5 V/ns

TBD

Pulse-Width Dispersion

300 ps to 20 ns

TBD

10% to 90% Duty Cycle Dispersion

1 V/ns, V

= 2.5 V

TBD

Common-Mode Dispersion

0 < V

< V

TBD

Toggle Rate

>50% output swing

TBD

Gbps

Deterministic Jitter

CML Outputs

= 200 mV, 5 V/ns,

PRBS

- 1 NRZ, 0.25 Gbps

TBD

RMS Random Jitter

= 200 mV, 5 V/ns,

PRBS

- 1 NRZ, 0.525 Gbps

TBD

Minimum Pulse Width

MIN

/PW < 50 ps

300

Rise Time

10% to 90%

150

Fall Time

10% to 90%

150

Output skew

SKEW

50%

POWER

SUPPLY

Input Supply Voltage Range

CCI

2.5

5.5 V

Output Supply Voltage Range

CCO

2.5

5.5 V

Positive Supply Differential

(ADCMP607)

CCI

CCO

Operating

-3.0

+3.0 V

Positive Supply Differential

(ADCMP607)

CCI

CCO

Nonoperating

-5.5

+5.5 V

Positive Supply Current

VCC

= 2.5 V

Positive Supply Current

VCC

= 5.5 V

Input Section Supply Current

(ADCMP607)

VCCI

CCI

= 2.5 V to 5 V

0.8

Output Section Supply Current

(ADCMP607)

VCCO

CCI

= 2.5 V to 5.5 V

22.5

Power Dissipation

= 2.5 V

= 5.5 V

125

Power Supply Rejection

PSRR

CCI

= 2.5 V to 5 V

-50

Preliminary Technical Data

ADCMP606/ADCMP607

Rev. PrA | Page 5 of 16

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

Supply Voltages

Input Supply Voltage (V to GND)

-0.5 V to +6.0 V

CCI

-0.5 V to +6.0 V

Output Supply Voltage

to GND)

CCO

-6.0 V to +6.0 V

Positive Supply Differential

(V - V

)

CCI

CCO

Input Voltages

THERMAL RESISTANCE

Input Voltage

-0.5 V to V + 0.5 V

CCI

Differential Input Voltage

±(V

CCI

+ 0.5 V)

is specified for the worst-case conditions, that is, a device

soldered in a circuit board for surface-mount packages.

Maximum Input/Output Current

±50 mA

Shutdown Control Pin

Table 3. Thermal Resistance

Applied Voltage (HYS to GND)

-0.5 V to V

+ 0.5 V

Package Type

Unit

CCO

Maximum Input/Output Current

±50 mA

ADCMP606 SC70 6-lead

426

°C/W

Latch/Hysteresis Control Pin

ADCMP607 LSCFP 12-lead

°C/W

Applied Voltage (HYS to GND)

-0.5 V to V

+ 0.5 V

CCO

Measurement in still air.

Maximum Input/Output Current

±50 mA

Output Current

±50 mA

Temperature

Operating Temperature, Ambient

-40°C to +125°C

Operating Temperature, Junction

150°C

Storage Temperature Range

-65°C to +150°C

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

ADCMP606/ADCMP607

Preliminary Technical Data

Rev. PrA | Page 6 of 16

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

PIN 1
INDICATOR

CCO

CCI

9 V

8 LE/HYS

7 S

1
2

1
1

1
0

TOP VIEW

(Not to Scale)

ADCMP607

0
03

CCI

CCO

ADCMP606

TOP VIEW

(Not to Scale)

0
591

0
02

Figure 3. ADCMP606 Pin Configuration

Figure 4. ADCMP607 Pin Configuration

Table 4. ADCMP606 (SC70-6) Pin Function Descriptions

Pin No.

Mnemonic

Description

1 Q

Noninverting Output. Q is at logic high if the analog voltage at the noninverting input, V

, is greater

than the analog voltage at the inverting input, V

2 V

Negative Supply Voltage.

3 V

Noninverting Analog Input.

4 V

Inverting Analog Input.

5 V /V

CCI

CCO

Input Section Supply/Output Section Supply. Shared pin.

Inverting Output. Q is at logic low if the analog voltage at the noninverting input, V

, is greater than

the analog voltage at the inverting input, V

Table 5. ADCMP607 (LSCFP-12) Pin Function Descriptions

Pin No.

Mnemonic

Description

1 V

Output Section Supply.

CCO

2 V

CCI

Input Section Supply.

3 V

Negative Supply Voltage.

4 V

Noninverting Analog Input.

5 V

Negative Supply Voltage.

6 V

Inverting Analog Input.

7 S

Shutdown. Drive this pin low to shut down the device.

LE/HYS

Latch/Hysteresis Control. Bias with resistor or current for hysteresis adjustment; drive low to latch.

9 V

Negative Supply Voltage.

Inverting Output. Q is at logic low if the analog voltage at the noninverting input, V

, is greater than the

analog voltage at the inverting input, V

, provided that the comparator is in compare mode.

11 V

Negative Supply Voltage.

12 Q

Noninverting Output. Q is at logic high if the analog voltage at the noninverting input, V

, is greater than

the analog voltage at the inverting input, V

, provided that the comparator is in compare mode.

Heat Sink
Paddle

The metallic back surface of the package is electrically connected to V

. It can be left floating because

Pin 3, Pin 5, Pin 9, and Pin 11 provide adequate electrical connection. It can also be soldered to the
application board if improved thermal and/or mechanical stability is desired.

Preliminary Technical Data

ADCMP606/ADCMP607

Rev. PrA | Page 9 of 16

APPLICATION INFORMATION

POWER/GROUND LAYOUT AND BYPASSING

If these high speed signals must be routed more than a
centimeter, then either microstrip or strip line techniques are
required to ensure proper transition times and to prevent
excessive output ringing and pulse-width-dependent
propagation delay dispersion.

The ADCMP606 and ADCMP607 comparators are very high
speed devices. Despite the low noise output stage, it is essential
to use proper high speed design techniques to achieve the
specified performance. Because comparators are
uncompensated amplifiers, feedback in any phase relationship is
likely to cause oscillations or undesired hysteresis. Of critical
importance is the use of low impedance supply planes,
particularly the output supply plane (V

It is also possible to operate the outputs with only the internal
termination if greater output swing is desired. This can be
especially useful for driving inputs on CMOS devices intended
for full swing ECL and PECL. V

CCO

) and the ground

plane (GND). Individual supply planes are recommended as
part of a multilayer board. Providing the lowest inductance
return path for switching currents ensures the best possible
performance in the target application.

CCO

must be kept high enough

that the specified minimum output low level (see the Electrical
Characteristics section) is not violated and the line length
driven is as short as possible.

USING/DISABLING THE LATCH FEATURE

It is also important to adequately bypass the input and output
supplies. Multiple high quality 0.01 F bypass capacitors should
be placed as close as possible to each of the V

The latch input of the ADCMP607 is designed for maximum
versatility. It can safely be left floating, or it can be driven low by
any standard TTL/CMOS device as a high speed latch.

CCI

and V

CCO

supply

pins and should be connected to the GND plane with redundant
vias. At least one of these should be placed to provide a physically
short return path for output currents flowing back from ground
to the V

In addition, the pin can be operated as a hysteresis control pin
with a bias voltage of 1.25 V nominal and an input resistance of
approximately 7000 , allowing the comparator hysteresis to be
easily controlled by either a resistor or an inexpensive CMOS DAC.
Driving this pin high or floating the pin removes all hysteresis.

pin. High frequency bypass capacitors should be

carefully selected for minimum inductance and ESR. Parasitic
layout inductance should also be strictly controlled to maximize
the effectiveness of the bypass at high frequencies.

Hysteresis control and latch mode can be used together if an
open drain, an open collector, or a three-state driver is connected
parallel to the hysteresis control resistor or current source.

CML-COMPATIBLE OUTPUT STAGE

Specified propagation delay dispersion performance can be
achieved by using proper transmission line terminations. The
outputs of the ADCMP606 and ADCMP607 are designed to drive
400 mV directly into a 50 cable or into transmission lines
terminated using either microstrip or strip line techniques with
50 referenced to V

Due to the programmable hysteresis feature, the logic threshold
of the latch pin is approximately 1.1 V regardless of V

. The CML output stage is shown in the

simplified schematic diagram in Figure 14. Each output is back-
terminated with 50 for best transmission line matching.

16mA

CCO

GND

Figure 14. Simplified Schematic Diagram of

CML-Compatible Output Stage

ADCMP606/ADCMP607

Preliminary Technical Data

Rev. PrA | Page 10 of 16

Q/Q OUTPUT

INPUT VOLTAGE

10V/ns

1V/ns

DISPERSION

± V

0
15

OPTIMIZING PERFORMANCE

As with any high speed comparator, proper design and layout
techniques are essential for obtaining the specified performance.
Stray capacitance, inductance, inductive power and ground
impedances, or other layout issues can severely limit performance
and often cause oscillation. Large discontinuities along input
and output transmission lines can also limit the specified pulse-
width dispersion performance. The source impedance should
be minimized as much as is practicable. High source impedance,
in combination with the parasitic input capacitance of the
comparator, causes an undesirable degradation in bandwidth at
the input, thus degrading the overall response. Thermal noise
from large resistances can easily cause extra jitter with slowly
slewing input signals; higher impedances encourage undesired
coupling.

Figure 16. Propagation Delay--Slew Rate Dispersion

COMPARATOR HYSTERESIS

The addition of hysteresis to a comparator is often desirable in a
noisy environment, or when the differential input amplitudes
are relatively small or slow moving. Figure 17 shows the transfer
function for a comparator with hysteresis. As the input voltage
approaches the threshold (0.0 V, in this example) from below
the threshold region in a positive direction, the comparator
switches from low to high when the input crosses +V

COMPARATOR PROPAGATION
DELAY DISPERSION

/2, and the

new switching threshold becomes -V

The ADCMP606/ADCMP607 comparators are designed to
reduce propagation delay dispersion over a wide input overdrive
range of 5 mV to V

/2. The comparator remains

in the high state until the new threshold, -V

/2, is crossed from

below the threshold region in a negative direction. In this manner,
noise or feedback output signals centered on 0.0 V input cannot
cause the comparator to switch states unless it exceeds the region
bounded by ±V

CCI

1 V. Propagation delay dispersion is the

variation in propagation delay that results from a change in the
degree of overdrive or slew rate (that is, how far or how fast the
input signal exceeds the switching threshold).

/2.

Propagation delay dispersion is a specification that becomes
important in high speed, time-critical applications, such as data
communication, automatic test and measurement, and instru-
mentation. It is also important in event-driven applications, such
as pulse spectroscopy, nuclear instrumentation, and medical
imaging. Dispersion is defined as the variation in propagation
delay as the input overdrive conditions are changed (

OUTPUT

INPUT

059

-
01

Figure 15

and Figure 16).

ADCMP606/ADCMP607 dispersion is typically <TBD ps as the
overdrive varies from 10 mV to 500 mV and the input slew rate
varies from 2 V/ns to 10 V/ns. This specification applies to both
positive and negative signals because each device has very closely
matched delays for positive-going and negative-going inputs, as
well as very low output skews.

Figure 17. Comparator Hysteresis Transfer Function

The customary technique for introducing hysteresis into a
comparator uses positive feedback from the output back to the
input. One limitation of this approach is that the amount of
hysteresis varies with the output logic levels, resulting in
hysteresis that is not symmetric about the threshold. The
external feedback network can also introduce significant
parasitics that reduce high speed performance and induce
oscillation in some cases.

Q/Q OUTPUT

INPUT VOLTAGE

500mV OVERDRIVE

10mV OVERDRIVE

DISPERSION

± V

The ADCMP607 comparator offers a programmable hysteresis
feature that can significantly improve accuracy and stability.
Connecting an external pull-down resistor or a current source
from the LE/HYS pin to GND, varies the amount of hysteresis
in a predictable, stable manner. Leaving the LE/HYS pin
disconnected or driving it high removes the hysteresis. The

Figure 15. Propagation Delay--Overdrive Dispersion

Preliminary Technical Data

ADCMP606/ADCMP607

Rev. PrA | Page 11 of 16

CROSSOVER BIAS POINT

maximum hysteresis that can be applied using this pin is
approximately 160 mV. Figure 18 illustrates the amount of
hysteresis applied as a function of the external resistor value,
and Figure TBD illustrates hysteresis as a function of the current.

In both op amps and comparators, rail-to-rail inputs of this type
have a dual front-end design. Certain devices are active near the
V

rail and others are active near the V

rail. At some predeter-

mined point in the common-mode range, a crossover occurs. At
this point, normally V

The hysteresis control pin appears as a 1.25 V bias voltage seen
through a series resistance of 7k ± 20% throughout the hysteresis
control range. The advantages of applying hysteresis in this manner
are improved accuracy, improved stability, reduced component
count, and maximum versatility. An external bypass capacitor is
not recommended on the HYS pin because it impairs the latch
function and often degrades the jitter performance of the device.
As described in the

/2, the direction of the bias current reverses

and the measured offset voltages and currents change.

The ADCMP606/ADCMP607 slightly elaborate on this scheme.
With V

less than 4 V, this crossover is at the expected V

/2,

but with V

greater than 4 V, the crossover point instead follows

1:1, bringing it to approximately 3 V with V

at 5 V. This

means that at any voltage, the comparator input characteristics
more closely resemble the inputs of nonrail-to-rail ground
sensing comparators, such as the AD8611.

Using/Disabling the Latch Feature section,

hysteresis control need not compromise the latch function.

MINIMUM INPUT SLEW RATE REQUIREMENT

(Remove if device is stable.)

As with most high speed comparators without hysteresis, a
minimum slew rate must be met to ensure that the device does not
oscillate as the input signal crosses the threshold. This oscillation
is due in part to the high input bandwidth of the comparator in
combination with feedback parasitics inherent in the package
and PC board. A minimum slew rate of TBD V/s ensures clean
output transitions from the ADCMP606/ADCMP607 comparators
unless hysteresis is programmed. In many applications, chattering
due to the absence of hysteresis is not harmful.

Figure 18. Hysteresis vs. R

Control Resistor

HYS

ADCMP606/ADCMP607

Preliminary Technical Data

Rev. PrA | Page 12 of 16

TYPICAL APPLICATION CIRCUITS

INPUT

2.5V

REF

INPUT

2.5V

±50mV

LE/HYS

ADCMP601

150pF

10k

100k

10k

ADCMP606

CML

PWM

OUTPUT

ADCMP606

CML

OUTPUT

0.1µF

2.5V TO 5V

0.1µF

INPUT

917

-
0

Figure 19. Self-Biased, 50% Slicer

ADCMP606

100

LVDS

591

CML

OUTPUT

3.3V

Figure 23. Oscillator and Pulse-Width Modulator

Figure 20. LVDS to CML

150k

LE/HYS

DIGITAL

INPUT

CONTROL

VOLTAGE

0V TO 2.5V

74 VHC

1G07

7
-
02

ADCMP607

2.5V TO 5V

LE/HYS

ADCMP607

82pF

10k

CONTROL

VOLTAGE

591

CML

OUTPUT

Figure 24. Hysteresis Adjustment with Latch

Figure 21. Current-Controlled Oscillator

ADCMP607

0
24

OUTPUT

CCO

+2.5V

CCI

2.5V

ADCMP607

100

LVDS

3.3V

PECL

CCO

1N4001

CCI

3.3V

Figure 25.Ground-Referenced CML with ±3 V Input Range

Figure 22.Fake PECL Levels Using a Series Diode

Preliminary Technical Data

ADCMP606/ADCMP607

Rev. PrA | Page 13 of 16

TIMING INFORMATION

Figure 26 illustrates the ADCMP606/ADCMP607 timing relationships. Table 6 provides definitions of the terms shown in the figure.

1.1V

50%

± V

DIFFERENTIAL

INPUT VOLTAGE

LATCH ENABLE

Q OUTPUT

PDL

PLOH

0
25

50%

Q OUTPUT

PDH

PLOL

Figure 26. System Timing Diagram

Table 6. Timing Descriptions

Symbol Timing

Description

Input to output high delay

Propagation delay measured from the time the input signal crosses the reference (± the
input offset voltage) to the 50% point of an output low-to-high transition.

PDH

Input to output low delay

Propagation delay measured from the time the input signal crosses the reference (± the
input offset voltage) to the 50% point of an output high-to-low transition.

PDL

Output rise time

Amount of time required to transition from a low to a high output as measured at the 20%
and 80% points.

Output fall time

Amount of time required to transition from a high to a low output as measured at the 20%
and 80% points.

Voltage overdrive

Difference between the input voltages V

and V .

Part Number ADCMP607

Document Outline