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Quad, 14-bit, 50 MSPS

Serial LVDS 1.8 V A/D Converter

AD9259

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700

www.analog.com

Fax: 781.461.3113

FEATURES

Four ADCs integrated into 1 package
98 mW ADC power per channel at 50 MSPS
SNR = 73 dB (to Nyquist)
ENOB = 12 bits
SFDR = 84 dBc (to Nyquist)
Excellent linearity

DNL = ±0.5 LSB (typical)
INL = ±1.5 LSB (typical)

Serial LVDS (ANSI-644, default)

Low power reduced signal option, IEEE 1596.3 similar

Data and frame clock outputs
315 MHz full power analog bandwidth
2 V p-p input voltage range
1.8 V supply operation
Serial port control

Full-chip and individual-channel power-down modes
Flexible bit orientation
Built-in and custom digital test pattern generation
Programmable clock and data alignment
Programmable output resolution
Standby mode

APPLICATIONS

Medical imaging and nondestructive ultrasound
Portable ultrasound and digital beam forming systems
Quadrature radio receivers
Diversity radio receivers
Tape drives
Optical networking
Test equipment

GENERAL DESCRIPTION

The AD9259 is a quad, 14-bit, 50 MSPS analog-to-digital
converter (ADC) with an on-chip sample-and-hold circuit that
is designed for low cost, low power, small size, and ease of use.
The product operates at a conversion rate of up to 50 MSPS and
is optimized for outstanding dynamic performance and low
power in applications where a small package size is critical.

The ADC requires a single 1.8 V power supply and LVPECL-/
CMOS-/LVDS-compatible sample rate clock for full performance
operation. No external reference or driver components are
required for many applications.

The ADC automatically multiplies the sample rate clock for the
appropriate LVDS serial data rate. A data clock (DCO) for

FUNCTIONAL BLOCK DIAGRAM

SERIAL

LVDS

REF

SELECT

AD9259

AGND

VIN A

VIN + A

VIN B

VIN + B

VIN D

VIN + D

VIN C

VIN + C

SENSE

VREF

AVDD

DRVDD

PDWN

REFT

REFB

D A

D + A

D B

D + B

D D

D + D

D C

D + C

FCO

FCO+

DCO+
DCO

CLK+

DRGND

CLK

SERIAL PORT

INTERFACE

CSB

SCLK/DTP

SDIO/ODM

RBIAS

SERIAL

LVDS

SERIAL

LVDS

SERIAL

LVDS

PIPELINE

ADC

PIPELINE

ADC

PIPELINE

ADC

PIPELINE

ADC

DATA RATE

MULTIPLIER

0.5V

0596

001

T/H

Figure 1.

capturing data on the output and a frame clock (FCO) for
signaling a new output byte are provided. Individual channel
power-down is supported and typically consumes 2 mW when
all channels are disabled.

The ADC contains several features designed to maximize
flexibility and minimize system cost, such as programmable
clock and data alignment and programmable digital test pattern
generation. The available digital test patterns include built-in
deterministic and pseudorandom patterns, along with custom user-
defined test patterns entered via the serial port interface (SPI®).

The AD9259 is available in a Pb-free, 48-lead LFCSP package. It is
specified over the industrial temperature range of -40°C to +85°C.

PRODUCT HIGHLIGHTS

Small Footprint. Four ADCs are contained in a small, space-
saving package; low power of 98 mW/channel at 50 MSPS.

Ease of Use. A data clock output (DCO) operates up to
350 MHz and supports double data rate operation (DDR).

User Flexibility. Serial port interface (SPI) control offers a wide
range of flexible features to meet specific system requirements.

Pin-Compatible Family. This includes the AD9287 (8-bit),
AD9219 (10-bit), and AD9228 (12-bit).

AD9259

Rev. 0 | Page 2 of 52

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

AC Specifications.......................................................................... 4

Digital Specifications ................................................................... 5

Switching Specifications .............................................................. 6

Timing Diagrams.............................................................................. 7

Absolute Maximum Ratings............................................................ 9

Thermal Impedance ..................................................................... 9

ESD Caution.................................................................................. 9

Pin Configuration and Function Descriptions........................... 10

Equivalent Circuits ......................................................................... 12

Typical Performance Characteristics ........................................... 14

Theory of Operation ...................................................................... 18

Analog Input Considerations ................................................... 18

Clock Input Considerations...................................................... 20

Serial Port Interface (SPI).............................................................. 28

Hardware Interface..................................................................... 28

Memory Map .................................................................................. 30

Reading the Memory Map Table.............................................. 30

Reserved Locations .................................................................... 30

Default Values ............................................................................. 30

Logic Levels................................................................................. 30

Evaluation Board ............................................................................ 34

Power Supplies ............................................................................ 34

Input Signals................................................................................ 34

Output Signals ............................................................................ 34

Default Operation and Jumper Selection Settings................. 35

Alternative Analog Input Drive Configuration...................... 36

Outline Dimensions ....................................................................... 50

Ordering Guide .......................................................................... 50

REVISION HISTORY

6/06--Revision 0: Initial Version

AD9259

Rev. 0 | Page 3 of 52

SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = -0.5 dBFS, unless otherwise noted.

Table 1.

AD9259-50

Parameter

Temperature Min

Typ

Max

Unit

RESOLUTION

Bits

ACCURACY

No Missing Codes

Full

Guaranteed

Offset Error

Full

±1

±8

Offset Matching

Full

±2

±8

Gain Error

Full

±0.5

±2

% FS

Gain Matching

Full

±0.3

±0.7

% FS

Differential Nonlinearity (DNL)

Full

±0.5

±1.0

LSB

Integral Nonlinearity (INL)

Full

±1.5

±3.5

LSB

TEMPERATURE DRIFT

Offset Error

Full

±2

ppm/°C

Gain Error

Full

±17

ppm/°C

Reference Voltage (1 V Mode)

Full

±21

ppm/°C

REFERENCE

Output Voltage Error (VREF = 1 V)

Full

±5

±30

Load Regulation @ 1.0 mA (VREF = 1 V)

Full

Input Resistance

Full

ANALOG INPUTS

Differential Input Voltage Range (VREF = 1 V)

Full

V p-p

Common-Mode Voltage

Full

AVDD/2

Differential Input Capacitance

Full

Analog Bandwidth, Full Power

Full

315

MHz

POWER SUPPLY

AVDD Full

1.7

1.8

1.9

DRVDD Full

1.7

1.8

1.9

IAVDD Full

185

192.5

IDRVDD Full

32.5

34.7

Total Power Dissipation (Including Output Drivers)

Full

392

409

Power-Down Dissipation

Full

Standby Dissipation

Full

CROSSTALK Full

-100

CROSSTALK (Overrange Condition)

Full

-100

See the

AN-835 Application Note

, "Understanding High Speed ADC Testing and Evaluation," for a complete set of definitions and how these tests were completed.

Can be controlled via SPI.

Overrange condition is specific with 6 dB of the full-scale input range.

AD9259

Rev. 0 | Page 4 of 52

AC SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = -0.5 dBFS, unless otherwise noted.

Table 2.

AD9259-50

Parameter

Temperature

Min

Typ

Max

Unit

SIGNAL-TO-NOISE RATIO (SNR)

= 2.4 MHz

Full

73.5

= 19.7 MHz

Full

71.0

73.0

= 70 MHz

Full

72.8

SIGNAL-TO-NOISE AND DISTORTION RATIO (SINAD)

= 2.4 MHz

Full

72.7

= 19.7 MHz

Full

70.2

72.2

= 70 MHz

Full

72.0

EFFECTIVE NUMBER OF BITS (ENOB)

= 2.4 MHz

Full

12.0

Bits

= 19.7 MHz

Full

11.6

11.9

Bits

= 70 MHz

Full

11.9

Bits

SPURIOUS-FREE DYNAMIC RANGE (SFDR)

= 2.4 MHz

Full

dBc

= 19.7 MHz

Full

dBc

= 70 MHz

Full

dBc

WORST HARMONIC (Second or Third)

= 2.4 MHz

Full

-88

dBc

= 19.7 MHz

Full

-84

-73

dBc

= 70 MHz

Full

-78

dBc

WORST OTHER (Excluding Second or Third)

= 2.4 MHz

Full

-90

dBc

= 19.7 MHz

Full

-90

-80

dBc

= 70 MHz

Full

-88

dBc

TWO-TONE INTERMODULATION DISTORTION (IMD)--

AIN1 AND AIN2 = -7.0 dBFS

IN1

= 15 MHz,

IN2

= 16 MHz

25°C

80.0

dBc

IN1

= 70 MHz,

IN2

= 71 MHz

25°C

80.0

dBc

See the

AN-835 Application Note

, "Understanding High Speed ADC Testing and Evaluation," for a complete set of definitions and how these tests were completed.

AD9259

Rev. 0 | Page 5 of 52

DIGITAL SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = -0.5 dBFS, unless otherwise noted.

Table 3.

AD9259-50

Parameter

Temperature Min

Typ

Max

Unit

CLOCK INPUTS (CLK+, CLK-)

Logic Compliance

CMOS/LVDS/LVPECL

Differential Input Voltage

Full 250

p-p

Input Common-Mode Voltage

Full

1.2

Input Resistance (Differential)

25°C

Input Capacitance

25°C

1.5

LOGIC INPUTS (PDWN, SCLK/DTP)

Logic 1 Voltage

Full

1.2

3.6

Logic 0 Voltage

Full

0.3

Input Resistance

25°C

Input Capacitance

25°C

0.5

LOGIC INPUT (CSB)

Logic 1 Voltage

Full

1.2

3.6

Logic 0 Voltage

Full

0.3

Input Resistance

25°C

Input Capacitance

25°C

0.5

LOGIC INPUT (SDIO/ODM)

Logic 1 Voltage

Full

1.2

DRVDD + 0.3

Logic 0 Voltage

Full

0.3

Input Resistance

25°C

Input Capacitance

25°C

LOGIC OUTPUT (SDIO/ODM)

Logic 1 Voltage (I

= 50 A)

Full

1.79

Logic 0 Voltage (I

= 50 A)

Full

0.05

DIGITAL OUTPUTS (D+, D-), (ANSI-644)

Logic Compliance

LVDS

Differential Output Voltage (V

) Full

247

454

Output Offset Voltage (V

) Full

1.125

1.375

Output Coding (Default)

Offset binary

DIGITAL OUTPUTS (D+, D-),

(Low Power, Reduced Signal Option)

Logic Compliance

LVDS

Differential Output Voltage (V

) Full

150

250

Output Offset Voltage (V

) Full

1.10

1.30

Output Coding (Default)

Offset binary

See the

AN-835 Application Note

, "Understanding High Speed ADC Testing and Evaluation," for a complete set of definitions and how these tests were completed.

This is specified for LVDS and LVPECL only.

AD9259

Rev. 0 | Page 6 of 52

SWITCHING SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = -0.5 dBFS, unless otherwise noted.

Table 4.

AD9259-50

Parameter

Temp Min

Typ

Max

Unit

CLOCK

Maximum Clock Rate

Full

MSPS

Minimum Clock Rate

Full

MSPS

Clock Pulse Width High (t

) Full

Clock Pulse Width Low (t

) Full

OUTPUT PARAMETERS

Propagation Delay (t

)

Full

2.0

2.7

3.5

Rise Time (t

) (20% to 80%)

Full

300

Fall Time (t

) (20% to 80%)

Full

300

FCO Propagation Delay (t

FCO

)

Full

2.0

2.7

3.5

DCO Propagation Delay (t

CPD

)

Full

FCO

SAMPLE

/28)

DCO to Data Delay (t

DATA

)

Full (t

SAMPLE

/28) - 300

SAMPLE

/28) (t

SAMPLE

/28) + 300

DCO to FCO Delay (t

FRAME

)

Full (t

SAMPLE

/28) - 300

SAMPLE

/28) (t

SAMPLE

/28) + 300

Data to Data Skew

DATA-MAX

- t

DATA-MIN

)

Full

±50

±150

Wake-Up Time (Standby)

25°C

600

Wake-Up Time (Power Down)

25°C

375

Pipeline Latency

Full

CLK
cycles

APERTURE

Aperture Delay (t

)

25°C

500

Aperture Uncertainty (Jitter)

25°C

ps rms

Out-of-Range Recovery Time

25°C

CLK
cycles

See the

AN-835 Application Note

, "Understanding High Speed ADC Testing and Evaluation," for a complete set of definitions and how these tests were completed.

Can be adjusted via the SPI interface.

SAMPLE

/28 is based on the number of bits multiplied by 2; delays are based on half duty cycles.

AD9259

Rev. 0 | Page 9 of 52

ABSOLUTE MAXIMUM RATINGS

Table 5.

Parameter

With
Respect To

Rating

ELECTRICAL

AVDD

AGND

-0.3 V to +2.0 V

DRVDD

DRGND

-0.3 V to +2.0 V

AGND

DRGND

-0.3 V to +0.3 V

AVDD

DRVDD

-2.0 V to +2.0 V

Digital Outputs

(D+, D-, DCO+,
DCO-, FCO+, FCO-)

DRGND

-0.3 V to +2.0 V

CLK+, CLK-

AGND

-0.3 V to +3.9 V

VIN+, VIN-

AGND

-0.3 V to +2.0 V

SDIO/ODM

AGND

-0.3 V to +2.0 V

PDWN, SCLK/DTP, CSB

AGND

-0.3 V to +3.9 V

REFT, REFB, RBIAS

AGND

-0.3 V to +2.0 V

VREF, SENSE

AGND

-0.3 V to +2.0 V

ENVIRONMENTAL

Operating Temperature

Range (Ambient)

-40°C to +85°C

Maximum Junction

Temperature

150°C

Lead Temperature

(Soldering, 10 sec)

300°C

Storage Temperature

Range (Ambient)

-65°C to +150°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

THERMAL IMPEDANCE

Table 6.

Air Flow Velocity (m/s)

0.0 24°C/W

1.0 21°C/W

12.6°C/W

1.2°C/W

2.5 19°C/W

for a 4-layer PCB with solid ground plane (simulated). Exposed pad

soldered to PCB.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

AD9259

Rev. 0 | Page 10 of 52

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

VIN + A

VIN A

AVDD

VIN + D

VIN D

DRVDD

DRGND

CLK+

CLK

AVDD

DRVDD

DRGND

AVDD

CSB

SCLK/DTP

SDIO/ODM

PDWN

AVDD

D +

D 

D +

D 

D +

D 

D +

D 

DCO

RBI

PIN 1

INDICATOR

EXPOSED PADDLE, PIN 0

(BOTTOM OF PACKAGE)

AD9259

TOP VIEW

0
03

Figure 5. 48-Lead LFCSP Top View

Table 7. Pin Function Descriptions

Pin No.

Name

Description

AGND

Analog Ground (Exposed Paddle)

1, 2, 5, 6, 9, 10, 27, 32,
35, 36, 39, 45, 46

AVDD

1.8 V Analog Supply

11, 26

DRGND

Digital Output Driver Ground

12, 25

DRVDD

1.8 V Digital Output Driver Supply

VIN - D

ADC D Analog Input--Complement

VIN + D

ADC D Analog Input--True

CLK-

Input Clock--Complement

CLK+

Input Clock--True

D - D

ADC D Complement Digital Output

D + D

ADC D True Digital Output

D - C

ADC C Complement Digital Output

D + C

ADC C True Digital Output

D - B

ADC B Complement Digital Output

D + B

ADC B True Digital Output

D - A

ADC A Complement Digital Output

D + A

ADC A True Digital Output

FCO-

Frame Clock Output--Complement

FCO+

Frame Clock Output--True

DCO-

Data Clock Output--Complement

DCO+

Data Clock Output--True

SCLK/DTP

Serial Clock/Digital Test Pattern

SDIO/ODM

Serial Data Input-Output/Output Driver Mode

CSB CSB

31 PDWN

Power-Down

VIN + A

ADC A Analog Input--True

VIN - A

ADC A Analog Input--Complement

AD9259

Rev. 0 | Page 14 of 52

TYPICAL PERFORMANCE CHARACTERISTICS

120

80

100

60

20

40

I
T

UDE

(

)

FREQUENCY (MHz)

AIN = 0.5dBFS

SNR = 73.8dB

ENOB = 11.88 BITS

SFDR = 83.4dBc

-
05

Figure 15. Single-Tone 32k FFT with f

= 2.3 MHz, f

SAMPLE

= 50 MSPS

120

80

100

60

20

40

I
T

UDE

(

)

FREQUENCY (MHz)

AIN = 0.5dBFS

SNR = 72.94dB

ENOB = 11.57 BITS

SFDR = 78.60dBc

Figure 16. Single-Tone 32k FFT with f

= 70 MHz, f

SAMPLE

= 50 MSPS

120

80

100

60

20

40

I
T

UDE

(

)

FREQUENCY (MHz)

AIN = 0.5dBFS

SNR = 71.96dB

ENOB = 11.41 BITS

SFDR = 76.68dBc

Figure 17. Single-Tone 32k FFT with f

= 120 MHz, f

SAMPLE

= 50 MSPS

I
T

UDE

(

)

120

20

40

60

80

100

FREQUENCY (MHz)

AIN = 0.5dBFS
SNR = 67.31dB
ENOB = 10.89 BITS
SFDR = 77.38dBc

-
0

Figure 18. Single-Tone 32k FFT with f

= 170 MHz, f

SAMPLE

= 50 MSPS

I
T

(

)

120

20

40

60

80

100

FREQUENCY (MHz)

AIN = 0.5dBFS
SNR = 66.87dB
ENOB = 10.82 BITS
SFDR = 74.97dBc

Figure 19. Single-Tone 32k FFT with f

= 190 MHz, f

SAMPLE

= 50 MSPS

I
T

(

)

120

20

40

60

80

100

FREQUENCY (MHz)

AIN = 0.5dBFS

SNR = 65.62dB

ENOB = 10.61 BITS

SFDR = 68.11dBc

Figure 20. Single-Tone 32k FFT with f

= 250 MHz, f

SAMPLE

= 50 MSPS

AD9259

Rev. 0 | Page 15 of 52

NR/

DR (

ENCODE (MSPS)

2V p-p, SNR

2V p-p, SFDR

Figure 21. SNR/SFDR vs. f

SAMPLE

, f

= 10.3 MHz, f

SAMPLE

= 50 MSPS

DR (

ENCODE (MSPS)

2V p-p, SNR

2V p-p, SFDR

Figure 22. SNR/SFDR vs. f

SAMPLE

, f

= 35 MHz, f

SAMPLE

= 50 MSPS

NR/

DR (

)

ANALOG INPUT LEVEL (dBFS)

100

60

50

40

30

20

10

= 10.3MHz

SAMPLE

= 50MSPS

2V p-p, SFDR

2V p-p, SNR

80dB

REFERENCE

0
66

Figure 23. SNR/SFDR vs. Analog Input Level, f

= 10.3 MHz, f

SAMPLE

= 50 MSPS

/
S

(

)

ANALOG INPUT LEVEL (dBFS)

100

60

50

40

30

20

10

= 35MHz

SAMPLE

= 50MSPS

2V p-p, SFDR

2V p-p, SNR

80dB

REFERENCE

0
65

Figure 24. SNR/SFDR vs. Analog Input Level, f

= 35 MHz, f

SAMPLE

= 50 MSPS

I
T

UDE

(

)

120

20

40

60

80

100

FREQUENCY (MHz)

AIN1 AND AIN2 = 7dBFS
SFDR = 87.76dBc
IMD2 = 90.18dBc
IMD3 = 87.27dBc

Figure 25. Two-Tone 32k FFT with f

IN1

= 15 MHz and

IN2

= 16 MHz, f

SAMPLE

= 50 MSPS

I
T

(

)

120

20

40

60

80

100

FREQUENCY (MHz)

AIN1 AND AIN2 = 7dBFS
SFDR = 80.37dBc
IMD2 = 79.75dBc
IMD3 = 84.50dBc

Figure 26. Two-Tone 32k FFT with f

IN1

= 70 MHz and

IN2

= 71 MHz, f

SAMPLE

= 50 MSPS

AD9259

Rev. 0 | Page 16 of 52

NR/

DR (

)

100

1000

ANALOG INPUT FREQUENCY (MHz)

2V p-p, SFDR (dBc)

2V p-p, SNR (dB)

Figure 27. SNR/SFDR vs. f

, f

SAMPLE

= 50 MSPS

I
N

AD/

DR (

TEMPERATURE (°C)

40

20

2V p-p, SINAD

2V p-p, SFDR

0
59

-
0
72

Figure 28. SINAD/SFDR vs. Temperature, f

= 10.3 MHz, f

SAMPLE

= 50 MSPS

2000

4000

6000

8000

10000 12000 14000 16000

2.0

1.5

1.0

0.5

1.0

1.5

(

)

CODE

0
59

-
0
73

Figure 29. INL, f

= 2.4 MHz, f

SAMPLE

= 50 MSPS

2000

4000

6000

8000 10000 12000 14000 16000

0.5

0.4

0.3

0.2

0.1

0.2

0.3

0.4

(

)

CODE

965

-
07

Figure 30. DNL, f

= 2.4 MHz, f

SAMPLE

= 50 MSPS

(

0
75

70

30

35

40

45

50

55

60

65

FREQUENCY (MHz)

Figure 31. CMRR vs. Frequency, f

SAMPLE

= 50 MSPS

I
TS

(

illio

)

0
86

0.2

0.4

0.6

0.8

1.0

1.2

N 3

N 2

N + 3

N + 2

N + 1

N 1

CODE

1.006 LSB rms

Figure 32. Input-Referred Noise Histogram, f

SAMPLE

= 50 MSPS

AD9259

Rev. 0 | Page 18 of 52

THEORY OF OPERATION

The AD9259 architecture consists of a pipelined ADC that is
divided into three sections: a 4-bit first stage followed by eight
1.5-bit stages and a final 3-bit flash. Each stage provides
sufficient overlap to correct for flash errors in the preceding
stages. The quantized outputs from each stage are combined
into a final 14-bit result in the digital correction logic. The
pipelined architecture permits the first stage to operate on a
new input sample while the remaining stages operate on preceding
samples. Sampling occurs on the rising edge of the clock.

Each stage of the pipeline, excluding the last, consists of a low
resolution flash ADC connected to a switched-capacitor DAC
and interstage residue amplifier (MDAC). The residue amplifier
magnifies the difference between the reconstructed DAC output
and the flash input for the next stage in the pipeline. One bit of
redundancy is used in each stage to facilitate digital correction
of flash errors. The last stage simply consists of a flash ADC.

The output staging block aligns the data, carries out the error
correction, and passes the data to the output buffers. The data is
then serialized and aligned to the frame and output clock.

ANALOG INPUT CONSIDERATIONS

The analog input to the AD9259 is a differential switched-capacitor
circuit designed for processing differential input signals. The input
can support a wide common-mode range and maintain excellent
performance. An input common-mode voltage of midsupply
minimizes signal-dependent errors and provides optimum
performance.

PAR

SAMPLE

PAR

VIN

VIN+

-
00

Figure 35. Switched-Capacitor Input Circuit

The clock signal alternately switches the input circuit between
sample mode and hold mode (see Figure 35). When the input
circuit is switched into sample mode, the signal source must be
capable of charging the sample capacitors and settling within
one-half of a clock cycle. A small resistor in series with each
input can help reduce the peak transient current injected from
the output stage of the driving source. In addition, low-Q inductors
or ferrite beads can be placed on each leg of the input to reduce
the high differential capacitance seen at the analog inputs, thus
realizing the maximum bandwidth of the ADC. Such use of

low-Q inductors or ferrite beads is required when driving the
converter front end at high IF frequencies. Either a shunt capacitor
or two single-ended capacitors can be placed on the inputs to
provide a matching passive network. This ultimately creates a
low-pass filter at the input to limit any unwanted broadband
noise. See the

AN-742 Application Note

, the

AN-827 Application

Note

, and the Analog Dialogue article "

Transformer-Coupled

Front-End for Wideband A/D Converters

" for more information

on this subject. In general, the precise values depend on the
application.

The analog inputs of the AD9259 are not internally dc-biased.
In ac-coupled applications, the user must provide this bias
externally. Setting the device so that V

= AVDD/2 is recom-

mended for optimum performance, but the device can function
over a wider range with reasonable performance, as shown in
Figure 36 and Figure 37.

NR/

DR (

ANALOG INPUT COMMON-MODE VOLTAGE (V)

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

SFDR (dBc)

SNR (dB)

= 2.3MHz

SAMPLE

= 50MSPS

Figure 36. SNR/SFDR vs. Common-Mode Voltage,

= 2.3 MHz, f

SAMPLE

= 50 MSPS

DR (

)

ANALOG INPUT COMMON-MODE VOLTAGE (V)

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

SFDR (dBc)

SNR (dB)

-
0

= 30MHz

SAMPLE

= 50MSPS

Figure 37. SNR/SFDR vs. Common-Mode Voltage,

= 30 MHz, f

SAMPLE

= 50 MSPS

AD9259

Rev. 0 | Page 19 of 52

For best dynamic performance, the source impedances driving
VIN+ and VIN- should be matched such that common-mode
settling errors are symmetrical. These errors are reduced by the
common-mode rejection of the ADC. An internal reference
buffer creates the positive and negative reference voltages, REFT
and REFB, respectively, that define the span of the ADC core.
The output common-mode of the reference buffer is set to
midsupply, and the REFT and REFB voltages and span are
defined as

REFT = 1/2 (AVDD + VREF)
REFB = 1/2 (AVDD - VREF)
Span = 2 × (REFT - REFB) = 2 × VREF

It can be seen from these equations that the REFT and REFB
voltages are symmetrical about the midsupply voltage and, by
definition, the input span is twice the value of the VREF voltage.

Maximum SNR performance is always achieved by setting the
ADC to the largest span in a differential configuration. In the
case of the AD9259, the largest input span available is 2 V p-p.

Differential Input Configurations

There are several ways in which to drive the AD9259 either
actively or passively. In either case, the optimum performance is
achieved by driving the analog input differentially. One example
is by using the

AD8332

differential driver. It provides excellent

performance and a flexible interface to the ADC (see Figure 41)
for baseband applications. This configuration is common for
medical ultrasound systems.

However, the noise performance of most amplifiers is not
adequate to achieve the true performance of the AD9259. For
applications where SNR is a key parameter, differential transfor-
mer coupling is the recommended input configuration. Two
examples are shown in Figure 38 and Figure 39.

In any configuration, the value of the shunt capacitor, C, is
dependent on the input frequency and may need to be reduced
or removed.

2V p-p

DIFF

IS OPTIONAL.

49.9

0.1F

AGND

AVDD

ADT11WT
1:1 Z RATIO

VIN

ADC

AD9259

VIN+

0
08

Figure 38. Differential Transformer Coupled Configuration

for Baseband Applications

ADC

AD9259

2V p-p

2.2pF

0.1F

AVDD

ADT11WT

1:1 Z RATIO

16nH

0.1F

16nH

499

VIN+

VIN

059

-
04

Figure 39. Differential Transformer Coupled Configuration for IF Applications

Single-Ended Input Configuration

A single-ended input may provide adequate performance in
cost-sensitive applications. In this configuration, SFDR and
distortion performance degrade due to the large input common-
mode swing. If the application requires a single-ended input
configuration, ensure that the source impedances on each input
are well matched in order to achieve the best possible performance.
A full-scale input of 2 V p-p can still be applied to the ADC's VIN+
pin while the VIN- pin is terminated. Figure 40 details a typical
single-ended input configuration.

2V p-p

49.9

0.1µF

AVDD

1k 25

AVDD

VIN

ADC

AD9259

VIN+

DIFF

0
09

DIFF

IS OPTIONAL.

Figure 40. Single-Ended Input Configuration

AD8332

1.0k

374

187

0.1F

187

0.1F

10F

0.1F

1V p-p

0.1F

LNA

120nH

VGA

VOH

VIP

INH

22pF

LMD

VIN

LOP

LON

VOL

18nF

274

VIN

ADC

AD9259

VIN+

VREF

0
07

Figure 41. Differential Input Configuration Using the

AD8332

AD9259

Rev. 0 | Page 20 of 52

CLOCK INPUT CONSIDERATIONS

For optimum performance, the AD9259 sample clock inputs
(CLK+ and CLK-) should be clocked with a differential signal.
This signal is typically ac-coupled into the CLK+ and CLK- pins
via a transformer or capacitors. These pins are biased internally
and require no additional bias.

Figure 42 shows one preferred method for clocking the AD9259.
The low jitter clock source is converted from single-ended to
differential using an RF transformer. The back-to-back Schottky
diodes across the secondary transformer limit clock excursions
into the AD9259 to approximately 0.8 V p-p differential. This
helps prevent the large voltage swings of the clock from feeding
through to other portions of the AD9259 and preserves the fast
rise and fall times of the signal, which are critical to low jitter
performance.

0.1µF

SCHOTTKY

DIODES:

HSM2812

CLOCK

INPUT

100

CLK

CLK+

ADC

AD9259

MIN-CIRCUITS

ADT11WT, 1:1Z

XFMR

Figure 42. Transformer Coupled Differential Clock

If a low jitter clock is available, another option is to ac-couple a
differential PECL signal to the sample clock input pins as shown
in Figure 43. The

AD9510

AD9511

AD9512

AD9513

AD9514

AD9515

family of clock drivers offers excellent jitter performance.

CLOCK

INPUT

100

0.1µF

240

CLOCK

INPUT

CLK

RESISTORS ARE OPTIONAL.

CLK

CLK+

ADC

AD9259

05965

-
025

AD9510/AD9511/

AD9512/AD9513/

AD9514/AD9515

PECL DRIVER

Figure 43. Differential PECL Sample Clock

CLOCK

INPUT

100

0.1µF

50*

CLOCK

INPUT

LVDS DRIVER

CLK

50 RESISTORS ARE OPTIONAL

CLK

CLK+

ADC

AD9259

0596

026

AD9510/AD9511/

AD9512/AD9513/

AD9514/AD9515

Figure 44. Differential LVDS Sample Clock

In some applications, it is acceptable to drive the sample clock
inputs with a single-ended CMOS signal. In such applications,
CLK+ should be directly driven from a CMOS gate, and the
CLK- pin should be bypassed to ground with a 0.1 F capacitor
in parallel with a 39 k resistor (see Figure 45). Although the
CLK+ input circuit supply is AVDD (1.8 V), this input is
designed to withstand input voltages up to 3.3 V, making the
selection of the drive logic voltage very flexible.

CLOCK

INPUT

0.1µF

CMOS DRIVER

OPTIONAL

100

0.1µF

CLK

RESISTOR IS OPTIONAL.

CLK

CLK+

ADC

AD9259

059

65-

0
27

AD9510/AD9511/

AD9512/AD9513/

AD9514/AD9515

Figure 45. Single-Ended 1.8 V CMOS Sample Clock

CLOCK

INPUT

0.1µF

AD9510/AD9511/

AD9512/AD9513/

AD9514/AD9515

CMOS DRIVER

OPTIONAL

100

CLK

RESISTOR IS OPTIONAL.

0.1µF

CLK

CLK+

ADC

AD9259

059

-
0
28

Figure 46. Single-Ended 3.3 V CMOS Sample Clock

Clock Duty Cycle Considerations

Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals. As a result, these ADCs may
be sensitive to clock duty cycle. Commonly, a 5% tolerance is
required on the clock duty cycle to maintain dynamic performance
characteristics. The AD9259 contains a duty cycle stabilizer (DCS)
that retimes the nonsampling edge, providing an internal clock
signal with a nominal 50% duty cycle. This allows a wide range
of clock input duty cycles without affecting the performance of
the AD9259. When the DCS is on, noise and distortion perfor-
mance are nearly flat for a wide range of duty cycles. However,
some applications may require the DCS function to be off. If so,
keep in mind that the dynamic range performance can be affected
when operated in this mode. See the Memory Map section for
more details on using this feature.

The duty cycle stabilizer uses a delay-locked loop (DLL) to
create the nonsampling edge. As a result, any changes to the
sampling frequency require approximately 10 clock cycles
to allow the DLL to acquire and lock to the new rate.

AD9259

Rev. 0 | Page 21 of 52

Clock Jitter Considerations

High speed, high resolution ADCs are sensitive to the quality of the
clock input. The degradation in SNR at a given input frequency
(f

) due only to aperture jitter (t

) can be calculated by

SNR degradation = 20 × log 10 [1/2 × × f

× t

]

In this equation, the rms aperture jitter represents the root mean
square of all jitter sources, including the clock input, analog input
signal, and ADC aperture jitter specifications. IF undersampling
applications are particularly sensitive to jitter (see Figure 47).

The clock input should be treated as an analog signal in cases
where aperture jitter may affect the dynamic range of the AD9259.
Power supplies for clock drivers should be separated from the
ADC output driver supplies to avoid modulating the clock signal
with digital noise. Low jitter, crystal-controlled oscillators make
the best clock sources. If the clock is generated from another
type of source (by gating, dividing, or other methods), it should
be retimed by the original clock at the last step.

Refer to the

AN-501 Application Note

and the

AN-756

Application Note

for more in-depth information about jitter

performance as it relates to ADCs (visit

www.analog.com

100

1000

16 BITS

14 BITS

12 BITS

100

110

120

130

0.125ps

0.25ps

0.5ps
1.0ps
2.0ps

ANALOG INPUT FREQUENCY (MHz)

10 BITS

RMS CLOCK JITTER REQUIREMENT

NR (

)

059

-
03

Figure 47. Ideal SNR vs. Input Frequency and Jitter

Power Dissipation and Power-Down Mode

As shown in Figure 48, the power dissipated by the AD9259 is
proportional to its sample rate. The digital power dissipation
does not vary much because it is determined primarily by the
DRVDD supply and bias current of the LVDS output drivers.

CURR

(

ENCODE (MSPS)

250

300

350

450

500

400

100

140

120

200

180

160

(mW

)

DRVDD CURRENT

TOTAL POWER

AVDD CURRENT

-
0

Figure 48. Supply Current vs. f

SAMPLE

for f

= 10.3 MHz, f

SAMPLE

= 50 MSPS

AD9259

Rev. 0 | Page 22 of 52

By asserting the PDWN pin high, the AD9259 is placed in
power-down mode. In this state, the ADC typically dissipates
2 mW. During power-down, the LVDS output drivers are placed in
a high impedance state. The AD9259 returns to normal operating
mode when the PDWN pin is pulled low. This pin is both 1.8 V
and 3.3 V tolerant.

In power-down mode, low power dissipation is achieved by
shutting down the reference, reference buffer, PLL, and biasing
networks. The decoupling capacitors on REFT and REFB are
discharged when entering power-down mode and must be
recharged when returning to normal operation. As a result, the
wake-up time is related to the time spent in the power-down
mode; shorter cycles result in proportionally shorter wake-up
times. With the recommended 0.1 F and 2.2 F decoupling
capacitors on REFT and REFB, it takes approximately 1 sec to
fully discharge the reference buffer decoupling capacitors and
375 s to restore full operation.

There are a number of other power-down options available
when using the SPI port interface. The user can individually
power down each channel or put the entire device into standby
mode. This allows the user to keep the internal PLL powered
when fast wake-up times (~600 ns) are required. See the
Memory Map section for more details on using these features.

Digital Outputs and Timing

The AD9259 differential outputs conform to the ANSI-644 LVDS
standard on default power-up. This can be changed to a low power,
reduced signal option similar to the IEEE 1596.3 standard using
the SDIO/ODM pin or via the SPI. This LVDS standard can further
reduce the overall power dissipation of the device by approximately
17 mW. See the SDIO/ODM Pin section or Table 15 in the
Memory Map section for more information. The LVDS driver
current is derived on-chip and sets the output current at each
output equal
to a nominal 3.5 mA. A 100 differential termination resistor
placed at the LVDS receiver inputs results in a nominal 350 mV
swing at the receiver.

The AD9259 LVDS outputs facilitate interfacing with LVDS
receivers in custom ASICs and FPGAs that have LVDS capability
for superior switching performance in noisy environments.
Single point-to-point net topologies are recommended with a

100 termination resistor placed as close to the receiver as
possible. No far-end receiver termination and poor differential
trace routing may result in timing errors. It is recommended
that the trace length is no longer than 24 inches and that the
differential output traces are kept close together and at equal
lengths. An example of the FCO and data stream with proper
trace length and position can be found in Figure 49.

CH1 500mV/DIV = DCO

CH2 500mV/DIV = DATA

CH3 500mV/DIV = FCO

2.5ns/DIV

596

Figure 49. LVDS Output Timing Example in ANSI Mode (Default)

An example of the LVDS output using the ANSI standard (default)
data eye and a time interval error (TIE) jitter histogram with
trace lengths less than 24 inches on regular FR-4 material is
shown in Figure 50. Figure 51 shows an example of when the
trace lengths exceed 24 inches on regular FR-4 material. Notice
that the TIE jitter histogram reflects the decrease of the data eye
opening as the edge deviates from the ideal position. It is up to
the user to determine if the waveforms meet the timing budget
of the design when the trace lengths exceed 24 inches. Additional
SPI options allow the user to further increase the internal ter-
mination (increasing the current) of all four outputs in order to
drive longer trace lengths (see Figure 52). Even though this
produces sharper rise and fall times on the data edges and is less
prone to bit errors, the power dissipation of the DRVDD supply
increases when this option is used. Also notice in Figure 52 that
the histogram has improved. See the Memory Map section for
more details.

AD9259

Rev. 0 | Page 23 of 52

100

100ps

0ps

100ps

I
E J

I
T

AM (

i
t
s
)

500

1.0ns

0.5ns

0ns

0.5ns

1.0ns

RAM

(

)

EYE: ALL BITS

ULS: 10000/15600

5
965

-
04

Figure 50. Data Eye for LVDS Outputs in ANSI Mode with Trace Lengths Less

than 24 Inches on Standard FR-4

200

1.0ns

0.5ns

0ns

0.5ns

1.0ns

I
AG

RAM

(

)

EYE: ALL BITS

ULS: 9600/15600

100

150ps 100ps

50ps

0ps

50ps

100ps

150ps

I
E J

I
T

AM (

i
t
s
)

Figure 51. Data Eye for LVDS Outputs in ANSI Mode with Trace Lengths

Greater than 24 Inches on Standard FR-4

100

150ps 100ps

50ps

0ps

50ps

100ps

150ps

I
E

RAM

(

i
t
s)

200

400

200

400

1.0ns

0.5ns

0ns

0.5ns

1.0ns

(

)

EYE: ALL BITS

ULS: 9599/15599

5-04

Figure 52. Data Eye for LVDS Outputs in ANSI Mode with 100 Termination

on and Trace Lengths Greater than 24 Inches on Standard FR-4

The format of the output data is offset binary by default. An
example of the output coding format can be found in Table 8.
If it is desired to change the output data format to twos
complement, see the Memory Map section.

Table 8. Digital Output Coding

Code

(VIN+) - (VIN-), Input
Span = 2 V p-p (V)

Digital Output Offset Binary
(D11 ... D0)

16383

+1.00

11 1111 1111 1111

8192

0.00

10 0000 0000 0000

8191

-0.000122

01 1111 1111 1111

-1.00

00 0000 0000 0000

Data from each ADC is serialized and provided on a separate
channel. The data rate for each serial stream is equal to 14 bits
times the sample clock rate, with a maximum of 700 Mbps
(14 bits × 50 MSPS = 700 Mbps). The lowest typical conversion
rate is 10 MSPS. However, if lower sample rates are required for
a specific application, the PLL can be set up for encode rates
lower than 10 MSPS via the SPI. This allows encode rates as low
as 5 MSPS. See the Memory Map section to enable this feature.

AD9259

Rev. 0 | Page 24 of 52

Two output clocks are provided to assist in capturing data from
the AD9259. The DCO is used to clock the output data and is
equal to seven times the sampling clock (CLK) rate. Data is
clocked out of the AD9259 and must be captured on the rising
and falling edges of the DCO that supports double data rate

(DDR) capturing. The frame clock out (FCO) is used to signal
the start of a new output byte and is equal to the sampling clock
rate. See the timing diagram shown in Figure 2 for more
information.

Table 9. Flex Output Test Modes

Output Test
Mode Bit
Sequence

Pattern Name

Digital Output Word 1

Digital Output Word 2

Subject
to Data
Format
Select

0000

Off

(default)

N/A N/A N/A

0001 Midscale

short

1000 0000 (8-bit)
10 0000 0000 (10-bit)
1000 0000 0000 (12-bit)
10 0000 0000 0000 (14-bit)

Same Yes

0010 +Full-scale

short 1111 1111 (8-bit)

11 1111 1111 (10-bit)
1111 1111 1111 (12-bit)
11 1111 1111 1111 (14-bit)

Same Yes

0011 -Full-scale

short 0000 0000 (8-bit)

00 0000 0000 (10-bit)
0000 0000 0000 (12-bit)
00 0000 0000 0000 (14-bit)

Same Yes

0100 Checker

board

1010 1010 (8-bit)
10 1010 1010 (10-bit)
1010 1010 1010 (12-bit)
10 1010 1010 1010 (14-bit)

0101 0101 (8-bit)
01 0101 0101 (10-bit)
0101 0101 0101 (12-bit)
01 0101 0101 0101 (14-bit)

0101

PN sequence long

N/A N/A Yes

0110

PN sequence short

N/A N/A Yes

0111 One/zero

word

toggle

1111 1111 (8-bit)
11 1111 1111 (10-bit)
1111 1111 1111 (12-bit)
11 1111 1111 1111 (14-bit)

0000 0000 (8-bit)
00 0000 0000 (10-bit)
0000 0000 0000 (12-bit)
00 0000 0000 0000 (14-bit)

1000

User input

1001

One/zero bit toggle

1010 1010 (8-bit)
10 1010 1010 (10-bit)
1010 1010 1010 (12-bit)
10 1010 1010 1010 (14-bit)

N/A No

1010 1×

sync

0000 1111 (8-bit)
00 0001 1111 (10-bit)
0000 0011 1111 (12-bit)
00 0000 0111 1111 (14-bit)

N/A No

1011

One bit high

1000 0000 (8-bit)
10 0000 0000 (10-bit)
1000 0000 0000 (12-bit)
10 0000 0000 0000 (14-bit)

N/A No

1100 Mixed

frequency 1010 0011 (8-bit)

10 0110 0011 (10-bit)
1010 0011 0011 (12-bit)
10 1000 0110 0111 (14-bit)

N/A No

PN, or pseudorandom number, sequence is determined by the number of bits in the shift register. The long sequence is 23 bits and the short sequence is
9 bits. How the sequence is generated and utilized is described in the ITU O.150 standard. In general, the polynomial, X23 + X18 + 1 (long) and X9 + X5 + 1
(short), defines the pseudorandom sequence.

AD9259

Rev. 0 | Page 25 of 52

When using the serial port interface (SPI), the DCO phase can
be adjusted in 60° increments relative to the data edge. This
enables the user to refine system timing margins if required.
The default DCO timing, as shown in Figure 2, is 90° relative to
the output data edge.

An 8-, 10-, and 12-bit serial stream can also be initiated from
the SPI. This allows the user to implement and test compatibility
to lower resolution systems. When changing the resolution to
an 8-, 10-, or 12-bit serial stream, the data stream is shortened.
See Figure 3 for a 12-bit example.

When using the SPI, all of the data outputs can also be inverted
from their nominal state. This is not to be confused with
inverting the serial stream to an LSB-first mode. In default
mode, as shown in Figure 2, the MSB is represented first in the
data output serial stream. However, this can be inverted so that
the LSB is represented first in the data output serial stream (see
Figure 4).

There are 12 digital output test pattern options available that
can be initiated through the SPI. This is a useful feature when
validating receiver capture and timing. Refer to Table 9 for the
output bit sequencing options available. Some test patterns have
two serial sequential words and can be alternated in various
ways, depending on the test pattern chosen. It should be noted
that some patterns may not adhere to the data format select
option. In addition, customer user patterns can be assigned in
the 0x19, 0x1A, 0x1B, and 0x1C register addresses. All test mode
options can support 8- to 14-bit word lengths in order to verify
data capture to the receiver.

Please consult the Memory Map section for information on how
to change these additional digital output timing features through
the serial port interface or SPI.

SDIO/ODM Pin

This pin is for applications that do not require SPI mode operation.
The SDIO/ODM pin can enable a low power, reduced signal option
similar to the IEEE 1596.3 reduced range link output standard if
this pin and the CSB pin are tied to AVDD during device power-
up. This option should only be used when the digital output trace
lengths are less than 2 inches in length to the LVDS receiver. The
FCO, DCO, and outputs function normally, but the LVDS signal
swing of all channels is reduced from 350 mV p-p to 200 mV p-p.
This output mode allows the user to further lower the power on
the DRVDD supply. For applications where this pin is not used,
it should be tied low. In this case, the device pin can be left open,
and the 30 k internal pull-down resistor pulls this pin low. This
pin is only 1.8 V tolerant. If applications require this pin to be
driven from a 3.3 V logic level, insert a 1 k resistor in series
with this pin to limit the current.

Table 10. Output Driver Mode Pin Settings

Selected ODM

ODM Voltage

Resulting
Output Standard

Resulting
FCO and DCO

Normal

operation

10 k to AGND

ANSI-644

(default)

ANSI-644

(default)

ODM AVDD

Low power,
reduced signal
option

Low power,
reduced
signal
option

SCLK/DTP Pin

This pin is for applications that do not require SPI mode operation.
The serial clock/digital test pattern (SCLK/DTP) pin can enable
a single digital test pattern if this pin and the CSB pin are held
high during device power-up. When the DTP is tied to AVDD,
all the ADC channel outputs shift out the following pattern: 10
0000 0000 0000. The FCO and DCO outputs still work as usual
while all channels shift out the repeatable test pattern. This pattern
allows the user to perform timing alignment adjustments among
the FCO, DCO, and output data. For normal operation, this pin
should be tied to AGND through a 10 k resistor. This pin is
both 1.8 V and 3.3 V tolerant.

Table 11. Digital Test Pattern Pin Settings

Selected DTP

DTP Voltage

Resulting
D+ and D-

Resulting
FCO and DCO

Normal

operation

10 k to AGND

Normal

operation

Normal operation

DTP

AVDD

10 0000 0000
0000

Normal operation

Additional and custom test patterns can also be observed when
commanded from the SPI port. Consult the Memory Map
section to choose from the different options available.

CSB Pin

The chip select bar (CSB) pin should be tied to AVDD for
applications that do not require SPI mode operation. By tying
CSB high, all SCLK and SDIO information is ignored. This pin
is both 1.8 V and 3.3 V tolerant.

RBIAS Pin

To set the internal core bias current of the ADC, place a resistor
(nominally equal to 10.0 k) to ground at the RBIAS pin. The
resistor current is derived on-chip and sets the ADC's AVDD
current to a nominal 185 mA at 50 MSPS. Therefore, it is
imperative that at least a 1% tolerance on this resistor be used to
achieve consistent performance. If SFDR performance is not as
critical as power, simply adjust the ADC core current to achieve
a lower power. Figure 53 and Figure 54 show the relationship
between the dynamic range and power as the RBIAS resistance
is changed. Nominally, a 10.0 k value is used, as indicated by
the dashed line.

AD9259

Rev. 0 | Page 26 of 52

DR (

Bc)

RESISTANCE (k)

SNR

SFDR

NR (

Figure 53. SFDR vs. RBIAS

600

500

400

300

200

100

I
AV

DD (

RESISTANCE (k)

Figure 54. IAVDD vs. RBIAS

Voltage Reference

A stable and accurate 0.5 V voltage reference is built into the
AD9259. This is gained up by a factor of 2 internally, setting
V

REF

to 1.0 V, which results in a full-scale differential input span

of 2 V p-p. The V

REF

is set internally by default; however, the

VREF pin can be driven externally with a 1.0 V reference to
achieve more accuracy.

When applying the decoupling capacitors to the VREF, REFT,
and REFB pins, use ceramic low ESR capacitors. These capacitors
should be close to the ADC pins and on the same layer of the
PCB as the AD9259. The recommended capacitor values and
configurations for the AD9259 reference pin can be found in
Figure 55.

Table 12. Reference Settings

Selected
Mode

SENSE
Voltage

Resulting
VREF (V)

Resulting
Differential
Span (V p-p)

External

Reference

AVDD

N/A

2 × external

reference

Internal,

2 V p-p FSR

AGND to 0.2 V

1.0

2.0

Internal Reference Operation

A comparator within the AD9259 detects the potential at the
SENSE pin and configures the reference. If SENSE is grounded,
the reference amplifier switch is connected to the internal
resistor divider (see Figure 55), setting VREF to 1 V.

The REFT and REFB pins establish their input span of the ADC
core from the reference configuration. The analog input full-
scale range of the ADC equals twice the voltage at the reference
pin for either an internal or an external reference configuration.

If the reference of the AD9259 is used to drive multiple
converters to improve gain matching, the loading of the refer-
ence by the other converters must be considered. Figure 57
depicts how the internal reference voltage is affected by loading.

1µF

0.1µF

REF

SENSE

0.5V

REFT

0.1µF

2.2µF

0.1µF

REFB

SELECT

LOGIC

ADC

CORE

VIN

VIN+

Figure 55. Internal Reference Configuration

1µF

0.1µF

REF

SENSE

AVDD

0.5V

REFT

0.1µF

2.2µF

0.1µF

REFB

SELECT

LOGIC

ADC

CORE

VIN

VIN+

05965-

046

EXTERNAL

REFERENCE

OPTIONAL.

Figure 56. External Reference Operation

AD9259

Rev. 0 | Page 28 of 52

SERIAL PORT INTERFACE (SPI)

The AD9259 serial port interface allows the user to configure
the converter for specific functions or operations through a
structured register space provided inside the ADC. This gives
the user added flexibility and customization depending on the
application. Addresses are accessed via the serial port and can
be written to or read from via the port. Memory is organized
into bytes that can be further divided down into fields, as doc-
umented in the Memory Map section. Detailed operational
information can be found in the Analog Devices user manual

Interfacing to High Speed ADCs via SPI

There are three pins that define the serial port interface, or SPI,
to this particular ADC. They are the SCLK, SDIO, and CSB
pins. The SCLK (serial clock) is used to synchronize the read
and write data presented to the ADC. The SDIO (serial data
input/output) is a dual-purpose pin that allows data to be sent
to and read from the internal ADC memory map registers. The
CSB (chip select bar) is an active low control that enables or
disables the read and write cycles (see Table 13).

Table 13. Serial Port Pins

Pin Function
SCLK

Serial Clock. The serial shift clock in. SCLK is used to
synchronize serial interface reads and writes.

SDIO

Serial Data Input/Output. A dual-purpose pin. The
typical role for this pin is an input or output, depending
on the instruction sent and the relative position in the
timing frame.

CSB

Chip Select Bar (Active Low). This control gates the read
and write cycles.

The falling edge of the CSB in conjunction with the rising edge
of the SCLK determines the start of the framing sequence. During
an instruction phase, a 16-bit instruction is transmitted, followed
by one or more data bytes, which is determined by Bit Fields
W0 and W1. An example of the serial timing and its definitions
can be found in Figure 59 and Table 14. In normal operation,
CSB is used to signal to the device that SPI commands are to be
received and processed. When CSB is brought low, the device
processes SCLK and SDIO to process instructions. Normally,
CSB remains low until the communication cycle is complete.
However, if connected to a slow device, CSB can be brought
high between bytes, allowing older microcontrollers enough
time to transfer data into shift registers. CSB can be stalled
when transferring one, two, or three bytes of data. When W0
and W1 are set to 11, the device enters streaming mode and
continues to process data, either reading or writing, until the
CSB is taken high to end the communication cycle. This allows
complete memory transfers without having to provide additional
instructions. Regardless of the mode, if CSB is taken high in the
middle of any byte transfer, the SPI state machine is reset and
the device waits for a new instruction.

In addition to the operation modes, the SPI port can be
configured to operate in different manners. For applications
that do not require a control port, the CSB line can be tied and
held high. This places the remainder of the SPI pins in their
secondary mode as defined in the Serial Port Interface (SPI)
section. CSB can also be tied low to enable 2-wire mode. When
CSB is tied low, SCLK and SDIO are the only pins required for
communication. Although the device is synchronized during
power-up, caution must be exercised when using this mode to
ensure that the serial port remains synchronized with the CSB
line. When operating in 2-wire mode, it is recommended to use
a 1-, 2-, or 3-byte transfer exclusively. Without an active CSB
line, streaming mode can be entered but not exited.

In addition to word length, the instruction phase determines if
the serial frame is a read or write operation, allowing the serial
port to be used to both program the chip and read the contents
of the on-chip memory. If the instruction is a readback operation,
performing a readback causes the serial data input/output (SDIO)
pin to change direction from an input to an output at the
appropriate point in the serial frame.

Data can be sent in MSB- or LSB-first mode. MSB-first mode
is the default at power-up and can be changed by adjusting the
configuration register. For more information about this and
other features, see the user manual

Interfacing to High Speed

ADCs via SPI

HARDWARE INTERFACE

The pins described in Table 13 compose the physical interface
between the user's programming device and the serial port of
the AD9259. The SCLK and CSB pins function as inputs when
using the SPI interface. The SDIO pin is bidirectional, functioning
as an input during write phases and as an output during readback.

This interface is flexible enough to be controlled by either serial
PROMS or PIC mirocontrollers. This provides the user an
alternative method, other than a full SPI controller, to program
the ADC (see the

AN-812 Application Note

If the user chooses not to use the SPI interface, these pins serve
a dual function and are associated with secondary functions
when the CSB is strapped to AVDD during device power-up.
See the Theory of Operation section for details on which pin-
strappable functions are supported on the SPI pins.

For users who simply wish to operate the DUT without using
SPI, remove any connections from the CSB, SCLK/DTP, and
SDIO/OMD pins. By disconnecting these pins from the control
bus, the DUT can operate in its most basic operation. Each of
these pins has an internal termination and will float to its
respective level.

AD9259

Rev. 0 | Page 30 of 52

MEMORY MAP

READING THE MEMORY MAP TABLE

Each row in the memory map table has eight address locations.
The memory map is roughly divided into three sections: chip
configuration register map (Address 0x00 to Address 0x02), device
index and transfer register map (Address 0x05 and Address 0xFF),
and program register map (Address 0x08 to Address 0x25).

The left-hand column of the memory map indicates the register
address number in hexadecimal. The default value of this address is
shown in hexadecimal in the right-hand column. The Bit 7 (MSB)
column is the start of the default hexadecimal value given. For
example, Hexadecimal Address 0x09, Clock, has a hexadecimal
default value of 0x01. This means Bit 7 = 0, Bit 6 = 0, Bit 5 = 0,
Bit 4 = 0, Bit 3 = 0, Bit 2 = 0, Bit 1 = 0, and Bit 0 = 1, or 0000 0001
in binary. This setting is the default for the duty cycle stabilizer in
the on condition. By writing a 0 to Bit 6 at this address, the duty
cycle stabilizer turns off. For more information on this and other
functions, consult the user manual

Interfacing to High Speed

ADCs via SPI

RESERVED LOCATIONS

Undefined memory locations should not be written to except
when writing the default values suggested in this data sheet.
Addresses that have values marked as 0 should be considered
reserved and have a 0 written into their registers during power-up.

DEFAULT VALUES

Coming out of reset, critical registers are preloaded with default
values. These values are indicated in Table 15, where an X refers
to an undefined feature.

LOGIC LEVELS

An explanation of various registers follows: "Bit is set" is
synonymous with "bit is set to Logic 1" or "writing Logic 1 for
the bit." Similarly, "clear a bit" is synonymous with "bit is set to
Logic 0" or "writing Logic 0 for the bit."

AD9259

Rev. 0 | Page 31 of 52

Table 15. Memory Map Register

Addr.
(Hex) Parameter

Name

Bit 7
(MSB)

Bit 6

Bit 5

Bit 4 Bit

3 Bit

2 Bit

Bit 0
(LSB)

Default
Value
(Hex)

Default Notes/
Comments

Chip Configuration Registers

00 chip_port_config

LSB

first

1 = on
0 = off
(default)

Soft
reset
1 = on
0 = off
(default)

1 1 Soft

reset
1 = on
0 = off
(default)

LSB first
1 = on
0 = off
(default)

0 0x18

The

nibbles

should be
mirrored so that
LSB- or MSB-first
mode registers
correctly
regardless of
shift mode.

chip_id

8-bit Chip ID Bits 7:0

(AD9259 = 0x04), (default)

0x04
Read
only

Default is unique
chip ID. This is a
read-only
register.

chip_grade

Child ID 6:4
(identify device variants of Chip ID)
100 = 50 MSPS

X X X X Read

only

Child ID used to
differentiate
graded devices.

Device Index and Transfer Registers

05 device_index_A

Clock
Channel
DCO
1 = on
0 = off
(default)

Clock
Channel
FCO
1 = on
0 = off
(default)

Data
Channel
D
1 = on
(default)
0 = off

Data
Channel
C
1 = on
(default)
0 = off

Data
Channel
B
1 = on
(default)
0 = off

Data
Channel
A
1 = on
(default)
0 = off

0x0F

Bits are set to
determine which
on-chip device
receives the next
write command.

device_update

X X X X X X X SW

transfer
1 = on
0 = off
(default)

0x00 Synchronously

transfers data
from the master
shift register to
the slave.

ADC Functions

modes

Internal power-down mode
000 = chip run (default)
001 = full power-down
010 = standby
011 = reset

0x00 Determines

various generic
modes of chip
operation.

clock

X X X X X X X Duty

cycle
stabilizer
1 = on
(default)
0 = off

0x01 Turns

the

internal duty
cycle stabilizer
on and off.

test_io

User test mode
00 = off (default)
01 = on, single alternate
10 = on, single once
11 = on, alternate once

Reset PN
long gen
1 = on
0 = off
(default)

Reset
PN short
gen
1 = on
0 = off
(default)

Output test mode--see

Table 9

in the

Digital Outputs and Timing

section

0000 = off (default)
0001 = midscale short
0010 = +FS short
0011 = -FS short
0100 = checker board output
0101 = PN 23 sequence
0110 = PN 9
0111 = one/zero word toggle
1000 = user input
1001 = one/zero bit toggle
1010 = 1× sync
1011 = one bit high
1100 = mixed bit frequency
(format determined by output_mode)

0x00

When set, the
test data is
placed on the
output pins in
place of normal
data.

AD9259

Rev. 0 | Page 32 of 52

Addr.
(Hex)

Parameter Name

Bit 7
(MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0
(LSB)

Default
Value
(Hex)

Default Notes/
Comments

output_mode

0 = LVDS
ANSI
(default)
1 = LVDS
low
power,
(IEEE
1596.3

similar)

X X X Output

invert
1 = on
0 = off
(default)

00 = offset binary
(default)
01 = twos
complement

0x00 Configures

the

outputs and the
format of the
data.

15 output_adjust X

Output driver
termination
00 = none (default)
01 = 200
10 = 100
11 = 100

0x00 Determines

LVDS or other
output properties.
Primarily func-
tions to set the
LVDS span and
common-mode
levels in place of
an external
resistor.

16 output_phase X

0011 = output clock phase adjust
(0000 through 1010)
(Default: 180° relative to DATA edge)
0000 = 0° relative to DATA edge
0001 = 60° relative to DATA edge
0010 = 120° relative to DATA edge
0011 = 180° relative to DATA edge
0100 = 240° relative to DATA edge
0101 = 300° relative to DATA edge
0110 = 360° relative to DATA edge
0111 = 420° relative to DATA edge
1000 = 480° relative to DATA edge
1001 = 540° relative to DATA edge
1010 = 600° relative to DATA edge
1011 to 1111 = 660° relative to DATA edge

0x03

On devices that
utilize global
clock divide,
determines
which phase of
the divider
output is used to
supply the
output clock.
Internal latching
is unaffected.

user_patt1_lsb

B7 B6 B5 B4 B3 B2 B1 B0 0x00

User-defined
pattern, 1 LSB.

1A user_patt1_msb

B15 B14

B13 B12 B11 B10 B9 B8 0x00

User-defined
pattern, 1 MSB.

user_patt2_lsb

B7 B6 B5 B4 B3 B2 B1 B0 0x00

User-defined
pattern, 2 LSB.

1C user_patt2_msb

B15 B14

B13 B12 B11 B10 B9 B8 0x00

User-defined
pattern, 2 MSB.

21 serial_control LSB

first

1 = on
0 = off
(default)

X X

<10
MSPS,
low
encode
rate
mode
1 = on
0 = off
(default)

000 = 14 bits (default, normal bit
stream)
001 = 8 bits
010 = 10 bits
011 = 12 bits
100 = 14 bits

0x00 Serial

stream

control. Default
causes MSB first
and the native
bit stream
(global).

serial_ch_stat

X X X X X X Channel

output
reset
1 = on
0 = off
(default)

Channel
power-
down
1 = on
0 = off
(default)

0x00

Used to power
down individual
sections of a
converter (local).

AD9259

Rev. 0 | Page 33 of 52

Power and Ground Recommendations

When connecting power to the AD9259, it is recommended
that two separate 1.8 V supplies be used: one for analog (AVDD)
and one for digital (DRVDD). If only one supply is available, it
should be routed to the AVDD first and then tapped off and
isolated with a ferrite bead or a filter choke preceded by
decoupling capacitors for the DRVDD. The user can employ
several different decoupling capacitors to cover both high and
low frequencies. These should be located close to the point of
entry at the PC board level and close to the parts with minimal
trace length.

A single PC board ground plane should be sufficient when
using the AD9259. With proper decoupling and smart parti-
tioning of the PC board's analog, digital, and clock sections,
optimum performance is easily achieved.

Exposed Paddle Thermal Heat Slug Recommendations

It is required that the exposed paddle on the underside of the
ADC is connected to analog ground (AGND) to achieve the
best electrical and thermal performance of the AD9259. An
exposed continuous copper plane on the PCB should mate to
the AD9259 exposed paddle, Pin 0. The copper plane should
have several vias to achieve the lowest possible resistive thermal
path for heat dissipation to flow through the bottom of the PCB.
These vias should be solder filled or plugged.

To maximize the coverage and adhesion between the ADC and
PCB, partition the continuous copper plane by overlaying a
silkscreen on the PCB into several uniform sections. This provides
several tie points between the two during the reflow process.
Using one continuous plane with no partitions only guarantees
one tie point between the ADC and PCB. See Figure 60 for a
PCB layout example. For detailed information on packaging
and the PCB layout of chip scale packages, see the

AN-772

Application Note

, "A Design and Manufacturing Guide for the

Lead Frame Chip Scale Package (LFCSP)," at

www.analog.com

SILKSCREEN PARTITION

PIN 1 INDICATOR

059

65-

Figure 60. Typical PCB Layout

AD9259

Rev. 0 | Page 34 of 52

EVALUATION BOARD

The AD9259 evaluation board provides all of the support cir-
cuitry required to operate the ADC in its various modes and
configurations. The converter can be driven differentially through a
transformer (default) or through the

AD8332

driver. The ADC

can also be driven in a single-ended fashion. Separate power pins
are provided to isolate the DUT from the

AD8332

drive circuitry.

Each input configuration can be selected by proper connection
of various jumpers (see Figure 63 to Figure 67). Figure 61 shows
the typical bench characterization setup used to evaluate the ac
performance of the AD9259. It is critical that the signal sources
used for the analog input and clock have very low phase noise
(<1 ps rms jitter) to realize the optimum performance of the
converter. Proper filtering of the analog input signal to remove
harmonics and lower the integrated or broadband noise at the
input is also necessary to achieve the specified noise performance.

See Figure 63 to Figure 71 for the complete schematics and
layout diagrams that demonstrate the routing and grounding
techniques that should be applied at the system level.

POWER SUPPLIES

This evaluation board comes with a wall-mountable switching
power supply that provides a 6 V, 2 A maximum output. Simply
connect the supply to the rated 100 V ac to 240 V ac wall outlet
at 47 Hz to 63 Hz. The other end is a 2.1 mm inner diameter
jack that connects to the PCB at P503. Once on the PC board,
the 6 V supply is fused and conditioned before connecting to
three low dropout linear regulators that supply the proper bias
to each of the various sections on the board.

When operating the evaluation board in a nondefault condition,
L504 to L507 can be removed to disconnect the switching
power supply. This enables the user to bias each section of the
board individually. Use P501 to connect a different supply for

each section. At least one 1.8 V supply is needed with a 1 A current
capability for AVDD_DUT and DRVDD_DUT; however, it is
recommended that separate supplies be used for both analog
and digital. To operate the evaluation board using the VGA
option, a separate 5.0 V analog supply is needed. The 5.0 V
supply, or AVDD_5 V, should have a 1 A current capability. To
operate the evaluation board using the SPI and alternate clock
options, a separate 3.3 V analog supply is needed in addition to
the other supplies. The 3.3 V supply, or AVDD_3.3 V, should
have a 1 A current capability as well.

INPUT SIGNALS

When connecting the clock and analog source, use clean signal
generators with low phase noise, such as Rohde & Schwarz SMHU
or HP8644 signal generators or the equivalent. Use a 1 m, shielded,
RG-58, 50 coaxial cable for making connections to the evalu-
ation board. Enter the desired frequency and amplitude from the
ADC specifications tables. Typically, most ADI evaluation boards
can accept ~2.8 V p-p or 13 dBm sine wave input for the clock.
When connecting the analog input source, it is recommended
to use a multipole, narrow-band, band-pass filter with 50
terminations. ADI uses TTE, Allen Avionics, and K&L types of
band-pass filters. The filter should be connected directly to the
evaluation board if possible.

OUTPUT SIGNALS

The default setup uses the

HSC-ADC-FPGA

high speed

deserialization board to deserialize the digital output data and
convert it to parallel CMOS. These two channels interface
directly with the ADI standard dual-channel FIFO data capture
board (

HSC-ADC-EVALA-DC

). Two of the four channels can

then be evaluated at the same time. For more information on
channel settings on these boards and their optional settings,
visit

www.analog.com/FIFO

ROHDE & SCHWARZ,

SMHU,

2V p-p SIGNAL

SYNTHESIZER

ROHDE & SCHWARZ,

SMHU,

2V p-p SIGNAL
SYNTHESIZER

BAND-PASS

FILTER

XFMR

INPUT

CLK

CHA TO CHD

14-BIT

SERIAL

LVDS

2 CH

14-BIT

PARALLEL

CMOS

USB

CONNECTION

AD9259

EVALUATION BOARD

HSC-ADC-FPGA

HIGH SPEED

DESERIALIZATION

BOARD

HSC-ADC-EVALA-DC

FIFO DATA

CAPTURE

BOARD

RUNNING

ADC

ANALYZER

AND SPI

USER

SOFTWARE

1.8V

DD_DU

DD_3.

DD_DU

5.0V

DD_5V

1.8V

6V DC

2A MAX

WALL OUTLET

100V TO 240V AC

47Hz TO 63Hz

SWITCHING

POWER

SUPPLY

3.3V

_
F

3
V

3.3V

1.5V

3.3V

SPI

0
59

-
0
14

Figure 61. Evaluation Board Connection

AD9259

Rev. 0 | Page 35 of 52

DEFAULT OPERATION AND JUMPER SELECTION
SETTINGS

The following is a list of the default and optional settings or
modes allowed on the AD9259 Rev. A evaluation board.

POWER: Connect the switching power supply that is
supplied in the evaluation kit between a rated 100 V ac
to 240 V ac wall outlet at 47 Hz to 63 Hz and P503.

AIN: The evaluation board is set up for a transformer-
coupled analog input with optimum 50 impedance
matching out to 200 MHz (see Figure 62). For more
bandwidth response, the differential capacitor across the
analog inputs can be changed or removed. The common
mode of the analog inputs is developed from the center
tap of the transformer or AVDD_DUT/2.

I
T

(

)

FREQUENCY (MHz)

0
88

16

14

12

10

100

150

200

250

300

350

400

450

500

3dB CUTOFF = 200MHz

Figure 62. Evaluation Board Full Power Bandwidth

VREF: VREF is set to 1.0 V by tying the SENSE pin to
ground, R237. This causes the ADC to operate in 2.0 V p-p
full-scale range. A separate external reference option using
the

ADR510

ADR520

is also included on the evaluation

board. Simply populate R231 and R235 and remove C214.
Proper use of the VREF options is noted in the Voltage
Reference section.

RBIAS: RBIAS has a default setting of 10 k (R201) to
ground and is used to set the ADC core bias current. To
further lower the core power (excluding the LVDS driver
supply), simply change the resistor setting. However, per-
formance of the ADC will degrade depending on the resistor
chosen. See the RBIAS Pin section for more information.

CLOCK: The default clock input circuitry is derived from a
simple transformer-coupled circuit using a high bandwidth
1:1 impedance ratio transformer (T201) that adds a very
low amount of jitter to the clock path. The clock input is

50 terminated and ac-coupled to handle single-ended
sine wave types of inputs. The transformer converts the
single-ended input to a differential signal that is clipped
before entering the ADC clock inputs.

A differential LVPECL clock can also be used to clock the
ADC input using the

AD9515

(U202). Simply populate

R225 and R227 with 0 resistors and remove R217 and
R218 to disconnect the default clock path inputs. In addition,
populate C207 and C208 with a 0.1 F capacitor and remove
C210 and C211 to disconnect the default cloth path outputs.
The

AD9515

has many pin-strappable options that are set

to a default working condition. Consult the

AD9515

data

sheet for more information about these and other options.

If using an oscillator, two oscillator footprint options are

also available (OSC201) to check the ADC performance.
J205 gives the user flexibility in using the enable pin, which
is common on most oscillators.

PDWN: To enable the power-down feature, simply short
J201 to the on position (AVDD) on the PDWN pin.

SCLK/DTP: To enable the digital test pattern
on the digital outputs of the ADC, use J204. If J204 is tied to
AVDD during device power-up, Test Pattern 10 0000 0000
0000 will be enabled. See the SCLK/DTP Pin section for
details.

SDIO/ODM: To enable the low power, reduced signal option
similar to the IEEE 1595.3 reduced range link LVDS output
standard, use J203. If J203 is tied to AVDD during device
power-up, it enables the LVDS outputs in a low power,
reduced signal option from the default ANSI standard.
This option changes the signal swing from 350 mV p-p to
200 mV p-p, which reduces the power of the DRVDD supply.
See the SDIO/ODM Pin section for more details.

CSB: To enable the SPI information on the SDIO and
SCLK pins that is to be processed, simply tie J202 low in
the always enable mode. To ignore the SDIO and SCLK
information, tie J202 to AVDD.

Non-SPI Mode: For users who wish to operate the DUT
without using SPI, simply remove the J202, J203, and J204
jumpers. This disconnects the CSB, SCLK/DTP, and SDIO/
OMD pins from the control bus, allowing the DUT to operate
in its simplest mode. Each of these pins has internal termi-
nation and will float to its respective level.

D+, D-: If an alternative data capture method to the setup
described in Figure 61 is used, optional receiver terminations,
R206 to R211, can be installed next to the high speed back-
plane connector.

AD9259

Rev. 0 | Page 37 of 52

CHANNEL A
P101

AIN

VGA INPUT CONNECTION

2
3

5
4

T101

CM1

FB103

FB102

FB101

C104

2.2pF

VIN_A

P102

DNP

CM1

INH1

CH_A

AVDD_DUT

CH_A

R104

AVDD_DUT

C106

DNP

C107

0.1µF

C103

DNP

C105

DNP

C101

0.1µF

C102

0.1µF

E101

R161

499

R152

DNP

R113

DNP

R105

DNP

R110

R107

DNP

R106

DNP

R112

R111

R108

R101

DNP

R102

64.9

R103

R109

CHANNEL B
P103

AIN

2
3

5
4

T102

CM2

FB106

FB105

FB104

C111

2.2pF

VIN_B

P104

DNP

CM2

INH2

CH_B

AVDD_DUT

CH_B

R116

AVDD_DUT

C113

DNP

C114

0.1µF

C110

DNP

C112

DNP

C108

0.1µF

C109

0.1µF

E102

R162

499

R153

DNP

R124

DNP

R118

DNP

R122

R120

DNP

R119

DNP

R126

R125

R121

R114

DNP

R115

64.9

R117

R123

CHANNEL C
P105

AIN

2
3

5
4

T103

CM3

FB109

FB108

FB107

C118

2.2pF

VIN_C

P106

DNP

CM3

INH3

CH_C

AVDD_DUT

CH_C

R130

AVDD_DUT

C120

DNP

C121

0.1µF

C117

DNP

C119

DNP

C115

0.1µF

C116

0.1µF

E103

R163

499

R154

DNP

R137

DNP

R131

DNP

R136

R133

DNP

R132

DNP

R139

R138

R134

R127

DNP

R128

64.9

R129

R135

CHANNEL D
P107

AIN

2
3

5
4

T104

CM4

FB112

FB111

R143

C125

2.2pF

VIN_D

P108

DNP

CM4

INH4

CH_D

AVDD_DUT

CH_D

FB110

AVDD_DUT

C127

DNP

C128

0.1µF

C124

DNP

C126

DNP

R159

DNP

C122

0.1µF

C123

0.1µF

E104

R164

499

R155

DNP

R160

DNP

R151

DNP

R147

R145

DNP

R144

DNP

R150

R149

R146

R140

DNP

R141

64.9

R142

R148

R156

DNP

R157

DNP

AIN

R158

DNP

DNP: DO NOT POPULATE

0
15

Figure 63. Evaluation Board Schematic, DUT Analog Inputs

AD9259

Rev. 0 | Page 38 of 52

1µ

C220 0.

1
µ

C218 0.

1
µ

1µ

C22

1
µ

C222 0.

1
µ

D_3.

GND

_
P

0
B

1
B

RSE

S0
S1

S10

S2
S3
S4
S5
S6
S7
S8
S9

NCB

VRE

= D

;
2
7
,
2
8

NCO

DNP

CK CI

CUI

I
O

DRI

I
RCU

I
T

ABL

I
ON

1µ

214

215

C201

CB3

-
3
C

C20

1
µ

DNP

1µ

209

1
µ

DNP

C215 0.

1
µ

DNP

211

1
µ

210

1
µ

202

0
1

201

203

DD_3

.
3V

I
G

NAL

DD_

3
V

;
4,

17,

20,

,

24,

26,

951

CR20

220 DNP

R24

R243 100

R24

100

201

1µ

R213 49.

9
k

R216 0

0
DNP

219 DNP

S0
S1
S2
S3
S4
S5
S6
S7
S8
S9

DD_

3
V

_3.

203

DD_3

.
3V

ND'

R24

DNP

R24

DD_3

.
3V

DD_3

.
3V

DD_3

.
3V

DD_3

.
3V

DD_3

.
3V

DD_3

.
3V

R24

DNP

R24

DNP

R24

R25

DNP

R25

DNP

R25

DNP

R25

DNP

DD_

R25

DNP

R26

DNP

R26

DNP

R26

DNP

NDAB1

NDA

NDAB2

NDAB3

NDAB4

NDAB5

NDAB6

NDAB7

NDAB8

NDAB9

NDCD1

NDCD

NDCD2

NDCD3

NDCD4

NDCD5

NDCD6

NDCD7

NDCD8

NDCD9

146

916

9_1

05 T

211

I
N

I
O

I
GI

L O

TPU

B3_

_CHB

_
C

B2_

CHA

B1_

CHA

_
CHA

CHA

R206 DNP

R211 DNP

R210 DNP

R209 DNP

R208 DNP

0
2

R207 DNP

_
C

C10

CHD

CHC

CHB

CHA

_
C

B4_

CHB

NAB

K+

D+A

D+B

D+C

D+D

DA

DB

DC

DD

DCO

DRG

DRV

FCO+
FCO

RBIAS

REF

/
D

I
O

/
O

SENSE

VIN

VINB

VINC

VIN

VREF

AVD

AVDD

DRG

NCE

I
NG

204

1
µ

202

2
µ

201

1
µ

R205

10k

R203

100k

R204

100k

J
201

24
23

22
21

45
46

43
44

201

D925

9 L

R202 100

B_DU

J
202

I
O

_
O

J
2
0
3

_
D

J
2
0
4

2
0
1

1
0
k

AVDD

_DU

CHA

CHB

CHC

CHD

CHA

CHB

CHC

DCO
DCO

FCO
FCO

_
D

AVDD

_DU

AVDD

_DU

VSENSE_

I
N

_
A

VIN

I
N

_
A

VIN_B

VREF

_
D

CHD

_
D

I
N

_
D

VIN_C

I
N

_
D

2
0
3

1
V

0
.
5
V

2
1
4

W

I
N

0
.
5
V

(
1
+

2
3
2
/
R

2
3
3
)

I
R

I
T

2
1
2

0
.
1
µ

2
2
9

4
.
9
9
k

2
1
4

1
µ

2
1
3

0
.
1
µ

2
3
0

1
0
k

2
3
1

_
D

2
2
8

4
7
0
k

2
3
4

2
3
5

2
3
6

2
3
7

_
D

AVDD_DUT

I
M

/
N

GND

5
1
0
/
2
0

1
V

2
3
2

2
3
3

2
1
7

2
1
8

2
2
5

2
2
6

4
9
.
9

2
2
7

2
3
8

2
3
9

1
0
k

2
0
6

0
.
1
µ

2
2
3

2
2
4

2
2
2

4
.
0
2
k

R266

100k

R267

100k

I
P

I
N

(
D

)

:

D

I
O

059

65-

Figure 64. Evaluation Board Schematic, DUT, VREF, Clock Inputs, and Digital Output Interface

AD9259

Rev. 0 | Page 39 of 52

R DO

NABL

(
0
V T

1
V

I
SA

E P

)

EXTERNAL VARIABLE GAIN DRIVE

VARIABLE GAIN CIRCUIT

(0V TO 1.0V DC)

R319

10k

JP
301

GND

R320

39k

AVDD_5V

I
N

RANG

.
25V

I
N

RANG

R315

10k

L310

120nH

C322

0.018µF

C317

0.018µF

R316

274

R317

274

C312

0.1µF

C325

0.1µF

C313

0.1µF

C314

0.1µF

L309

120nH

C318

22pF

C321

0.1µF

C320

0.1µF

C316

0.1µF

R318

10k

C323

22pF

C319

0.1µF

C324

0.1µF

INH4

INH3

DD_5V

C326

10µF

C315

10µF

I
O

NAL

A DRI

RCUI

R CHANN

C AND D

C311

0.1µF

R312

10k

R313

10k

DNP

C303

DNP

L304

R303

DNP

L308

R304

DNP

L306

L305

L302

L303

L307

C308

0.1µF

C307

0.1µF

C306

0.1µF

C305

0.1µF

R310

187

R309

187

R308

187

R307

187

C302

DNP

L301

C301

DNP

R305

374

R306

374

CH_C

CH_D

CH_C

DD_5V

C304

DNP

R301

DNP

R302

DNP

16 VG

COM1

COM2

ENBL

ENBV

GAIN

HILO

I
NH1

I
NH2

LMD

LOP1

LOP2

MODE

RCLMP

VCM1

VCM2

VIN1

VIN2

VIP1

VIP2

AD8332

R311

10k

DNP

R314

10k

DNP

C310

0.1µF

C309

1000pF

I
N

I
N =

±50

I
N =

H =

±7

PIN

I
V

E G

I
N

PE =

.
0
V

I
VE G

I
N

PE =

.
2
5
V T

.
0
V

U301

POPULATE L301 TO L308 WITH
0 RESISTORS OR DESIGN
YOUR OWN FILTER.

DNP: DO NOT POPULATE

0
17

Figure 65. Evaluation Board Schematic, Optional DUT Analog Input Drive

AD9259

Rev. 0 | Page 40 of 52

MOD

EPI

POSI

TIVE G

AIN

SLO

PE=

1.0

NEG

IVE G

AIN

SLO

PE=

2.2

5V-5

.0V

HIL

HI G

AIN

RAN

=2.

25V

-5.

GAI

NRA

NGE

=0V

1.0V

R41

1
0

120

C420

0.018

µF

8µ

C41

1µ

425

1µ

1
µ

424

1µ

0
9

1
20n

418

22p

C41

1µ

C41

1µ

C41

1
µ

417

22p

1µ

I
NH2

I
NH1

AVDD_

10µ

OPT

ION

RIV

ECI

RCUI

CHAN

NEL

ANDB

409

1µ

412

403

DNP

404 0

408 0

404

DNP

0
6

405

0
2

0
3

0
7

408

1µ

407

1µ

C40

1µ

405

1µ

R40

187

408

R40

C402 DN

401

DNP

374

406

CH_A

CH_B

CH_A

AVD

D_5V

AVD

D_5V

AVD

D_5V

404

DNP

R40

DNP

INH

LMD

LON

LOP

VOH

VOL

VPS1

VPS2

VPSV

401

COM

R41

10k

DNP

412

1µ

C41

100

RCL

HILO

PIN

=LO

=±

50m

HIL

=±

75m

(0V

R416

274

LATE

L401

TOL4

WITH

RESI

STO

DESI

URO

FIL

C Y2

I
CI

RCU

I
T

I
F

I
O

_
O

D_D

431 1k

R43

D_3

.
3
V

NC7

0
7

R42

10k

D_D

SET/

0
1

3
.
3
V

I
O

D_3

.
3
V

= P

MMI

_
5
V

D_5

_3.

J
402

1µ

R418

4.75k

I
C1

629

419

CR4

EMO

VE W

OGR

G P

I
C

(
U

4
0
2
)

R427

R420

R428

R426

SDO

SDI_

SCL

K_CHA

CSB1

_CHA

C42

1µ

_
D

_
DU

D_D

C Y2

404

430

10k

R42

10k

NC7

1
6

1µ

PIC PROGRAMMING HEADER

MCLR/GP3

GP0

GP1

PICVCC

MCLR/GP3

GP0

GP1

PICVCC

J401

0
1

, D

423

,
DNP

422

,
DNP

OPTIONAL

P: D

65-

0
18

Figure 66. Evaluation Board Schematic, Optional DUT Analog Input Drive and SPI Interface (Continued)

AD9259

Rev. 0 | Page 41 of 52

I
NG

NNE

D T

ION

.
0
V

.
8
V

.
3
V

501

_
A

_AV

502

DUT

_AV

DUT

_DRV

C509 0.

1µ

C50

503

10µ

501

10µ

DD_DU

DD_DUT

1
µ

C50

1µ

C507

C50

1
µ

DD_5V

10µ

0
4

0
2

10µ

C50

DD_3.

10µ

0
8

I
NG

ACI

DD_3.

1
µ

C524

1µ

C525

C521 0.

1
µ

C531 0.

1µ

C530 0.

1µ

2
9

1µ

2
2

1µ

C52

1
µ

C527 0.

1
µ

C52

1
µ

1µ

1
7

1µ

C516

C518 0.

1µ

2
0

1µ

C519 0.

1µ

C523 0.

1µ

DRV

_
D

_DUT

DD_5V

DC110F

PPL

Y I

6V,

503

C501

501

D502 3A SH

_
R

-
214

D501 S

2
A_RE

2A DO

-
2
14AA

R501

CHO

_CO

I
L

CR501

R501 261

PWR

_
I
N

GND

3333

9AK

-
5

U50

333

39AKC

-
3
.
3

U502

U501

3333

9AK

-
1
.
8

U503

3333

9AK

-
1
.
8

505

10µ

504

1
5

1µ

C513 1µ

C512

1µ

C514

1µ

_
I
N

_
AV

_
DRV

_AV

_
A

_
I
N

C53

1µ

C53

1µ

C53

1µ

C533 1µ

507

10µ

506

10µ

0
59

-
01

Figure 67. Evaluation Board Schematic, Power Supply Inputs

AD9259

Rev. 0 | Page 46 of 52

Table 16. Evaluation Board Bill of Materials (BOM)

Item

Qnty.
per
Board REFDES

Device

Pkg.

Value

Mfg.

Part

Number

1 1 AD9259LFCSP_REVA

PCB

PCB PCB

2 75 C101, C102, C107,

C108, C109, C114,
C115, C116, C121,
C122, C123, C128,
C201, C203, C204,
C205, C206, C210,
C211, C212, C213,
C216, C217, C218,
C219, C220, C221,
C222, C223, C224,
C310, C311, C312,
C313, C314, C316,
C319, C320, C321,
C324, C325, C409,
C410, C412, C414,
C416, C417, C419,
C422, C423, C424,
C425, C427, C428,
C429, C503, C505,
C507, C509, C516,
C517, C518, C519,
C520, C521, C522,
C523, C524, C525,
C526, C527, C528,
C529, C530, C531

Capacitor 402 0.1 F, ceramic,

X5R, 10 V, 10% tol

Panasonic ECJ-0EB1A104K

3 4 C104, C111, C118,

C125

Capacitor 402 2.2 pF, ceramic,

COG, 0.25 pF tol,
50 V

Murata GRM1555C1H2R2GZ01B

4 4 C315, C326, C413,

C426

Capacitor 805 10 F, 6.3 V ±10%

ceramic, X5R

AVX 08056D106KAT2A

5 1 C202

Capacitor 603 2.2 F, ceramic,

X5R, 6.3 V, 10% tol

Panasonic ECJ-1VB0J225K

6 2 C309,

C411

Capacitor 402 1000 pF, ceramic,

X7R, 25 V, 10% tol

Kemet C0402C102K3RACTU

7 4 C317, C322, C415,

C420

Capacitor 402 0.018 F, ceramic,

X7R, 16 V, 10% tol

AVX 0402YC183KAT2A

8 4 C318, C323, C418,

C421

Capacitor 402 22 pF, ceramic,

NPO, 5% tol, 50 V

Kemet C0402C220J5GACTU

9 1 C501

Capacitor 1206 10 F, tantalum,

16 V, 20% tol

Rohm TCA1C106M8R

10 9

C214, C512, C513,
C514, C515, C532,
C533, C534, C535

Capacitor 603 1 F, ceramic, X5R,

6.3 V, 10% tol

Panasonic ECJ-1VB0J105K

11 8

C305, C306, C307,
C308, C405, C406,
C407, C408

Capacitor 805 0.1 F, ceramic,

X7R, 50 V, 10% tol

AVX 08055C104KAT2A

12 4

C502, C504, C506,
C508

Capacitor 603 10 F, ceramic,

X5R, 6.3 V, 20% tol

Panasonic ECJ-1VB0J106M

13 1

CR201

Diode

SOT-23 30 V, 20 mA, dual

Schottky

Agilent
Technologies

HSMS2812

14 2

CR401,

CR501

LED

603

Green, 4 V, 5 m
candela

Panasonic LNJ306G8TRA

D502

Diode

DO-214AB

3 A, 30 V, SMC

Micro
Commercial Co.

SK33MSCT

D501

Diode

DO-214AA

2 A, 50 V, SMC

Micro
Commercial Co.

S2A

AD9259

Rev. 0 | Page 47 of 52

Item

Qnty.
per
Board REFDES

Device

Pkg.

Value

Mfg.

Part

Number

17 1

F501

Fuse

1210 6.0 V, 2.2 A trip-

current resettable
fuse

Tyco/Raychem NANOSMDC110F-2

18 1

FER501

Choke

Coil 2020 10 H, 5 A, 50 V,

190 @ 100 MHz

Murata DLW5BSN191SQ2L

19 12 FB101, FB102, FB103,

FB104, FB105, FB106,
FB107, FB108, FB109,
FB110, FB111, FB112

Ferrite bead

603

10 , test freq
100 MHz, 25% tol,
500 mA

Murata BLM18BA100SN1

20 1

JP301

Connector 2-pin 100 mil header

jumper, 2-pin

Samtec TSW-102-07-G-S

21 2

J205,

J402

Connector 3-pin 100 mil header

jumper, 3-pin

Samtec TSW-103-07-G-S

J201 to J204

Connector

12-pin

100 mil header
male, 4 × 3 triple
row straight

Samtec TSW-104-08-G-T

23 1

J401

Connector 10-pin 100 mil header,

male, 2 × 5 double
row straight

Samtec TSW-105-08-G-D

24 8

L501, L502, L503, L504,
L505, L506, L507, L508

Ferrite bead

1210

10 H, bead core
3.2 × 2.5 × 1.6
SMD, 2 A

Panasonic-ECG EXC-CL3225U1

L309, L310, L409, L410

Inductor

402

120 nH, test freq
100 MHz, 5% tol,
150 mA

Murata LQG15HNR12J02B

26 16 L301, L302, L303, L304,

L305, L306, L307, L308,
L401, L402, L403, L404,
L405, L406, L407, L408

Resistor

805

0 , 1/8 W, 5% tol

Panasonic

ERJ-6GEY0R00V

27 1

OSC201

Oscillator

SMT

Clock oscillator,
50.00 MHz, 3.3 V

CTS REEVES

CB3LV-3C-50M0000-T

28 5

P101, P103, P105,
P107, P201

Connector SMA Side-mount SMA

for 0.063" board
thickness

Johnson
Components

142-0711-821

29 1

P202

Connector HEADER

1469169-1, right
angle 2-pair,
25 mm, header
assembly

Tyco 1469169-1

30 1

P503

Connector 0.1",

PCMT

RAPC722, power
supply connector

Switchcraft SC1153

31 15 R201, R205, R214,

R215, R221, R239,
R312, R315, R318,
R411, R414, R417,
R425, R429, R430

Resistor 402 10 k, 1/16 W,

5% tol

Panasonic ERJ-2GEJ103X

32 14 R103, R117, R129,

R142, R216, R217,
R218, R223, R224,
R237, R420, R426,
R427, R428

Resistor 402 0 , 1/16 W,

5% tol

Panasonic ERJ-2GE0R00X

33 4

R102, R115, R128,
R141

Resistor 402 64.9 , 1/16 W,

1% tol

Panasonic ERJ-2RKF64R9X

34 4

R104, R116, R130,
R143

Resistor 603 0 , 1/10 W,

5% tol

Panasonic ERJ-3GEY0R00V

AD9259

Rev. 0 | Page 48 of 52

Item

Qnty.
per
Board REFDES

Device

Pkg.

Value

Mfg.

Part

Number

35 15 R109, R111, R112,

R123, R125, R126,
R135, R138, R139,
R148, R149, R150,
R431, R432, R433

Resistor 402 1 k, 1/16 W,

1% tol

Panasonic ERJ-2RKF1001X

36 8

R108, R110, R121,
R122, R134, R136,
R146, R147

Resistor 402 33 , 1/16 W, 5%

tol

Panasonic ERJ-2GEJ330X

37 4

R161, R162, R163,
R164

Resistor 402 499 , 1/16 W,

1% tol

Panasonic ERJ-2RKF4990X

38 3

R202,

R203,

R204

Resistor

402

100 k, 1/16 W,
1% tol

Panasonic ERJ-2RKF1003X

39 1

R222

Resistor

402

4.02 k, 1/16 W,
1% tol

Panasonic ERJ-2RKF4021X

40 1

R213

Resistor

402

49.9 , 1/16 W,
0.5% tol

Susumu RR0510R-49R9-D

41 1

R229

Resistor

402

4.99 k, 1/16 W,
5% tol

Panasonic ERJ-2RKF4991X

42 2

R230,

R319

Potentiometer

3-lead 10 k, Cermet

trimmer
potentiometer,
18 turn top adjust,
10%, 1/2 W

BC
Components

CT-94W-103

43 1

R228

Resistor

402

470 k, 1/16 W,
5% tol

Yageo America

9C04021A4703JLHF3

44 1

R320

Resistor

402

39 k, 1/16 W,
5% tol

Susumu RR0510P-393-D

45 8

R307, R308, R309,
R310, R407, R408,
R409, R410

Resistor 402 187 , 1/16 W,

1% tol

Panasonic ERJ-2RKF1870X

46 4

R305, R306, R405,
R406

Resistor 402 374 , 1/16 W,

1% tol

Panasonic ERJ-2RKF3740X

47 4

R316, R317, R415,
R416

Resistor 402 274 , 1/16 W,

1% tol

Panasonic ERJ-2RKF2740X

48 11 R245, R247, R249,

R251, R253, R255,
R257, R259, R261,
R263, R265

Resistor

201

0 , 1/20 W, 5% tol

Panasonic

ERJ-1GE0R00C

49 4

R418

Resistor

402

4.75 k, 1/16 W,
1% tol

Panasonic ERJ-2RKF4751X

50 1

R419

Resistor

402

261 , 1/16 W,
1% tol

Panasonic ERJ-2RKF2610X

51 1

R501

Resistor

603

261 , 1/16 W,
1% tol

Panasonic ERJ-3EKF2610V

52 2

R240,

R241

Resistor

402

243 , 1/16 W,
1% tol

Panasonic ERJ-2RKF2430X

53 2

R242,

R243

Resistor

402

100 , 1/16 W,
1% tol

Panasonic ERJ-2RKF1000X

54 1

S401

Switch

SMD

LIGHT TOUCH,
100GE, 5 mm

Panasonic EVQ-PLDA15

55 5

T101, T102, T103, T104,
T201

Transformer CD542 ADT1-1WT, 1:1

impedance ratio
transformer

Mini-Circuits ADT1-1WT

56 2

U501,

U503

SOT-223

ADP33339AKC-1.8,
1.5 A, 1.8 V LDO
regulator

ADI ADP33339AKC-1.8

Part Number AD9259

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