High Performance, 12-Bit, 12-Channel

Output Decimating, LCD DecDriver®

Preliminary Technical Data

AD8387

Rev. PrA

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700

www.analog.com

Fax: 781.461.3113

FEATURES

High accuracy, high resolution voltage outputs

12-bit input resolution
Laser-trimmed outputs

Fast settling, high voltage drive

35 ns settling time to 0.25% into 150 pF load
Slew rate 420 V/s
Outputs to within 1.3 V of supply rails

High update rates

Fast, 120 MHz clock

Programmable video reference (brightness), offset, and

full-scale (contrast) output levels

Flexible logic

INV bit reverses polarity of video signal
R/L reverses loading order of data
ISW selects frame/row or column inversion
DSW selects single or dual data bus mode

Output short-circuit protection
3.3 V logic, TBD, -18 V analog supplies
Available in 80-lead, 12 mm × 12 mm, TQFP E-pad

APPLICATIONS

LCD analog column driver

FUNCTIONAL BLOCK DIAGRAM

VID6

VID7

VID8

VID9

VID10

VID11

TWO-

STAGE

LATCH

TWO-

STAGE

LATCH

TWO-

STAGE

LATCH

TWO-

STAGE

LATCH

TWO-

STAGE

LATCH

TWO-

STAGE

LATCH

DAC

VID0

VID1

VID2

VID3

VID4

VID5

TWO-

STAGE

LATCH

TWO-

STAGE

LATCH

TWO-

STAGE

LATCH

TWO-

STAGE

LATCH

TWO-

STAGE

LATCH

TWO-

STAGE

LATCH

DAC

SEQUENCE

CONTROL

XFR

CLK

DSW

R/L

SCALING

CONTROL

DBB(0:11)

DBA(0:11)

VRH VRL

INV

ISW

TSW

THERMAL

SWITCH

GSW

G-MODE

SWITCH

BIAS

BYP

05653-001

AD8387

Figure 1.

GENERAL DESCRIPTION

The AD8387 DecDriver provides a fast, 12 bit, latched,
decimating dual digital input, which drives 12 high voltage
outputs. Twelve-bit input words are loaded into 12 separate high
speed, bipolar DACs sequentially. Flexible digital input format
allows more than one AD8387 to be used in parallel for higher
resolution displays. The output signal can be adjusted for dc
reference, signal inversion, and contrast for maximum
flexibility.

The AD8387 is fabricated on ADI's fast bipolar, 26 V XFCB
process, providing fast input logic, bipolar DACs with trimmed
accuracy and fast settling, high voltage, precision drive
amplifiers on the same chip.

The AD8387 dissipates TBD W nominal static power. The
AD8387 is offered in an 80-lead TQFP E-pad package and
operates over the commercial temperature range of 0°C to
+85°C.

AD8387

Preliminary Technical Data

Rev. PrA | Page 2 of 16

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Absolute Maximum Ratings............................................................ 5

Exposed Paddle............................................................................. 5

Overload Protection..................................................................... 5

Maximum Power Dissipation ..................................................... 5

Operating Temperature Range ................................................... 5

ESD Caution.................................................................................. 5

Pin Configuration and Function Descriptions............................. 6

Typical Performance Characteristics ............................................. 8

Timing Diagrams.............................................................................. 9

Single Data Bus Configuration, DSW = Low ........................... 9

Dual Data Bus Configuration, DSW = High .......................... 10

Functional Description .................................................................. 12

Reference and Control Input Description............................... 12

Theory of Operation ...................................................................... 13

Transfer Function and Analog Output Voltage...................... 13

Accuracy ...................................................................................... 13

Applications..................................................................................... 14

Optimized Reliability with the Thermal Switch .................... 14

Initial Power-Up After Assembly or Repair............................ 14

Power-Up During Normal Operation ..................................... 14

Operation In High Ambient Temperature.............................. 14

Power Supply Sequencing ......................................................... 14

Power-On Sequence................................................................... 14

Power-Off Sequence................................................................... 14

Grounded Output Mode During Power-Off .......................... 14

PCB Design for Optimized Thermal Performance ............... 14

Thermal Pad Design .................................................................. 15

Thermal via Structure Design .................................................. 15

AD8387 PCB Design Recommendations ............................... 15

Outline Dimensions ....................................................................... 16

Ordering Guide .......................................................................... 16

REVISION HISTORY

8/05--Revision PrA: Initial Version

Preliminary Technical Data

AD8387

Rev. PrA | Page 3 of 16

SPECIFICATIONS

25°C, AVCC = 15.5 V, DVCC = 3.3 V, VRH = 9.5 V, VRL = 7 V, T

A MIN

= 0°C, T

A MAX

= 85°C, unless otherwise noted.

Table 1.

Parameter

Conditions

Min

Typ

Max

Unit

VIDEO DC PERFORMANCE

A MIN

to T

A MAX

VDE--Differential Error Voltage

@ DAC Code 0

TBD

@ DAC Code 1024

TBD

@ DAC Code 2048

TBD

@ DAC Code 3072

TBD

@ DAC Code 4095

TBD

VCME--Common-Mode Error Voltage

@ DAC Code 0

TBD

@ DAC Code 1024

TBD

@ DAC Code 2048

TBD

@ DAC Code 3072

TBD

@ DAC Code 4095

TBD

VDE--VDE Matching

@ DAC Code 0

TBD

@ DAC Code 1024

TBD

@ DAC Code 2048

TBD

@ DAC Code 3072

TBD

@ DAC Code 4095

TBD

V--Channel Matching

@ DAC Code 0

TBD

@ DAC Code 1024

TBD

@ DAC Code 2048

TBD

@ DAC Code 3072

TBD

@ DAC Code 4095

TBD

DNL

TBD

LSB

VIDEO OUTPUT DYNAMIC PERFORMANCE

A MIN

to T

A MAX

, V

= 5 V step, C

= 150 pF

Data Switching Slew Rate

20% to 80%

420

V/s

Invert Switching Slew Rate

20% to 80%

570

V/s

Data Switching Settling Time to 1%

TBD

Data Switching Settling Time to 0.25%

TBD

Invert Switching Settling Time to 1%

TBD

Invert Switching Settling Time to 0.25%

250

Invert Switching Overshoot

CLK and Data Feedthrough

TBD

mV p-p

All-Hostile Crosstalk

Amplitude

TBD

mV p-p

Glitch Duration

TBD

DAC Transition Glitch Energy

DAC Code 2047 to 2048

TBD

nV-s

VIDEO OUTPUT CHARACTERISTICS

Output Voltage Swing

AVCC - VOH, VOL - AGND

1.1

1.3

Output Voltage--Grounded Mode

0.06

TBD

Data Switching Delay: t

50% of VIDx

12.5 14.5

16.5

INV Switching Delay: t

50% of VIDx

12.2 14.2

16.2

Output Current

100

Output Resistance

REFERENCE INPUTS

VRL Range

VRH VRL

5.25

AVCC - 4

VRH Range

VRH VRL

VRL

VRL + 2.75

VRH to VRL Range

TBD

2.75

VRH Input Resistance

TBD

VRL Input Current

To VRL

TBD

VRH Input Current

TBD

AD8387

Preliminary Technical Data

Rev. PrA | Page 4 of 16

Parameter

Conditions

Min

Typ

Max

Unit

RESOLUTION

Coding

Binary

Bits

DIGITAL INPUT CHARACTERISTICS

CLK Frequency

DSW = high dual bus mode

120

MHz

DSW = low single bus mode

MHz

CLK to Data Setup Time: t

CLK to XFR Setup Time: t

CLK to Data Hold Time: t

CLK to XFR Hold Time: t

CLK High Time: t

DSW = high dual bus mode

3.5

CLK Low Time: t

DSW = high dual bus mode

3.5

CLK High Time: t

DSW = low single bus mode

3.5

CLK Low Time: t

DSW = low single bus mode

3.5

TBD

TSW

333

XFR

TBD

-1

TSW

-1.3

XFR

-2

0.8

1.65

POWER SUPPLIES

DVCC, Operating Range

3.3

3.6

DVCC, Quiescent Current

TBD

AVCC Operating Range

TBD

AVCC Quiescent Current

TBD

OPERATING TEMPERATURE

Ambient Temperature Range, T

°C

VDE = differential error voltage. VCME = common-mode error voltage. VDE = VDE matching between outputs. V = maximum deviation between outputs. Full-scale

output voltage = VFS = 2 × (VRH - VRL). See the Accuracy section.

Measured on two outputs differentially as CLK and DBx(0:11) are driven and XFR is held low.

Measured on two outputs differentially as the others are transitioning by 5 V. Measured for both states of INV.

Measured from 50% of rising CLK edge to 50% of output change. Measurement is made for both states of INV.

Measured from 50% of INV transition to 50% of output change.

Operation at 85°C ambient temperature requires the thermal switch disabled. In addition to a thermally optimized PCB, operation at high data update rates can

require additional thermal management, such as airflow across the surface of the AD8387.

Preliminary Technical Data

AD8387

Rev. PrA | Page 5 of 16

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

Supply Voltages

AVCCx - AGNDx

18 V

DVCC - DGND

4.5 V

Input Voltages

Maximum Digital Input Voltage

DVCC + 0.5 V

Minimum Digital Input Voltage

DGND - 0.5 V

Maximum Analog Input Voltage

AVCC + 0.5 V

Minimum Analog Input Voltage

AGND - 0.5 V

Internal Power Dissipation

TQFP E-Pad @ T

= 25°C

4.16 W

Operating Temperature Range

0°C to 85°C

Storage Temperature Range

-65°C to +125°C

Lead Temperature Range (Soldering 10 sec)

300°C

80-lead TQFP E-Pad:

= 24°C/W (Still Air) [JEDEC Standard, 4-layer PCB in still air.]

= 16°C/W

= TBD°C/W

Stresses above those listed under the Absolute Maximum
Ratings may cause permanent damage to the device. This is a
stress rating only; functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to the
absolute maximum ratings for extended periods may reduce
device reliability.

EXPOSED PADDLE

To ensure optimized thermal performance, the exposed paddle
must be thermally connected to an external plane, such as
AVCC or GND, as described in the Applications section.

OVERLOAD PROTECTION

The AD8387 overload protection circuit consists of an output
current limiter and a thermal switch.

When TSW is low, the thermal switch is disabled and the
output current limiter is enabled. The maximum current at any
one output is internally limited to 100 mA average. In the event
of a momentary short-circuit between a video output and a
power supply rail (VCC or AGND), the output current limit is
sufficiently low to provide temporary protection.

When TSW is high, the output current limiter, as well as the
thermal switch, is enabled. The thermal switch debiases the
output amplifier when the junction temperature reaches the
internally set trip point. In the event of an extended short-
circuit between a video output and a power supply rail, the
output amplifier current continues to switch between 0 and
100 mA typical with a period determined by the thermal time
constant and the hysteresis of the thermal trip point. The
thermal switch provides long term protection by limiting the
average junction temperature to a safe level.

MAXIMUM POWER DISSIPATION

The maximum power that can be safely dissipated by the AD8387
is limited by its junction temperature. The maximum safe junction
temperature for plastic encapsulated devices, as determined by the
glass transition temperature of the plastic, is approximately 150°C.
Exceeding this limit temporarily can cause a shift in the parametric
performance due to a change in the stresses exerted on the die by
the package. Exceeding a junction temperature of 150°C for an
extended period can result in device failure.

OPERATING TEMPERATURE RANGE

To ensure operation within the specified operating temperature
range, it is necessary to limit the maximum power dissipation as
follows.

STILL AIR

200LFM

500LFM

1.0

MAXIMUM PO

WER DISSIPAT

I
O

(

)

3.0

100

105

110

115

125

120

AMBIENT TEMPERATURE (

THERMAL

SWITCH

DISABLED

ENABLED

05653-

002

2.5

2.0

1.5

Figure 2. Maximum Power Dissipation vs. Temperature,

AD8387 on a 4-layer JEDEC PCB with thermally optimized landing

pattern as described in the Applications section.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

AD8387

Preliminary Technical Data

Rev. PrA | Page 6 of 16

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

DBA6

DBA7

DBA8

DBA11

DBA10

DBA9

DBA5

XFR

DVCC1

DGND1

DSW

R/L

DBB11

DBB10

DBB9

DBB8

DBB7

DBB6

DBB5

CLK

AGND1, 2
VID2

AVCC2, 3

VID4

AGND3, 4

VID3

VID1

AVCC4, 5

VID5

AGND5, 6

AVCC6, 7

VID7

AGND7, 8

VID8

AVCC8, 9

VID9

AGND9, 10

VID10

AVCC10, 11

VID6

PIN 1

NC = NO CONNECT

DBB4

DBB3

DBB2

DBB1

DBB0

DVCC3

DGND3

ISW

INV

GSW

TSW

AGNDB

AVCCB

BYP

TSTA

AGND1

VID11

DBA4

DBA3

DBA2

BBA1

DBA0

DVCC2

DGND2

AGNDD

AVCCD

VRH

VRL

AGND0

VID0

AVCC0

, 1

AD8387

TOP VIEW

(Not to Scale)

05653-

004

Figure 3. 80-Lead TQFP E-Pad Pin Configuration

Preliminary Technical Data

AD8387

Rev. PrA | Page 7 of 16

Table 3. 80-Lead TQFP E-Pad Pin Configurations

Pin No.

Mnemonic

Function

Description

1 to 7,
76 to 80;

14 to 25

DBA(0:11)

DBB(0:11)

Data Input

Two 12-Bit Data Input Buses. MSB = DBx(11). When in single data bus mode,
DSW = low, and DBA and DBB must receive the same data. See Figure 10 for
correct connections. Clock input. When DSW is high, data is loaded from both
DBA(0:11) and DBB(0:11) on the rising CLK edge simultaneously.

8 XFR

Transfer/Start
Sequence

The state of XFR is detected on the rising edge of CLK. Data is transferred to
the outputs and a new loading sequence begins on the next rising edge of CLK
after XFR is detected high.

9, 26, 75

DVCCx

Digital Power Supplies

Digital power supplies.

10, 27, 74

DGNDx

Digital Ground

These pins are normally connected to the digital ground plane.

11 CLK

Clock

When DSW and R/L are low, data is loaded from DBA(0:11) on the rising CLK
edge and from DBB(0:11) on the falling CLK edge. When DSW is low and R/L is
high, data is loaded from DBB(0:11) on the rising CLK edge and from DBA(0:11)
on the falling CLK edge. When this input is high, the AD8387 is in dual data bus
mode. Data is loaded from both DBA(0:11) and DBB(0:11) on the rising CLK edge
simultaneously.

DSW

Data Mode Switch

When low, the AD8387 is in single data bus mode. When R/L is low, data is
loaded from DBA(0:11) on the rising CLK edge and from DBB(0:11) on the
falling CLK edge. When R/L is high, data is loaded from DBB(0:11) on the
rising CLK edge and from DBA(0:11) on the falling CLK edge.

13 R/L

Right/Left

Select

A new data loading sequence begins on the left, with Channel 0, when this
input is low; and a new data loading sequence begins on the right, with
Channel 11, when this input is high.

ISW

Invert Mode Switch

When this input is high, the AD8387 is in column inversion mode. While
INV = high, the VID(0, 2, 4, 6, 8, 10) outputs are above VRL, and the
VID(1, 3, 5, 7, 9, 11) outputs are below VRL. While INV = low, the VID(0, 2, 4, 6, 8, 10)
outputs are below VRL, and the VID(1, 3, 5, 7, 9, 11) outputs are above VRL.

29 INV Invert

When ISW is low, the AD8387 is in frame or row inversion mode. When this input is
high, all VIDx output voltages are above VRL. When low, the VIDx outputs voltages
are below VRL. While ISW is high, the AD8387 is in column inversion mode. While this
input is high, the VID(0, 2, 4, 6, 8, 10) outputs are above VRL, and the VID(1, 3, 5, 7, 9,
11) outputs are below VRL. While this input is low, the VID(0, 2, 4, 6, 8, 10) outputs are
below VRL, and the VID(1, 3, 5, 7, 9, 11) outputs are above VRL.

GSW

Output Mode Switch

When this input is high, the video outputs operate normally. When low, the
video outputs are forced near AGND. This function operates when AVCC power
is off but requires DVCC power to be on.

TSW

Thermal Switch

When this input is low, the thermal switch is disabled. When high, the thermal
switch is enabled. When this input is low, the AD8387 is in frame or row
inversion mode. All video outputs are above VRL when INV = high and
below VRL when INV = low.

32, 33, 39, 43,
47, 51, 55, 59,
63, 69, 70

AGNDx

Analog Ground

Analog supply returns.

34, 35, 41,
45, 49, 53,
57, 61, 67, 68

AVCCx

Analog Power Supplies

Analog power supplies.

35 BYP

Bypass

A 0.1 F capacitor connected between BYP and AGND ensures optimum settling
time.

TSTA

Test Pin

Connect this pin to AGND.

38, 71 to 73

No connect.

40, 42, 44, 46,
48, 50, 52, 54,
56, 58, 60, 62

VID0 to
VID11

Analog Outputs

These pins are directly connected to the analog inputs of the LCD panel.

VRL

Video Center Reference

This voltage sets the video center voltage. The video outputs are above
this reference while INV = high and below this reference while INV = low.

65, 66

VRH

Full-Scale Reference

Twice the voltage applied between VRH and VRL sets the full-scale video output
voltage.

Preliminary Technical Data

AD8387

Rev. PrA | Page 9 of 16

TIMING DIAGRAMS

SINGLE DATA BUS CONFIGURATION, DSW = LOW

VID0
VID1
VID2
VID3
VID4
VID5
VID6
VID7
VID8
VID9

VID10
VID11

CHANNEL 0
CHANNEL 1
CHANNEL 2
CHANNEL 3
CHANNEL 4
CHANNEL 5
CHANNEL 6
CHANNEL 7
CHANNEL 8
CHANNEL 9
CHANNEL 10
CHANNEL 11

DBB(0:11)

DBA(0:11)

CLK

XFR

R/L

INV

D(0:11)

CLK

XFR

R/L

INV

VRH

ISW

VRL

DSW

12-CHANNEL

LCD

REFERENCES

AD8387

IMAGE

PROCESSOR

PIXEL

CLK

VRH

VRL

05653-

005

Figure 10. AD8387 in Single Data Bus System

INPUTS

OUT

CLK

D(0:11)

XFR

R/L

PIXEL CLK

12

VID0

11

VID1

10

VID2

VID3

VID4

VID5

VID6

VID7

VID8

VID9

VID10

VID11

VID0

VID1

VID2

VID3

VID4

VID5

VID6

VID7

VID8

10

VID9

11

VID10

12

VID11

LEFT

RIGHT

05653-

006

Figure 11. AD8387 in Single Data Bus Configuration Scanning Left-to-Right and Right-to-Left

AD8387

Preliminary Technical Data

Rev. PrA | Page 10 of 16

DUAL DATA BUS CONFIGURATION, DSW = HIGH

VID0
VID1
VID2
VID3
VID4
VID5
VID6
VID7
VID8
VID9

VID10
VID11

CHANNEL 0
CHANNEL 1
CHANNEL 2
CHANNEL 3
CHANNEL 4
CHANNEL 5
CHANNEL 6
CHANNEL 7
CHANNEL 8
CHANNEL 9
CHANNEL 10
CHANNEL 11

DBB(0:11)

DBA(0:11)

CLK

XFR

R/L

INV

DB(0:11)

DA(0:11)

CLK

XFR

R/L

INV

VRH

ISW

VRL

DSW

12-CHANNEL

LCD

AD8387

IMAGE

PROCESSOR

PIXEL

CLK

DVCC

05653-

007

REFERENCES

VRH

VRL

Figure 12. AD8387 in Dual Data Bus System

INPUTS

OUTPUTS

DBA(0:11)

DBB(0:11)

CLK

XFR

R/L

PIXEL CLK

12

VID0

11

VID1

10

VID2

VID3

VID4

VID5

VID6

VID7

VID8

VID9

VID10

VID11

LEFT

INPUTS

OUTPUTS

DBA(0:11)

DBB(0:11)

CLK

XFR

R/L

PIXEL CLK

VID0

VID1

VID2

VID3

VID4

VID5

VID6

VID7

VID8

10

VID9

11

VID10

12

VID11

RIGHT

05653-008

Figure 13. AD8387 in Dual Data Bus Configuration Scanning Left-to-Right and Right-to-Left

Preliminary Technical Data

AD8387

Rev. PrA | Page 11 of 16

CLK

DB(0:9)

STSQ

XFR

05653-

009

Figure 14. Input Timing (DSW = Low)

DB(0:11)

STSQ

XFR

INV

VID(0:11)

VRL

50%

VRL

VRL + VFS

VRLVFS

CLK

PIXELS

12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1

PIXELS

0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11

1 2 3 4 5 6

7 8 9 10 11

13 14

05653-

010

Figure 15. Output Timing (DSW = Low)

Table 4.

Parameter

Conditions

Min

Typ

Max

Unit

Data Setup Time

Data Hold Time

XFR Setup Time

XFR Hold Time

CLK High Time

TBD

CLK Low Time

TBD

Data Switching Delay

12.5

14.5

16.5

Invert Switching Delay

12.2

14.2

16.2

AD8387

Preliminary Technical Data

Rev. PrA | Page 12 of 16

FUNCTIONAL DESCRIPTION

The AD8387 is a system building block designed to directly
drive the columns of LCD microdisplays of the type
popularized for use in projection systems. It has 12 channels of
precision, 12-bit DACs loaded from a dual, high speed, 12-bit
wide input. Precision current feedback amplifiers, providing
well damped pulse response and fast voltage settling into large
capacitive loads, buffer the 12 outputs. Laser trimming at the
wafer level ensures low absolute output errors and tight
channel-to-channel matching. Tight part-to-part matching in
high resolution systems is guaranteed by the use of external
voltage references.

REFERENCE AND CONTROL INPUT DESCRIPTION

Data Transfer/Start Sequence Control--Input Data
Loading, Data Transfer

A valid XFR control input initiates a new six clock cycle, during
which data loaded during the previous cycle is transferred to
the outputs, and 12 input data words are loaded sequentially
into 12 internal channels.

When XFR is held high at the preceding rising CLK edge, data
loaded during the previous cycle is transferred to the outputs on
the rising CLK edge. When XFR is held high at the preceding
rising CLK edge, a new loading sequence begins on the current
rising CLK edge.

When the AD8387 is configured for single data bus (DSW =
low), data is loaded on both the rising and falling edges of CLK.
When configured for dual data bus (DSW = high), data is
loaded on the rising edges of CLK.

DSW Control--Data Mode Switch

When this input is high, the AD8387 is in dual data bus mode.
Data is loaded from both DBA(0:11) and DBB(0:11) on the
rising CLK edge simultaneously. When low, the AD8387 is in
single data bus mode. Data is loaded on the rising CLK edge
from DBA(0:11) and on the falling CLK edge from DBB(0:11).

Right/Left Control--Input Data Loading

To facilitate image mirroring, the direction of the loading
sequence is set by the R/L control. A new loading sequence
begins at Channel 0 and proceeds to Channel 11 when the R/L
control is held low. It begins at Channel 11 and proceeds to
Channel 0 when the R/L control is held high.

TSW Control--Thermal Switch Control

When this input is high, the thermal switch is enabled. When
low or left unconnected, the thermal switch is disabled.

An internal, 10 k pull-down resistor disables the thermal
switch when this pin is left unconnected.

GSW Control--Output Mode Switch

When this input is high, the video outputs operate normally.
When low or left open, the video outputs are forced to AGND.
This function operates when AVCC power is off but requires
DVCC power to be on.

INV Control--Analog Output Inversion

With ISW = low, the analog voltage equivalent of the input code
is subtracted from (VRL + VFS), while INV is held high, and
added to (VRL - VFS), while INV is held low.

With ISW = high, the analog voltage equivalent of the input
code is subtracted form (VRL + VFS) for VID(0, 2, 4, 6, 8, 10)
and added to (VRL - VFS) for VID(1, 3, 5, 7, 9, 11), while INV
is held high. The analog voltage equivalent of the input code is
added to (VRL - VFS) for VID(0, 2, 4, 6, 8, 10) and subtracted
from (VRL + VFS) for VID(1, 3, 5, 7, 9, 11), while INV is held low.

ISW Control--Inversion Mode Switch

When this input is low, the AD8387 is in frame or row inversion
mode. All video outputs are above VRL when INV = high and
below VRL when INV = low.

When this input is high, the AD8387 is in column inversion
mode. While INV = high, the VID(0, 2, 4, 6, 8, 10) outputs are
above VRL and the VID(1, 3, 5, 7, 9, 11) outputs are below VRL.
While INV = low, the VID(0, 2, 4, 6, 8, 10) outputs are below
VRL and the VID(1, 3, 5, 7, 9, 11) outputs are above VRL.

VRH, VRL Inputs--Full-Scale Video Reference Inputs

Two times the difference between VRH and VRL (analog input
voltages) sets the full-scale output voltage.

VFS = 2 × (VRH - VRL)

Preliminary Technical Data

AD8387

Rev. PrA | Page 13 of 16

THEORY OF OPERATION

TRANSFER FUNCTION AND ANALOG OUTPUT
VOLTAGE

The DecDriver has two regions of operation where the video
output voltages are either above or below the reference voltage
VRL. The transfer function defines the video output voltage as
the function of the digital input code as:

VIDx(n) = VRL + VFS × (1 - n/4095), for INV = High

VIDx(n) = VRL - VFS × (1 - n/4095), for INV = Low

where n is the input code.

VFS = 2 × (VRH - VRL)

A number of internal limits define the usable range of the video
output voltages, VIDx, which is shown in Figure 16.

VIDx VOLTS

AVCC

(VRL + VFS)

VRL

(VRL VFS)

AGND

VIDx vs. INPUT CODE

INPUT CODE

INV = LOW

INV = HIGH

4095

1.3V

VFS

5.5V

VFS

5.5V

1.3V

VRL

(AVCC 4)

AVCC

18V

INTERNAL LIMITS AND

USABLE VOLTAGE RANGES

05653-011

Figure 16. AD8387 Transfer Function and Usable Voltage Ranges

ACCURACY

To best correlate transfer function errors to image artifacts, the
overall accuracy of the DecDriver is defined by three
parameters, VDE , VCME, and V.

VDE, the differential error voltage, measures the difference
between the rms value of the output and the rms value of the
ideal. The defining expression is

[

]

VFS

VOUTP

VOUTN

VDE

4095

)

(

)

(

)

(

VCME, the common-mode error voltage, measures ½ the dc
bias of the output. The defining expression is

VRL

VOUTP

VOUTN

VCME

)

(

)

(

)

(

VDE measures the maximum VDE deviation between outputs.
The defining equation is

VDE = max(VDE(n){-min(VDE(n)})

V measures the maximum deviation between the output
voltages. The defining expression is

V(n) = max{VN(n), VP(n)}

where:

VN(n) = max{VOUTN(n)

(0 - 5)

} - min{VOUTN(n)

(0 - 5)

}

VP(n) = max{VOUTP(n)

(0 - 5)

} - min{VOUTP(n)

(0 - 5)

}

AD8387

Preliminary Technical Data

Rev. PrA | Page 14 of 16

APPLICATIONS

OPTIMIZED RELIABILITY WITH THE THERMAL
SWITCH

While internal current limiters provide short-term protection
against temporary shorts at the outputs, the thermal switch
provides protection against persistent shorts lasting for several
seconds. To optimize reliability with the use of the thermal
switch, the following sequence of operations is recommended.

INITIAL POWER-UP AFTER ASSEMBLY OR REPAIR

Grounded output mode is disabled, and thermal switch is
enabled. Ensure that the GSW pin is low and that the TSW pin
is high upon initial power-up and that they remain unchanged
throughout this procedure.

The initial power-up sequence follows:

Execute the initial power-up.

Identify any shorts at outputs.

Power down, repair shorts, and repeat the initial power-up
sequence until proper system functionality is verified.

POWER-UP DURING NORMAL OPERATION

Grounded output mode is disabled, and thermal switch is
disabled.

If TSW = low and GSW = high, all outputs go into normal
operating mode with the thermal switch disabled.

OPERATION IN HIGH AMBIENT TEMPERATURE

To extend the maximum operating junction temperature of the
AD8387 to 150°C, keep the thermal switch disabled during
normal operation. TSW = low ensures a disabled thermal switch.

POWER SUPPLY SEQUENCING

As indicated under the Absolute Maximum Ratings, the voltage
at any input pin cannot exceed its supply voltage by more than
0.5 V. Power-on and power-off sequencing can be required to
comply with the absolute maximum ratings.

Failure to comply with the Absolute Maximum Ratings can
result in functional failure or damage to the internal ESD
diodes. Damaged ESD diodes can cause temporary parametric
failures, which can result in image artifacts. Damaged ESD
diodes cannot provide full ESD protection, reducing reliability.

POWER-ON SEQUENCE

Apply AVCC

Apply VRH

Apply VRL

Apply DVCC

Apply signal inputs

POWER-OFF SEQUENCE

Remove signal inputs

Remove DVCC

Remove VRL

Remove VRH

Remove AVCC

GROUNDED OUTPUT MODE DURING POWER-OFF

Certain applications require that video outputs be held near
AGND during power-down. The following power-off sequence
ensures that the outputs are near ground during power-off and
that the Absolute Maximum Ratings are not violated.

Enable grounded output mode: GSW = low

Turn off analog reference voltages in ascending order.

Turn off AVCC.

Turn off digital signals.

Turn off DVCC.

PCB DESIGN FOR OPTIMIZED THERMAL
PERFORMANCE

Although the maximum safe operating junction temperature is
higher, the AD8387 is 100% tested at a junction temperature of
125°C. Consequently, the maximum guaranteed operating
junction temperature is 125°C. To limit the maximum junction
temperature at or below the guaranteed maximum, the package
in conjunction with the PCB must effectively conduct heat away
from the junction.

The AD8387 package is designed to provide enhanced thermal
characteristics through the exposed die paddle on the bottom
surface of the package. To take full advantage of this feature, the
exposed paddle must be in direct thermal contact with the PCB,
which then serves as a heat sink.

A thermally effective PCB must incorporate two thermal pads
and a thermal via structure. The thermal pad on the top surface
of the PCB provides a solderable contact surface on the top
surface of the PCB. The thermal pad on the bottom PCB layer
provides a surface in direct contact with the ambient. The
thermal via structure provides a thermal path to the inner and
bottom layers of the PCB to remove heat.

Preliminary Technical Data

AD8387

Rev. PrA | Page 15 of 16

THERMAL PAD DESIGN

To minimize thermal performance degradation of production
PCBs, the contact area between the thermal pad and the PCB
should be maximized. Therefore, the size of the thermal pad on
the top PCB layer should match the exposed paddle. The
second thermal pad of the same size should be placed on the
bottom side of the PCB. At least one thermal pad should be in
direct thermal contact with an external plane, such as AVCC or
GND.

THERMAL VIA STRUCTURE DESIGN

Effective heat transfer from the top to the inner and bottom
layers of the PCB requires thermal vias incorporated into the
thermal pad design. Thermal performance increases
logarithmically with the number of vias.

Near optimum thermal performance of production PCBs is
attained only when tightly spaced thermal vias are placed on the
full extent of the thermal pad.

AD8387 PCB DESIGN RECOMMENDATIONS

Table 5.Land Pattern Dimensions

Pad Size

0.6 mm × 0.25 mm

Pad Pitch

0.5 mm

Thermal Pad Size

6 mm × 6 mm

Thermal via Structure

0.25 mm - 0.35 mm holes

0.5 mm - 1.0 mm grid

Thermal Pad and Thermal via Connections

The thermal pad on the solder side is connected to a plane. The
use of thermal spokes is not recommended when connecting
the thermal pads or via structure to the plane.

Solder Masking

Solder masking of the via holes on the top layer of the PCB
plugs the via holes, inhibiting solder flow into the holes. To
minimize the formation of solder voids due to solder flowing
into the via holes (solder wicking), via diameter should be made
small, and an optional solder mask can be used. To optimize the
thermal pad coverage when using the solder mask, its diameter
should be no more than 0.1 mm larger than the via hole
diameter.

Pads are set by customer's PCB design rules.

Thermal via Holes

--Circular mask, centered on the via holes.

Diameter of the mask should be 0.1mm larger than the via hole
diameter.

Solder Mask--Bottom Layer

This is set by customer's PCB design rules.

16mm

6.5mm

05653-

012

Figure 17. Land Patter--Top Layer

6.5mm

05653-

014

Figure 18. Land Pattern--Bottom Layer

05653-

013

Figure 19. Solder Mask--Top Layer

AD8387

Preliminary Technical Data

Rev. PrA | Page 16 of 16

OUTLINE DIMENSIONS

COMPLIANT TO JEDEC STANDARDS MS-026-ADD-HD

0.27
0.22
0.17

14.20
14.00 SQ
13.80

12.20
12.00 SQ
11.80

0.50 BSC

LEAD PITCH

0.75
0.60
0.45

1.20

MAX

1.05
1.00
0.95

0.20
0.09

0.08 MAX

COPLANARITY

VIEW A

ROTATED 90° CCW

SEATING

PLANE

0° MIN

7°

3.5°

0°

0.15
0.05

VIEW A

PIN 1

TOP VIEW

(PINS DOWN)

6.00

BSC SQ

BOTTOM VIEW

(PINS UP)

EXPOSED

PAD

Figure 20. 80-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP]

(SV-80-1)

Dimensions shown in millimeters

ORDERING GUIDE

Model

Temperature Range

Package Description

Package Option

AD8387ASVZ

0°C to 85°C

80-Lead TQFP

SV-80-1

Z = Pb-free part.

PR05653-0-8/05(PrA)

Part Number AD8387

Document Outline