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Part Number AD8029

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Low Power, High Speed
Rail-to-Rail Input/Output Amplifier
AD8029/AD8030/AD8040
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703
© 2003 Analog Devices, Inc. All rights reserved.
FEATURES
Low power
1.3 mA supply current/amplifier
High speed
125 MHz, ­3 dB bandwidth (G = +1)
60 V/µs slew rate
80 ns settling time to 0.1%
Rail-to-rail input and output
No phase reversal, inputs 200 mV beyond rails
Wide supply range: 2.7 V to 12 V
Offset voltage: 6 mV max
Low input bias current
+0.7 µA to ­1.5 µA
Small packaging
SOIC-8, SC70-6, SOT23-8, SOIC-14, TSSOP-14
APPLICATIONS
Battery-powered instrumentation
Filters
A-to-D drivers
Buffering
CONNECTION DIAGRAMS
NC = NO CONNECT
NC
1
­IN
2
+IN
3
­V
S
4
DISABLE
+V
S
V
OUT
NC
8
7
6
5
03679-A
-
004
V
OUT
1
­V
S
2
+IN
3
5
DISABLE
6
+V
S
4
­IN
+
­
03679-A
-
002
Figure 1. SOIC-8 (R)
Figure 2. SC70-6 (KS)
V
OUT
1
1
­IN 1
2
+IN 1
3
­V
S
4
+V
OUT
2
+V
S
­IN 2
+IN 2
8
7
6
5
03679-A
-
003
+V
S
4
+IN 2
5
­IN 2
6
V
OUT
2
7
+IN 3
­V
S
­IN 3
V
OUT
3
11
10
9
8
V
OUT
1
1
­IN 1
2
+IN 1
3
V
OUT
4
­IN 4
+IN 4
14
13
12
03679-A
-
001
Figure 3. SOIC-8(R) and
SOT23-8 (RJ)
Figure 4. SOIC-14 (R) and
TSSOP-14 (RU)
GENERAL DESCRIPTION
The AD8029 (single), AD8030 (dual), and AD8040 (quad) are
rail-to-rail input and output high speed amplifiers with a
quiescent current of only 1.3 mA per amplifier. Despite their
low power consumption, the amplifiers provide excellent
performance with 125 MHz small signal bandwidth and
60 V/µs slew rate. ADI's proprietary XFCB process enables high
speed and high performance on low power.
This family of amplifiers exhibits true single-supply operation
with rail-to-rail input and output performance for supply
voltages ranging from 2.7 V to 12 V. The input voltage range
extends 200 mV beyond each rail without phase reversal. The
dynamic range of the output extends to within 40 mV of each
rail.
The AD8029/AD8030/AD8040 provide excellent signal quality
with minimal power dissipation. At G = +1, SFDR is ­72 dBc at
1 MHz and settling time to 0.1% is only 80 ns. Low distortion
and fast settling performance make these amplifiers suitable
drivers for single-supply A/D converters.
The versatility of the AD8029/AD8030/AD8040 allows the user
to operate the amplifiers on a wide range of supplies while
consuming less than 6.5 mW of power. These features extend
the operation time in applications ranging from battery-
powered systems with large bandwidth requirements to high
speed systems where component density requires lower power
dissipation.
The AD8029/AD8030 are the only low power, rail-to-rail input
and output high speed amplifiers available in SOT23 and SC70
micro packages. The amplifiers are rated over the extended
industrial temperature range, ­40°C to +125°C.
TIME (
µ
s)
03679-A-010
VOLTAGE (V)
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
1
µ
s/DIV
G = +1
V
S
= +5V
R
L
= 1k
TIED TO MIDSUPPLY
INPUT
OUTPUT
Figure 5. Rail-to-Rail Response
AD8029/AD8030/AD8040
Rev. A | Page 2 of 20
TABLE OF CONTENTS
Specifications..................................................................................... 3
Specifications with ±5 V Supply ................................................. 3
Specifications with +5 V Supply ................................................. 4
Specifications with +3 V Supply ................................................. 5
Absolute Maximum Ratings............................................................ 6
Maximum Power Dissipation ..................................................... 6
Typical Performance Characteristics ............................................. 7
Theory of Operation ...................................................................... 15
Input Stage................................................................................... 15
Output Stage................................................................................ 15
Applications..................................................................................... 16
Wideband Operation ................................................................. 16
Output Loading sensitivity........................................................ 16
Disable Pin .................................................................................. 17
Circuit Considerations .............................................................. 18
Design Tools and Technical Support ....................................... 18
Outline Dimensions ....................................................................... 19
Ordering Guide............................................................................... 20
ESD Caution................................................................................ 20
REVISION HISTORY
Revision A
11/03--Data Sheet Changed from Rev. 0 to Rev. A
Change Page
Added AD8040 part .......................................................Universal
Change to Figure 5 ....................................................................... 1
Changes to Specifications ............................................................ 3
Changes to Figures 10­12............................................................ 7
Change to Figure 14 ..................................................................... 8
Changes to Figures 20 and 21 ..................................................... 9
Inserted new Figure 36............................................................... 11
Change to Figure 40 ................................................................... 12
Inserted new Figure 41............................................................... 12
Added Output Loading Sensitivity section ............................. 16
Changes to Table 5...................................................................... 17
Changes to Power Supply Bypassing section .......................... 18
Changes to Ordering Guide ...................................................... 20
AD8029/AD8030/AD8040
Rev. A | Page 3 of 20
SPECIFICATIONS
SPECIFICATIONS WITH ±5 V SUPPLY
Table 1. V
S
= ±5 V @ T
A
= 25°C, G = +1, R
L
= 1 k to ground, unless otherwise noted. All specifications are per amplifier.
Parameter Conditions Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
­3 dB Bandwidth
G = +1, V
O
= 0.1 V p-p
80
125
MHz
G = +1, V
O
= 2 V p-p
14
19
MHz
Bandwidth for 0.1 dB Flatness
G = +2, V
O
= 0.1 V p-p
6
MHz
Slew Rate
G = +1, V
O
= 2 V Step
62
V/µs
G = ­1, V
O
= 2 V Step
63
V/µs
Settling Time to 0.1%
G = +2, V
O
= 2 V Step
80
ns
NOISE/DISTORTION PERFORMANCE
Spurious Free Dynamic Range (SFDR)
f
C
= 1 MHz, V
O
= 2 V p-p
­74
dBc
f
C
= 5 MHz, V
O
= 2 V p-p
­56
dBc
Input Voltage Noise
f = 100 kHz
16.5
nV/Hz
Input Current Noise
f = 100 kHz
1.1
pA/Hz
Crosstalk (AD8030/AD8040)
f = 5 MHz, V
IN
= 2 V p-p
­79
dB
DC PERFORMANCE
Input Offset Voltage
PNP Active, V
CM
= 0 V
1.6
5
mV
NPN Active, V
CM
= 4.5 V
2
6
mV
Input Offset Voltage Drift
T
MIN
to T
MAX
30 µV/°C
Input Bias Current
1
NPN Active, V
CM
= 4.5 V
0.7
1.3
µA
T
MIN
to T
MAX
1 µA
PNP Active, V
CM
= 0 V
­1.7
­2.8
µA
T
MIN
to T
MAX
2 µA
Input Offset Current
±0.1
±0.9
µA
Open-Loop Gain
V
o
= ±4.0 V
65
74
dB
INPUT CHARACTERISTICS
Input Resistance
6
M
Input Capacitance
2
pF
Input Common-Mode Voltage Range
­5.2 to +5.2
V
Common-Mode Rejection Ratio
V
CM
= ­4.5 V to +3 V, R
L
= 10 k
80
90
dB
DISABLE PIN (AD8029)
DISABLE Low Voltage
­V
S
+ 0.8
V
DISABLE Low Current
­6.5
µA
DISABLE High Voltage
­V
S
+ 1.2
V
DISABLE High Current
0.2
µA
Turn-Off Time
50% of DISABLE to <10% of Final V
O
,
V
IN
= ­1 V, G = ­1
150
ns
Turn-On Time
50% of DISABLE to <10% of Final V
O
,
V
IN
= ­1 V, G = ­1
85 ns
OUTPUT CHARACTERISTICS
Output Overdrive Recovery Time
(Rising/Falling Edge)
V
IN
= +6 V to ­6 V, G = ­1
55/45
ns
Output Voltage Swing
R
L
= 1 k
­V
S
+ 0.22
+V
S
­ 0.22
V
R
L
= 10 k
­V
S
+ 0.05
+V
S
­ 0.05
V
Short-Circuit Current
Sinking and Sourcing
170/160
mA
Off Isolation (AD8029)
V
IN
= 0.1 V p-p, f = 1 MHz, DISABLE = Low
­55
dB
Capacitive Load Drive
30% Overshoot
20
pF
POWER SUPPLY
Operating Range
2.7
12
V
Quiescent Current/Amplifier
1.4
1.5
mA
Quiescent Current (Disabled)
DISABLE = Low
150
200
µA
Power Supply Rejection Ratio
V
s
± 1 V
73
80
dB
1
Plus, +, (or no sign) indicates current into pin; minus (­) indicates current out of pin.
AD8029/AD8030/AD8040
Rev. A | Page 4 of 20
SPECIFICATIONS WITH +5 V SUPPLY
Table 2. V
S
= 5 V @ T
A
= 25°C, G = +1, R
L
= 1 k to midsupply, unless otherwise noted. All specifications are per amplifier.
Parameter Conditions Min
Typ
Max
Unit
DYNAMIC
PERFORMANCE
­3 dB Bandwidth
G = +1, V
O
= 0.1 V p-p
80
120
MHz
G = +1, V
O
= 2 V p-p
13
18
MHz
Bandwidth for 0.1 dB Flatness
G = +2, V
O
= 0.1 V p-p
6
MHz
Slew Rate
G = +1, V
O
= 2 V Step
55
V/µs
G = ­1, V
O
= 2 V Step
60
V/µs
Settling Time to 0.1%
G = +2, V
O
= 2 V Step
82
ns
NOISE/DISTORTION
PERFORMANCE
Spurious Free Dynamic Range (SFDR)
f
C
= 1 MHz, V
O
= 2 V p-p
­73
dBc
f
C
= 5 MHz, V
O
= 2 V p-p
­55
dBc
Input Voltage Noise
f = 100 kHz
16.5
nV/Hz
Input Current Noise
f = 100 kHz
1.1
pA/Hz
Crosstalk (AD8030/AD8040)
f = 5 MHz, V
IN
= 2 V p-p
-79
dB
DC
PERFORMANCE
Input Offset Voltage
PNP Active, V
CM
= 2.5 V
1.4
5
mV
NPN Active, V
CM
= 4.5 V
1.8
6
mV
Input Offset Voltage Drift
T
MIN
to T
MAX
25 µV/°C
Input Bias Current
1
NPN Active, V
CM
= 4.5 V
0.8
1.2
µA
T
MIN
to T
MAX
1 µA
PNP Active, V
CM
= 2.5 V
­1.8
­2.8
µA
T
MIN
to T
MAX
2 µA
Input Offset Current
±0.1
±0.9
µA
Open-Loop Gain
V
o
= 1 V to 4 V
65
74
dB
INPUT
CHARACTERISTICS
Input
Resistance
6 M
Input
Capacitance
2 pF
Input Common-Mode Voltage Range
­0.2 to +5.2
V
Common-Mode Rejection Ratio
V
CM
= 0.25 V to 2 V, R
L
= 10 k
80
90
dB
DISABLE PIN (AD8029)
DISABLE Low Voltage
­V
S
+ 0.8
V
DISABLE Low Current
­6.5
µA
DISABLE High Voltage
­V
S
+ 1.2
V
DISABLE High Current
0.2 µA
Turn-Off Time
50% of DISABLE to <10% of Final V
O
,
V
IN
= ­1 V, G = ­1
155
ns
Turn-On Time
50% of DISABLE to <10% of Final V
O
,
V
IN
= ­1 V, G = ­1
90
ns
OUTPUT
CHARACTERISTICS
Overdrive Recovery Time
(Rising/Falling Edge)
V
IN
= ­1 V to +6 V, G = ­1
45/50
ns
Output Voltage Swing
R
L
= 1 k
­V
S
+ 0.17
+V
S
­ 0.17
V
R
L
= 10 k
­V
S
+ 0.04
+V
S
­ 0.04
V
Short-Circuit Current
Sinking and
Sourcing
95/60
mA
Off Isolation (AD8029)
V
in
= 0.1 V p-p, f = 1 MHz, DISABLE = Low
­55
dB
Capacitive Load Drive
30% Overshoot
15
pF
POWER
SUPPLY
Operating Range
2.7
12
V
Quiescent Current/Amplifier
1.3
1.5
mA
Quiescent Current (Disabled)
DISABLE = Low
140
200
µA
Power Supply Rejection Ratio
V
S
± 1 V
73
80
dB
1
Plus, +, (or no sign) indicates current into pin; minus (­) indicates current out of pin.
AD8029/AD8030/AD8040
Rev. A | Page 5 of 20
SPECIFICATIONS WITH +3 V SUPPLY
Table 3. V
S
= +3 V @ T
A
= 25°C, G = +1, R
L
= 1 k to midsupply, unless otherwise noted. All specifications are per amplifier.
Parameter Conditions Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
­3 dB Bandwidth
G = +1, V
O
= 0.1 V p-p
80
112
MHz
G = +1, V
O
= 2 V p-p
13
18
MHz
Bandwidth for 0.1 dB Flatness
G = +2, V
O
= 0.1 V p-p
6
MHz
Slew Rate
G = +1, V
O
= 2 V Step
55
V/µs
G = ­1, V
O
= 2 V Step
57
V/µs
Settling Time to 0.1%
G = +2, V
O
= 2 V Step
110
ns
NOISE/DISTORTION PERFORMANCE
Spurious Free Dynamic Range (SFDR)
f
C
= 1 MHz, V
O
= 2 V p-p
­72
dBc
f
C
= 5 MHz, V
O
= 2 V p-p
­60
dBc
Input Voltage Noise
f = 100 kHz
16.5
nV/Hz
Input Current Noise
f = 100 kHz
1.1
pA/Hz
Crosstalk (AD8030/AD8040)
f = 5 MHz, V
IN
= 2 V p-p
-80
dB
DC PERFORMANCE
Input Offset Voltage
PNP Active, V
CM
= 1.5 V
1.1
5
mV
NPN Active, V
CM
= 2.5 V
1.6
6
mV
Input Offset Voltage Drift
T
MIN
to T
MAX
24
µV/°C
Input Bias Current
1
NPN Active, V
CM
= 2.5 V
0.7
1.2
µA
T
MIN
to T
MAX
1
µA
Input Bias Current
1
PNP Active, V
CM
= 1.5 V
­1.5
­2.5
µA
T
MIN
to T
MAX
1.6
µA
Input Offset Current
±0.1
±0.9
µA
Open-Loop Gain
V
o
= 0.5 V to 2.5 V
64
73
dB
INPUT CHARACTERISTICS
Input Resistance
6
M
Input Capacitance
2
pF
Input Common-Mode Voltage Range
­0.2 to +3.2
V
Common-Mode Rejection Ratio
V
CM
= 0.25 V to 1.25 V, R
L
= 10 k
78
88
dB
DISABLE PIN (AD8029)
DISABLE Low Voltage
­V
S
+ 0.8
V
DISABLE Low Current
­6.5
µA
DISABLE High Voltage
­V
S
+ 1.2
V
DISABLE High Current
0.2
µA
Turn-Off Time
50% of DISABLE to <10% of Final V
O
,
V
IN
= ­1 V, G = ­1
165
ns
Turn-On Time
50% of DISABLE to <10% of Final V
O
,
V
IN
= ­1 V, G = ­1
95
ns
OUTPUT CHARACTERISTICS
Output Overdrive Recovery Time
(Rising/Falling Edge)
V
IN
= ­1 V to +4 V, G = ­1
75/100
ns
Output Voltage Swing
R
L
= 1 k
­V
S
+ 0.09
+V
S
­ 0.09
V
R
L
= 10 k
­V
S
+ 0.04
+V
S
­ 0.04
V
Short-Circuit Current
Sinking and Sourcing
80/40
mA
Off Isolation (AD8029)
V
IN
= 0.1 V p-p, f = 1 MHz, DISABLE = Low
­55
dB
Capacitive Load Drive
30% Overshoot
10
pF
POWER SUPPLY
Operating Range
2.7
12
V
Quiescent Current/Amplifier
1.3
1.4
mA
Quiescent Current (Disabled)
DISABLE = Low
145
200
µA
Power Supply Rejection Ratio
V
S
± 1 V
70
76
dB
1
Plus, +, (or no sign) indicates current into pin; minus (­) indicates current out of pin.
AD8029/AD8030/AD8040
Rev. A | Page 6 of 20
ABSOLUTE MAXIMUM RATINGS
Table 4. AD8029/AD8030/AD8040 Stress Ratings
Parameter Rating
Supply Voltage
12.6 V
Power Dissipation
See Figure 6
Common-Mode Input Voltage
±V
S
± 0.5 V
Differential Input Voltage
±1.8 V
Storage Temperature
­65°C to +125°C
Operating Temperature Range
­40°C to +125°C
Lead Temperature Range
(Soldering 10 sec)
300°C
Junction Temperature
150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
MAXIMUM POWER DISSIPATION
The maximum safe power dissipation in the AD8029/AD8030/
AD8040 package is limited by the associated rise in junction
temperature (T
J
) on the die. The plastic encapsulating the die
locally reaches the junction temperature. At approximately
150°C, which is the glass transition temperature, the plastic
changes its properties. Even temporarily exceeding this
temperature limit may change the stresses that the package
exerts on the die, permanently shifting the parametric
performance of the AD8029/AD8030/AD8040. Exceeding a
junction temperature of 175°C for an extended period can
result in changes in silicon devices, potentially causing failure.
The still-air thermal properties of the package and PCB (
JA
),
ambient temperature (T
A
), and the total power dissipated in the
package (P
D
) determine the junction temperature of the die. The
junction temperature can be calculated as
T
J
= T
A
+ (P
D
×
JA
)
The power dissipated in the package (P
D
) is the sum of the
quiescent power dissipation and the power dissipated in the
package due to the load drive for all outputs. The quiescent
power is the voltage between the supply pins (V
S
) times the
quiescent current (I
S
). Assuming the load (R
L
) is referenced to
midsupply, the total drive power is V
S
/2 × I
OUT
, some of which is
dissipated in the package and some in the load (V
OUT
× I
OUT
).
The difference between the total drive power and the load
power is the drive power dissipated in the package.
P
D
= Quiescent Power + (Total Drive Power ­ Load Power)
(
)
L
OUT
L
OUT
S
S
S
D
R
V
R
V
V
I
V
P
2
­
2


×
+
×
=
RMS output voltages should be considered. If R
L
is referenced to
V
S
­, as in single-supply operation, then the total drive power is
V
S
× I
OUT
.
If the rms signal levels are indeterminate, consider the worst
case, when V
OUT
= V
S
/4 for R
L
to midsupply:
(
) (
)
L
S
S
S
D
R
V
I
V
P
2
4
/
+
×
=
In single-supply operation with R
L
referenced to V
S
­, worst case
is V
OUT
= V
S
/2.
Airflow will increase heat dissipation, effectively reducing
JA
.
Also, more metal directly in contact with the package leads
from metal traces, through holes, ground, and power planes will
reduce the
JA
. Care must be taken to minimize parasitic capaci-
tances at the input leads of high speed op amps, as discussed in
the PCB Layout section.
Figure 6 shows the maximum safe power dissipation in the
package versus the ambient temperature for the SOIC-8
(125°C/W), SOT23-8 (160°C/W), SOIC-14 (90°C/W),
TSSOP-14 (120°C/W), and SC70-6 (208°C/W) packages on a
JEDEC standard 4-layer board.
JA
values are approximations.
­40
­20 ­10
­30
0 10 20 30 40 50 60 70 80 90 100 110 120
2.5
M
A
XIM
U
M
POW
E
R
D
I
SSIPA
TION
(
W
)
1.0
0.5
1.5
2.0
0
AMBIENT TEMPERATURE (°C)
SOIC-8
TSSOP-14
SOIC-14
SOT-23-8
SC70-6
03679-A
-
018
Figure 6. Maximum Power Dissipation
Output Short Circuit
Shorting the output to ground or drawing excessive current
from the AD8029/AD8030/AD8040 could cause catastrophic
failure.
AD8029/AD8030/AD8040
Rev. A | Page 7 of 20
TYPICAL PERFORMANCE CHARACTERISTICS
Default Conditions: V
S
= 5 V (T
A
= 25°C, R
L
= 1 k tied to midsupply, unless otherwise noted.)
FREQUENCY (MHz)
0.1
1
10
100
1000
­14
­13
­12
­11
­10
­9
­8
­7
­6
­5
­4
­3
­2
­1
0
1
NORMALIZE
D
CLOS
E
D
-LOOP
GAIN (dB)
03679-0-004
G = +10
R
F
= 9k
, R
G
= 1k
G = +2
R
F
= R
G
= 1k
G = ­1
R
F
= R
G
= 1k
V
O
= 0.1V p-p
G = +1
R
F
= 0
Figure 7. Small Signal Frequency Response for Various Gains
FREQUENCY (MHz)
1
10
100
1000
­8
­7
­6
­5
­4
­3
­2
­1
0
1
CLOSED-LOOP GAIN (dB)
03679-0-005
±
5V
+5V
+3V
G = +1
V
O
= 0.1V p-p
Figure 8. Small Signal Frequency Response for Various Supplies
FREQUENCY (MHz)
1
10
100
­8
­7
­6
­5
­4
­3
­2
­1
0
1
CLOSED-LOOP GAIN (dB)
03679-0-006
±
5V
+5V
+3V
G = +1
V
O
= 2V p-p
Figure 9. Large Signal Frequency Response for Various Supplies
FREQUENCY (MHz)
1
10
100
­0.8
­0.7
­0.6
­0.5
­0.4
­0.3
­0.2
­0.1
0
0.1
0.2
NORMALIZE
D
CLOS
E
D
-LOOP
GAIN (dB)
03679-A-011
DASHED LINES: V
OUT
= 2V p-p
SOLID LINES: V
OUT
= 0.1V p-p
G = +1
G = +2
R
F
= 1k
Figure 10. 0.1 dB Flatness Frequency Response
FREQUENCY (MHz)
1
10
100
­8
­7
­6
­5
­4
­3
­2
­1
0
1
NORMALIZE
D
CLOS
E
D
-LOOP
GAIN (dB)
03679-A-012
±
5V
+3V
+5V
G = +2
V
O
= 0.1V p-p
R
F
= 1k
Figure 11. Small Signal Frequency Response for Various Supplies
FREQUENCY (MHz)
1
10
100
­8
­7
­6
­5
­4
­3
­2
­1
0
1
NORMALIZE
D
CLOS
E
D
-LOOP
GAIN (dB)
03679-A-013
V
S
=
±
5
V
S
= +3
V
S
= +5
G = +2
V
O
= 2V p-p
R
F
= 1k
Figure 12. Large Signal Frequency Response for Various Supplies
AD8029/AD8030/AD8040
Rev. A | Page 8 of 20
FREQUENCY (MHz)
1
10
100
1000
­8
­7
­6
­5
­4
­3
­2
­1
0
1
2
3
4
5
6
CLOSED-LOOP GAIN (dB)
03679-0-010
0pF
20pF
10pF
5pF
G = +1
V
O
= 0.1V p-p
Figure 13. Small Signal Frequency Response for Various C
LOAD
FREQUENCY (MHz)
1
10
100
­8
­7
­6
­5
­4
­3
­2
­1
0
1
NORMALIZE
D
CLOS
E
D
-LOOP
GAIN (dB)
03679-A-014
2V p-p
1V p-p
0.1V p-p
G = +2
R
F
= 1k
Figure 14. Frequency Response for Various Output Amplitudes
03679-0-054
10
100
1k
10k
100k
1M
10M
100M
1G
80
70
60
225
180
135
90
45
0
50
40
OPEN-LOOP GAIN (dB)
OPEN
-
L
OOP PH
A
SE (
D
egrees)
30
20
10
0
­10
­20
FREQUENCY (Hz)
Figure 15. Open-Loop Gain and Phase vs. Frequency
FREQUENCY (MHz)
1
10
100
1000
03679-0-013
CLOSED-
L
OOP GAIN (
d
B)
­8
­7
­6
­5
­4
­3
­2
­1
0
1
2
G = +1
V
O
= 0.1V p-p
V
ICM
= 0V
V
ICM
= V
S+
­ 0.2V
V
ICM
= V
S­
+ 0.2V
Figure 16. Small Signal Frequency Response for Various
Input Common-Mode Voltages
FREQUENCY (MHz)
1
10
100
­6
­5
­4
­3
­2
­1
0
1
2
CLOSED-LOOP GAIN (dB)
03679-0-014
+125
°
C
+85
°
C
+25
°
C
­40
°
C
G = +1
V
O
= 0.1V p-p
Figure 17. Small Signal Frequency Response vs. Temperature
FREQUENCY (MHz)
1
10
100
­8
­7
­6
­5
­4
­3
­2
­1
0
1
CLOSED-LOOP GAIN (dB)
03679-0-015
+125°C
+25°C
+85°C
­40°C
G = +1
V
O
= 2V p-p
Figure 18. Large Signal Frequency Response vs. Temperature
AD8029/AD8030/AD8040
Rev. A | Page 9 of 20
FREQUENCY (MHz)
03679-0-016
0.01
0.1
10
1
HARMONIC DIS
T
ORTION (dBc
)
­105
­95
­85
­75
­65
­55
­45
­35
G = +1
V
OUT
= 2V p-p
R
L
= 1k
SECOND HARMONIC: SOLID LINE
THIRD HARMONIC: DASHED LINE
V
S
= +3V
V
S
= +5V
V
S
=
±
5V
Figure 19. Harmonic Distortion vs. Frequency and Supply Voltage
03679-A-015
HARMONIC DIS
T
ORTION (dBc
)
­80
0.5
1.5
2.5
3.5
4.5
5.5
6.5
7.5
8.5
9.5
­75
­70
­65
­60
­55
­50
­45
­40
OUTPUT AMPLITUDE (V p-p)
G = +2
FREQ = 1MHz
R
F
= 1k
SECOND HARMONIC: SOLID LINE
THIRD HARMONIC: DASHED LINE
V
S
= +3V
V
S
= +5V
V
S
= +10V
Figure 20. Harmonic Distortion vs. Output Amplitude
FREQUENCY (MHz)
0.01
0.1
1
10
HARMONIC DIS
T
ORTION (dBc
)
­110
­100
­90
­80
­70
­60
­50
­40
­30
03679-A-016
SECOND HARMONIC: SOLID LINE
THIRD HARMONIC: DASHED LINE
V
S
= +5V
V
OUT
= 2.0V p-p
R
L
= 1k
R
F
= 1k
G = +2
G = +1
G = ­1
Figure 21. Harmonic Distortion vs. Frequency and Gain
FREQUENCY (MHz)
0.01
0.1
1
10
­110
­100
­90
­80
­70
­60
­50
­40
03679-0-075
HARMONIC DIS
T
ORTION (dBc
)
G = +1
V
OUT
= 2V p-p
SECOND HARMONIC: SOLID LINE
THIRD HARMONIC: DASHED LINE
R
L
= 1k
R
L
= 2k
R
L
= 5k
Figure 22. Harmonic Distortion vs. Frequency and Load
INPUT COMMON-MODE VOLTAGE (V)
03679-0-020
1.0
1.5
2.0
2.5
3.0
3.5
4.0
HARMONIC DIS
T
ORTION (dBc
)
­100
­90
­80
­70
­60
­50
­40
G = +1
V
OUT
= 2V p-p
FREQ = 1MHz
SECOND HARMONIC: SOLID LINE
THIRD HARMONIC: DASHED LINE
V
S
= +3V
V
S
= +5V
Figure 23. Harmonic Distortion vs. Input Common Mode Voltage
FREQUENCY (Hz)
10
100
1k
10k
100k
1M
10M
1
10
100
1000
0.1
1
10
100
03679-0-069
VOLTA
GE N
O
ISE (
n
V/ H
z
)
CURRE
NT NOIS
E
(pA/ Hz)
VOLTAGE NOISE
CURRENT NOISE
Figure 24. Voltage and Current Noise vs. Frequency
AD8029/AD8030/AD8040
Rev. A | Page 10 of 20
­100
TIME (ns)
­75
­50
­25
25
0
OUTPUT VOLTAGE (mV)
50
75
100
G = +1
V
S
= ±2.5V
20ns/DIV
25mV/DIV
03679-0-022
Figure 25. Small Signal Transient Response
03679-A
-
023
TIME (ns)
OUTPUT VOLTAGE (V)
­2.5
2.5
2.0
1.5
1.0
0.5
0
­0.5
­1.0
­1.5
­2.0
0.5V/DIV
25ns/DIV
G = +1
V
S
= ±2.5V
2V p-p
4V p-p
Figure 26. Large Signal Transient Response
­4
­3
­2
­1
1
0
2
3
4
G = ­1 (R
F
= 1k
)
R
L
= 1k
V
S
= ±2.5V
200ns/DIV
1V/DIV
03679-0-024
INPUT
OUTPUT
TIME (ns)
OUTPUT VOLTAGE (
V
)
Figure 27. Output Overdrive Recovery
­100
­75
­50
­25
25
0
50
75
100
G = +1
V
S
= ±2.5V
20ns/DIV
25mV/DIV
03679-0-025
C
L
= 20pF
C
L
= 5pF
C
L
= 10pF
TIME (ns)
OUTPUT VOLTAGE (mV)
Figure 28. Small Signal Transient Response with Capacitive Load
03679-0-059
VOLTAGE (V)
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
TIME (Seconds)
1
µ
s/DIV
G = +1
V
S
= +5V
R
L
= 1k
TIED TO MIDSUPPLY
INPUT
OUTPUT
Figure 29. Rail-to-Rail Response, G = +1
­4
­3
­2
­1
1
0
2
3
4
G = +1
R
L
= 1k
V
S
= ±2.5V
200ns/DIV
1V/DIV
03679-0-027
INPUT
OUTPUT
TIME (ns)
OUTPUT VOLTAGE (V)
Figure 30. Input Overdrive Recovery
AD8029/AD8030/AD8040
Rev. A | Page 11 of 20
­0.1%
+0.1%
500ns/DIV
03679-0-062
V
OUT
­ 2V
IN
(0.1%/DIV)
G = +2
V
S
=
±
2.5V
+1V
­1V
V
OUT
(500mV/DIV)
Figure 31. Long-Term Settling Time
FREQUENCY (Hz)
1k
10k
100k
1M
10M
100M
1G
­100
­90
­80
­70
­60
­50
­40
­30
­20
03679-0-078
CMRR (dB)
Figure 32. Common-Mode Rejection Ratio vs. Frequency
03679-0-055
0.1
1
10
100
1000
­20
OUTP
UT (dB)
­70
­60
­50
­40
­30
­80
FREQUENCY (MHz)
G = +1
R
L
= 1k
DISABLE = LOW
V
IN
= 0.1V p-p
Figure 33. AD8029 Off-Isolation vs. Frequency
­0.1%
+0.1%
20ns/DIV
03679-0-063
V
OUT
­ 2V
IN
(0.1%/DIV)
V
OUT
(500mV/DIV)
V
IN
(250mV/DIV)
G = +2
Figure 34.0.1% Short-Term Settling Time
1k
10k
100k
1M
10M
100M
1G
FREQUENCY (Hz)
­100
­90
­80
­70
­60
­50
­40
­30
­20
­10
0
P
S
RR (dB)
03679-0-033
+PSRR
­PSRR
Figure 35. PSRR vs. Frequency
03679-A
-
005
FREQUENCY (MHz)
CROS
S
T
ALK (dB)
0.01
­130
1000
0.1
1.0
10
100
­30
­40
­50
­60
­70
­80
­90
­100
­110
­120
DRIVE AMP
1k
50
V
IN
CROSSTALK = 20log
(
V
OUT
V
IN
)
LISTEN AMP
1k
V
OUT
AD8040
(AMP 4 DRIVE
AMP 1 LISTEN)
AD8030
(AMP 2 DRIVE
AMP 1 LISTEN)
Figure 36. AD8030/AD8040 Crosstalk vs. Frequency
AD8029/AD8030/AD8040
Rev. A | Page 12 of 20
INPUT COMMON-MODE VOLTAGE (V)
­1
0
1
2
3
4
5
6
7
8
9
10
1
­2.5
­2.0
­1.5
­1.0
­0.5
0
0.5
1.0
1.5
2.0
2.5
03679-0-074
INP
U
T BIAS
CURRE
NT (
µ
A)
1
V
S
= +3V
V
S
= +5V
V
S
= +10V
Figure 37. Input Bias Current vs. Input Common-Mode Voltage
TEMPERATURE (
°
C)
­40 ­25 ­10
5
20
35
50
65
80
95
110 125
­2.0
­1.0
­1.2
­1.4
­1.6
­1.8
0
1.0
0.8
0.6
0.4
0.2
03679-0-073
INP
U
T BIAS
CURRE
NT (P
NP
ACTIV
E
)
(
µ
A)
INP
U
T BIAS
CURRE
NT (NP
N
ACTIV
E
)
(
µ
A)
V
S
= +3
V
S
= +5
V
S
=
±
5
NPN ACTIVE
PNP ACTIVE
Figure 38. Input Bias Current vs. Temperature
TEMPERATURE (
°
C)
S
U
P
P
L
Y
CURRE
NT (mA)
­40
­20
0
20
40
60
80
100
120
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
03679-0-067
V
S
=
±
5V
V
S
= +5V
V
S
= +3V
Figure 39 Quiescent Supply Current vs. Temperature
INPUT COMMON-MODE VOLTAGE (V)
INPUT OFFSET VOLTAGE (
m
V)
­1
0
1
2
3
4
5
6
7
8
9
10
1
­4
­3
­2
­1
0
1
2
3
4
03679-A-017
1
V
S
= +3V
V
S
= +5V
V
S
= +10V
R
L
= 1k
TO
MIDSUPPLY
G = +1
Figure 40. Input Offset Voltage vs. Input Common-Mode Voltage
03679-A
-
006
TEMPERATURE (°C)
IN
PU
T OFFSET VOLTA
GE (
m
V)
­4
125
­40 ­25 ­10
5
20
35
50
65
80
95
110
V
S
= ±5V
V
S
= +5V
V
S
= +3V
4
3
2
1
0
­1
­2
­3
Figure 41. Input Offset Voltage vs. Temperature
INPUT OFFSET VOLTAGE (mV)
FREQUENCY
­5
­4
­3
­2
­1
0
1
2
3
4
5
0
20
40
60
80
100
120
03679-0-064
COUNT = 1088
MEAN = 0.44mV
STDEV = 1.05mV
Figure 42. Input Offset Voltage Distribution
AD8029/AD8030/AD8040
Rev. A | Page 13 of 20
03679-0-061
100k
1M
10M
100M
1G
OUTP
UT IMP
E
DANCE
(
)
1
10
100
1k
1M
100k
10k
FREQUENCY (Hz)
DISABLE = LOW
Figure 43. AD8029 Output Impedance vs. Frequency, Disabled
LOAD RESISTANCE (
)
OUTP
UT S
A
TURATION V
O
LTAGE
(V
)
100
1000
10000
­0.5
0.5
­0.4
­0.3
­0.2
­0.1
0
0.1
0.2
0.3
0.4
V
S
= +3V
V
S
= +5V V
S
=
±
5V
V
OH
­ V
S
V
OL
­ V
S
LOAD RESISTANCE TIED
TO MIDSUPPLY
03679-0-041
Figure 44. Output Saturation Voltage vs. Load Resistance
TEMPERATURE (
°
C)
OUTP
UT S
A
TURATION V
O
LTAGE
(mV
)
­40 ­25 ­10
5
20
35
50
65
80
95
110 125
30
50
70
90
110
130
150
170
03679-0-066
V
S
=
±
5V
V
S
= +5V
V
S
= +3V
R
L
= 1k
TIED TO MIDSUPPLY
SOLID LINE: V
S+
­ VOH
DASHED LINE: VOL ­ V
S­
Figure 42. Output Saturation Voltage vs. Temperature
03679-0-060
1k
10k
100k
1M
10M
100M
1G
OUTP
UT IMP
E
DANCE
(
)
0.1
1
10
100
1000
FREQUENCY (Hz)
G = +1
Figure 45. Output Impedance vs. Frequency, Enabled
OUTPUT VOLTAGE (V)
­2.5 ­2.0 ­1.5 ­1.0 ­0.5
­0
0.5
1.0
1.5
2.0
2.5
­2.0
­1.5
­1.0
­0.5
0
0.5
1.0
1.5
2.0
03679-0-072
INP
U
T E
RROR V
O
LTAGE
(mV
)
R
L
= 10k
R
L
= 1k
V
S
=
±
2.5V
Figure 46. Input Error Voltage vs. Output Voltage
AD8029/AD8030/AD8040
Rev. A | Page 14 of 20
03679-A-020
0
50
100
150
200
250
300
350
1.5
OUTP
UT AMP
L
ITUDE
(V
)
­1.0
­0.5
0
0.5
1.0
­1.5
TIME (ns)
DISABLE (­0.5V TO ­2V)
R
L
= 10k
R
L
= 100
R
L
= 1k
V
S
=
±
2.5V
G = ­1 (R
F
= 1k
)
OUTPUT DISABLED
Figure 47. AD8029 DISABLE Turn-Off Timing
03679-A-021
0
50
100
150
200
250
300
350
1.5
OUTP
UT AMP
L
ITUDE
(V
)
­1.5
­1.0
­0.5
0
0.5
1.0
TIME (ns)
DISABLE (­2V TO ­0.5V)
R
L
= 100
R
L
= 1k
R
L
= 10k
V
S
=
±
2.5V
G = ­1 (R
F
= 1k
)
OUTPUT ENABLED
Figure 48. AD8029 DISABLE Turn-On Timing
DISABLE PIN VOLTAGE (V)
V
S
= +3V, +5V, +10V
0
1
0.8
1.2
2
3
­7
­6
­5
­4
­3
­2
­1
0
1
03679-A-022
DIS
ABLE
P
I
N CURRE
NT (
µ
A)
Figure 49. AD8029 DISABLE Pin Current vs. DISABLE Pin Voltage
AD8029/AD8030/AD8040
Rev. A | Page 15 of 20
THEORY OF OPERATION
03679-0-051
IN­
IN+
R
5
R
6
R
7
R
8
R
1
R
2
R
3
R
4
M
TOP
I
TAIL
M
BOT
OUTPUT
BUFFER
­V
S
R
TH
I
TH
+V
S
­1.2V
+V
S
V
OUT
Q
10
Q
11
C
MT
C
MB
­V
S
AD8029 ONLY
TO DISABLE
CIRCUITRY
DISABLE
Q
3
Q
4
Q
2
Q
1
Q
9
Q
8
Q
7
Q
6
Q
5
OUT
IN
COM
SPD
Figure 50. Simplified Schematic
The AD8029 (single), AD8030 (dual), and AD8040 (quad) are
rail-to-rail input and output amplifiers fabricated using Analog
Devices' XFCB process. The XFCB process enables the AD8029/
AD8030/AD8040 to operate on 2.7 V to 12 V supplies with a
120 MHz bandwidth and a 60 V/µs slew rate. A simplified sche-
matic of the AD8029/AD8030/AD8040 is shown in Figure 50.
INPUT STAGE
For input common-mode voltages less than a set threshold
(1.2 V below V
CC
), the resistor degenerated PNP differential pair
(comprising Q
1
toQ
4
) carries the entire I
TAIL
current, allowing
the input voltage to go 200 mV below ­V
S
. Conversely, input
common-mode voltages exceeding the same threshold cause
I
TAIL
to be routed away from the PNP differential pair and into
the NPN differential pair through transistor Q
9
. Under this
condition, the input common-mode voltage is allowed to rise
200 mV above +V
S
while still maintaining linear amplifier
behavior. The transition between these two modes of operation
leads to a sudden, temporary shift in input stage transconduc-
tance, g
m
, and dc parameters (such as the input offset voltage
V
OS
), which in turn adversely affect the distortion performance.
The SPD block shortens the duration of this transition, thus
improving the distortion performance. As shown in Figure 50,
the input differential pair is protected by a pair of two series
diodes, connected in anti-parallel, which clamp the differential
input voltage to approximately ±1.5 V.
OUTPUT STAGE
The currents derived from the PNP and NPN input differential
pairs are injected into the current mirrors M
BOT
and M
TOP
, thus
establishing a common-mode signal voltage at the input of the
output buffer.
The output buffer performs three functions:
1.
It buffers and applies the desired signal voltage to the
output devices, Q
10
and Q
11
.
2.
It senses the common-mode current level in the output
devices.
3.
It regulates the output common-mode current by
establishing a common-mode feedback loop.
The output devices Q
10
and Q
11
work in a common-emitter
configuration, and are Miller-compensated by internal
capacitors, C
MT
and C
MB
.
The output voltage compliance is set by the output devices'
collector resistance R
C
(about 25 ), and by the required load
current I
L
. For instance, a light equivalent load (5 k) allows the
output voltage to swing to within 40 mV of either rail, while
heavier loads cause this figure to deteriorate as R
C
× I
L
.
AD8029/AD8030/AD8040
Rev. A | Page 16 of 20
APPLICATIONS
WIDEBAND OPERATION
+V
S
­V
S
C2
10
µ
F
C1
0.1
µ
F
C4
0.1
µ
F
C3
10
µ
F
V
OUT
+
­
AD8029
R
G
R1
R
F
DISABLE
V
IN
R1 = R
F
||R
G
03679-0-052
Figure 51. Wideband Non-inverting Gain Configuration
+V
S
­V
S
C1
0.1
µ
F
C4
0.1
µ
F
C3
10
µ
F
R1
V
OUT
­
+
AD8029
R
G
R1 = R
F
||R
G
R
F
V
IN
03679-0-053
C2
10
µ
F
DISABLE
Figure 52. Wideband Inverting Gain Configuration
OUTPUT LOADING SENSITIVITY
To achieve maximum performance and low power dissipation,
the designer needs to consider the loading at the output of
AD8029/AD8030/AD8040. Table 5 shows the effects of output
loading and performance.
When operating at unity gain, the effective load at the amplifier
output is the resistance (R
L
) being driven by the amplifier. For
gains other than 1, in noninverting configurations, the feedback
network represents an additional current load at the amplifier
output. The feedback network (R
F
+ R
G
) is in parallel with R
L
,
which lowers the effective resistance at the output of the
amplifier. The lower effective resistance causes the amplifier to
supply more current at the output. Lower values of feedback
resistance increase the current draw, thus increasing the
amplifier's power dissipation.
For example, if using the values shown in Table 5 for a gain of 2,
with resistor values of 2.5 k, the effective load at the output is
1.67 k. For inverting configurations, only the feedback resistor
R
F
is in parallel with the output load. If the load is greater than
that specified in the data sheet, the amplifier can introduce
nonlinearities in its open-loop response, which increases
distortion. Figure 53 and Figure 54 illustrate effective output
loading and distortion performance. Increasing the resistance of
the feedback network can reduce the current consumption, but
has other implications.
FREQUENCY (MHz)
HARMONIC DIS
T
ORTION (dBc
)
0.01
­120
0.1
1.0
10
03679-A
-
008
­40
­50
­60
­70
­80
­90
­100
­110
V
S
= 5V
V
OUT
= 0.1V p-p
R
L
= 5k
R
L
= 2.5k
V
S
= 5V
V
OUT
= 2.0V p-p
SECOND HARMONIC ­ SOLID LINES
THIRD HARMONIC ­ DOTTED LINES
R
L
= 1k
Figure 53. Gain of 1 Distortion
FREQUENCY (MHz)
HARMONIC DIS
T
ORTION (dBc
)
0.01
­120
0.1
1.0
10
03679-A
-
009
­40
­50
­60
­70
­80
­90
­100
­110
V
S
= 5V
V
OUT
= 0.1V p-p
R
F
= R
L
= 1k
V
S
= 5V
V
OUT
= 2.0V p-p
SECOND HARMONIC ­ SOLID LINES
THIRD HARMONIC ­ DOTTED LINES
R
F
= R
L
= 5k
R
F
= R
L
= 2.5k
Figure 54. Gain of 2 Distortion
AD8029/AD8030/AD8040
Rev. A | Page 17 of 20
Table 5. Effect of Load on Performance
Noninverting
Gain
R
F
(k)
R
G
(k)
R
LOAD
(k)
­3 dB SS BW
(MHz)
Peaking
(dB)
HD2 at 1 MHz,
2 V p-p (dB)
HD3 at 1 MHz,
2 V p-p (dB)
Output Noise
(nV/Hz)
1
0
N/A
1
120
0.02
­80 ­72 16.5
1
0
N/A
2
130
0.6
­84 ­83 16.5
1
0
N/A
5
139 1 ­87.5 ­92.5 16.5
2
1
1
1
36 0
­72 ­60 33.5
2 2.5
2.5
2.5
44.5
0.2
­79
­72.5
34.4
2
5
5
5
43 2
­84 ­86 36
­1
1
1
1
40 0.01
­68 ­57 33.6
­1
2.5
2.5
2.5
40 0.05
­74 ­68 34
­1
5
5
5
34 1
­78 ­80 36
The feedback resistance (R
F
|| R
G
) combines with the input
capacitance to form a pole in the amplifier's loop response. This
can cause peaking and ringing in the amplifier's response if the
RC time constant is too low. Figure 55 illustrates this effect.
Peaking can be reduced by adding a small capacitor (1 pF­4 pF)
across the feedback resistor. The best way to find the optimal
value of capacitor is to empirically try it in your circuit. Another
factor of higher resistance values is the impact it has on noise
performance. Higher resistor values generate more noise. Each
application is unique and therefore a balance must be reached
between distortion, peaking, and noise performance. Table 5
outlines the trade-offs that different loads have on distortion,
peaking, and noise performance. In gains of 1, 2, and 10,
equivalent loads of 1 k, 2 k, and 5 k are shown.
With increasing load resistance, the distortion and ­3 dB
bandwidth improve, while the noise and peaking degrade
slightly.
R
L
= 5k
FREQUENCY (MHz)
NORMALIZE
D
CLOS
E
D
-LOOP
GAIN (dB)
1
­8
10
100
1000
03679-A
-
007
2
1
0
­1
­2
­3
­4
­5
­6
R
L
= 2.5k
­7
R
F
= R
L
= 5k
R
F
= R
L
= 2.5k
R
F
= R
L
= 1k
G = +2
G = +1
R
L
= 1k
V
S
= 5V
V
OUT
= 0.1V p-p
Figure 55. Frequency Response for Various Feedback/Load Resistances
DISABLE PIN
The AD8029 disable pin allows the amplifier to be shut down
for power conservation or multiplexing applications. When in
the disable mode, the amplifier draws only 150 µA of quiescent
current. The disable pin control voltage is referenced to the
negative supply. The amplifier enters power-down mode any
time the disable pin is tied to the most negative supply or within
0.8 V of the negative supply. If left open, the amplifier will
operate normally. For switching levels, refer to Table 6.
Table 6. Disable Pin Control Voltage
Supply Voltage
Disable Pin
Voltage
+3 V
+5 V
±5 V
Low
(Disabled)
0 V to <0.8 V
0 V to <0.8 V
­5 V to <­4 .2 V
High
(Enabled)
1.2 V to 3 V
1.2 V to 5 V
­3.8 V to +5 V
AD8029/AD8030/AD8040
Rev. A | Page 18 of 20
CIRCUIT CONSIDERATIONS
PCB Layout
High speed op amps require careful attention to PCB layout to
achieve optimum performance. Particular care must be
exercised to minimize lead lengths of the bypass capacitors.
Excess lead inductance can influence the frequency response
and even cause high frequency oscillations. Using a multilayer
board with an internal ground plane can help reduce ground
noise and enable a more compact layout.
To achieve the shortest possible trace length at the inverting
input, the feedback resistor, R
F
, should be located the shortest
distance from the output pin to the input pin. The return node
of the resistor R
G
should be situated as close as possible to the
return node of the negative supply bypass capacitor.
On multilayer boards, all layers beneath the op amp should be
cleared of metal to avoid creating parasitic capacitive elements.
This is especially true at the summing junction, i.e., the inver-
ting input, ­IN. Extra capacitance at the summing junction can
cause increased peaking in the frequency response and lower
phase margin.
Grounding
To minimize parasitic inductances and ground loops in high
speed, densely populated boards, a ground plane layer is critical.
Understanding where the current flows in a circuit is critical in
the implementation of high speed circuit design. The length of
the current path is directly proportional to the magnitude of the
parasitic inductances and thus the high frequency impedance of
the path. Fast current changes in an inductive ground return
will create unwanted noise and ringing.
The length of the high frequency bypass capacitor pads and
traces is critical. A parasitic inductance in the bypass grounding
works against the low impedance created by the bypass
capacitor. Because load currents flow from supplies as well as
from ground, the load should be placed at the same physical
location as the bypass capacitor ground. For large values of
capacitors, which are intended to be effective at lower
frequencies, the current return path length is less critical.
Power Supply Bypassing
Power supply pins are actually inputs to the op amp. Care must
be taken to provide the op amp with a clean, low noise dc
voltage source.
Power supply bypassing is employed to provide a low imped-
ance path to ground for noise and undesired signals at all
frequencies. This cannot be achieved with a single capacitor
type; but with a variety of capacitors in parallel the bandwidth
of power supply bypassing can be greatly extended. The bypass
capacitors have two functions:
1.
Provide a low impedance path for noise and undesired
signals from the supply pins to ground.
2.
Provide local stored charge for fast switching conditions
and minimize the voltage drop at the supply pins during
transients. This is typically achieved with large electrolytic
capacitors.
Good quality ceramic chip capacitors should be used and
always kept as close as possible to the amplifier package. A
parallel combination of a 0.1 µF ceramic and a 10 µF electrolytic
covers a wide range of rejection for unwanted noise. The 10 µF
capacitor is less critical for high frequency bypassing and, in
most cases, one per supply line is sufficient. The values of
capacitors are circuit-dependant and should be determined by
the system's requirements.
DESIGN TOOLS AND TECHNICAL SUPPORT
Analog Devices is committed to the design process by providing
technical support and online design tools. ADI offers technical
support via free evaluation boards, sample ICs, Spice models,
interactive evaluation tools, application notes, phone and email
support--all available at
www.analog.com
.
AD8029/AD8030/AD8040
Rev. A | Page 19 of 20
OUTLINE DIMENSIONS
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
0.50 (0.0196)
0.25 (0.0099)
×
45°
8°
0°
1.75 (0.0688)
1.35 (0.0532)
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0040)
4
1
8
5
5.00 (0.1968)
4.80 (0.1890)
4.00 (0.1574)
3.80 (0.1497)
1.27 (0.0500)
BSC
6.20 (0.2440)
5.80 (0.2284)
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
COMPLIANT TO JEDEC STANDARDS MS-012AA
Figure 56. 8-Lead Standard Small Outline Package, Narrow Body [SOIC] (R-8)
Dimensions shown in millimeters and (inches)
0.22
0.08
0.46
0.36
0.26
8°
4°
0°
0.30
0.15
1.00
0.90
0.70
SEATING
PLANE
1.10 MAX
3
5
4
2
6
1
2.00 BSC
PIN 1
2.10 BSC
0.65 BSC
1.25 BSC
1.30 BSC
0.10 MAX
0.10 COPLANARITY
COMPLIANT TO JEDEC STANDARDS MO-203AB
Figure 57. 6-Lead Plastic Surface-Mount Package [SC70] (KS-6)
Dimensions shown in millimeters
1
3
5
6
2
8
4
7
2.90 BSC
PIN 1
1.60 BSC
1.95
BSC
0.65 BSC
0.38
0.22
0.15 MAX
1.30
1.15
0.90
SEATING
PLANE
1.45 MAX
0.22
0.08
0.60
0.45
0.30
8°
4°
0°
2.80 BSC
COMPLIANT TO JEDEC STANDARDS MO-178BA
Figure 58. 8-Lead Small Outline Transistor Package [SOT23] (RJ-8)
Dimensions shown in millimeters
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
COPLANARITY
0.10
14
8
7
1
6.20 (0.2441)
5.80 (0.2283)
4.00 (0.1575)
3.80 (0.1496)
8.75 (0.3445)
8.55 (0.3366)
1.27 (0.0500)
BSC
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0039)
0.51 (0.0201)
0.31 (0.0122)
1.75 (0.0689)
1.35 (0.0531)
8°
0°

0.50 (0.0197)
0.25 (0.0098)
1.27 (0.0500)
0.40 (0.0157)
0.25 (0.0098)
0.17 (0.0067)
COMPLIANT TO JEDEC STANDARDS MS-012AB
×
45°
Figure 59. 14-Lead Standard Small Outline Package [SOIC] (R-14)
Dimensions shown in millimeters and (inches)
4.50
4.40
4.30
14
8
7
1
6.40
BSC
PIN 1
5.10
5.00
4.90
0.65
BSC
SEATING
PLANE
0.15
0.05
0.30
0.19
1.20
MAX
1.05
1.00
0.80
0.20
0.09
8°
0°
0.75
0.60
0.45
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153AB-1
Figure 60. 14-Lead Thin Shrink Small Outline Package [TSSOP] (RU-14)
Dimensions shown in millimeters
AD8029/AD8030/AD8040
Rev. A | Page 20 of 20
ORDERING GUIDE
Model
Minimum Ordering Quantity
Temperature Range Package
Description Package
Option Branding
AD8029AR
1
­40°C to +125°C
8-Lead SOIC
R-8
AD8029AR-REEL
2,500
­40°C to +125°C
8-Lead SOIC
R-8
AD8029AR-REEL7
1,000
­40°C to +125°C
8-Lead SOIC
R-8
AD8029AKS-R2
250
­40°C to +125°C
6-Lead SC70
KS-6
H6B
AD8029AKS-REEL
10,000
­40°C to +125°C
6-Lead SC70
KS-6
H6B
AD8029AKS-REEL7
3,000
­40°C to +125°C
6-Lead SC70
KS-6
H6B
AD8030AR
1
­40°C to +125°C
8-Lead SOIC
R-8
AD8030AR-REEL
2,500
­40°C to +125°C
8-Lead SOIC
R-8
AD8030AR-REEL7
1,000
­40°C to +125°C
8-Lead SOIC
R-8
AD8030ARJ-R2
250
­40°C to +125°C
8-Lead SOT23-8
RJ-8
H7B
AD8030ARJ-REEL
10,000
­40°C to +125°C
8-Lead SOT23-8
RJ-8
H7B
AD8030ARJ-REEL7
3,000
­40°C to +125°C
8-Lead SOT23-8
RJ-8
H7B
AD8040AR
1
­40°C to +125°C
14-Lead SOIC
R-14
AD8040AR-REEL
2500
­40°C to +125°C
14-Lead SOIC
R-14
AD8040AR-REEL7
1000
­40°C to +125°C
14-Lead SOIC
R-14
AD8040ARU
1
­40°C to +125°C
14-Lead TSSOP
RU-14
AD8040ARU-REEL
2500
­40°C to +125°C
14-Lead TSSOP
RU-14
AD8040ARU-REEL7
1000
­40°C to +125°C
14-Lead TSSOP
RU-14
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
this product features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
© 2003 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C03679­0­11/03(A)