14-Bit, 500 kSPS PulSARTM

ADC in MSOP/QFN

Preliminary Technical Data

AD7946

Rev Pr D

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
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registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700

www.analog.com

Fax: 781.326.8703

FEATURES

14-bit resolution with no missing codes
Throughput: 500 kSPS
INL: ±0.4 LSB typ, ±1 LSB max (±0.0061 % of FSR)
S/(N + D): 85 dB @ 20 kHz
THD: -100 dB @ 20 kHz
Pseudo-differential analog input range

0 V to V

REF

with V

REF

up to VDD

No pipeline delay
Single-supply 5V operation with

1.8 V/2.5 V/3 V/5 V logic interface

Serial interface SPI®/QSPITM/µWire/DSP compatible
Daisy chain multiple ADCs and BUSY indicator
Power dissipation

3.3 mW @ 5 V/100 kSPS,
3.3 µW @ 5 V/100 SPS

Stand-by current: 1 nA
10-lead package: MSOP (MSOP-8 size) and

QFN (LFCSP), 3 mm × 3 mm same space as SOT-23

Pin-for-pin compatible with the 16-Bit AD7686

APPLICATIONS

Battery-powered equipment
Data acquisition
Instrumentation
Medical instruments
Process control

Table 1. MSOP, QFN (LFCSP)/SOT-23 14 and16-Bit ADC

Type

100 kSPS

250 kSPS

500 kSPS

16-Bit True
Differential

AD7684

AD7687

AD7688

16-Bit Pseudo
Differential/Unipolar

AD7683

AD7685

AD7694

AD7686

16-Bit Unipolar

AD7680

14-Bit Pseudo
Differential/Unipolar

AD7942

AD7946

14-Bit Unipolar

AD7940

APPLICATION DIAGRAM

AD7946

REF

GND

VDD

IN+

IN

VIO

SDI

SCK

SDO

CNV

1.8 TO VDD

3- OR 4-WIRE INTERFACE
(SPI, DAISY CHAIN, CS)

0.5 TO 5V

0 TO VREF

Figure 1.

GENERAL DESCRIPTION

The AD7946 is a 14-bit, charge redistribution successive
approximation, analog-to-digital converter (ADC) that operates
from a single 5V power supply, VDD. It contains a low power,
high speed, 14-bit sampling ADC with no missing codes, an
internal conversion clock, and a versatile serial interface port.
The part also contains a low noise, wide bandwidth, short
aperture delay track-and-hold circuit. On the CNV rising edge,
it samples an analog input IN+ between 0 V to REF with respect
to a ground sense IN-. The reference voltage, REF, is applied
externally and can be set up to the supply voltage.

Its power scales linearly with throughput.

The SPI compatible serial interface also features the ability,
using the SDI input, to daisy chain several ADCs on a single 3-
wire bus and provides an optional BUSY indicator. It is
compatible with 1.8 V, 2.5 V, 3 V, or 5 V logic using the separate
supply VIO.

The AD7946 is housed in a 10-lead MSOP or a 10-lead QFN
(LFCSP) with operation specified from -40°C to +85°C.

AD7946

Preliminary Technical Data

Rev Pr D | Page 2 of 27

TABLE OF CONTENTS

Specifications..................................................................................... 3

Timing Specifications....................................................................... 5

Absolute Maximum Ratings............................................................ 6

ESD Caution.................................................................................. 6

Pin Configuration and Function Descriptions............................. 7

Terminology ...................................................................................... 8

Typical Performance Characteristics ............................................. 9

Circuit Information.................................................................... 12

Converter Operation.................................................................. 12

Typical Connection Diagram ................................................... 13

Digital Interface.......................................................................... 17

Application Hints ........................................................................... 24

Layout .......................................................................................... 24

Evaluating the AD7946's Performance.................................... 24

Outline Dimensions ....................................................................... 25

Ordering Guide .......................................................................... 26

REVISION HISTORY

5/04--Revision D: Preliminary

Preliminary Technical Data

AD7946

Rev Pr D | Page 3 of 27

SPECIFICATIONS

VDD = 4.5 V to 5.5 V, VIO = 2.3 V to VDD, V

REF

= VDD, T

= 40°C to +85°C, unless otherwise noted.

Table 2.

Parameter Conditions

Min

Typ

Max

Unit

RESOLUTION

Bits

ANALOG INPUT

Voltage Range

IN+ - IN-

REF

Absolute Input Voltage

IN+

-0.1

VDD + 0.1

IN-

-0.1

0.1

Analog Input CMRR

= 250 kHz

Leakage Current at 25°C

Acquisition Phase

Input Impedance

ACCURACY

No Missing Codes

Bits

Differential Linearity Error

-0.7

±0.25

+0.7

LSB

Integral Linearity Error

-1

±0.4

LSB

Transition Noise

REF = VDD = 5 V

0.33

LSB

Gain Error

, T

MIN

to T

MAX

±TBD

LSB

Gain Error Temperature Drift

±TBD

ppm/°C

Offset Error

, T

MIN

to T

MAX

±TBD

Offset Temperature Drift

±TBD

ppm/°C

Power Supply Sensitivity

VDD = 5V

± 5%

±TBD

LSB

THROUGHPUT

Conversion Rate

500

kSPS

Transient Response

Full-Scale Step

400

AC ACCURACY

Signal-to-Noise f

= 20 kHz, V

REF

= 5 V

Spurious-Free Dynamic Range

= 20 kHz

-100

Total Harmonic Distortion

= 20 kHz

-100

Signal-to-(Noise + Distortion)

= 20 kHz, V

REF

= 5 V

= 20 kHz, V

REF

= 5 V, -60 dB

Input

Intermodulation Distortion

TBD

LSB means least significant bit. With the 5 V input range, one LSB is 305.2 µV.

See Terminology section. These specifications do include full temperature range variation but do not include the error contribution from the external reference.

All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full-scale, unless otherwise specified.

IN1

= 21.4 kHz, f

IN2

= 18.9 kHz, each tone at -7 dB below full-scale.

AD7946

Preliminary Technical Data

Rev Pr D | Page 4 of 27

VDD = 4.5 V to 5.5 V, VIO = 2.3 V to VDD, V

REF

= VDD, T

= 40°C to +85°C, unless otherwise noted.

Table 3.

Parameter Conditions

Min

Typ

Max

Unit

REFERENCE

Voltage Range

0.5

VDD + 0.3

Load Current

500 kSPS, REF = 5 V

TBD

µA

SAMPLING DYNAMICS

-3 dB Input Bandwidth

MHz

Aperture Delay

VDD = 5 V

2.5

DIGITAL INPUTS

Logic Levels

0.3

0.3 × VIO

0.7 × VIO

VIO + 0.3

-1

µA

-1

µA

DIGITAL OUTPUTS

Data Format

Serial 14 Bits Straight Binary

Pipeline Delay

Conversion Results Available Immediately
after Completed Conversion

SINK

= +500 µA

0.4

SOURCE

= -500 µA

VIO - 0.3

POWER SUPPLIES

VDD Specified

Performance

4.5

5.5

VIO

Specified Performance

2.3

VDD + 0.3

VIO Range

1.8

VDD + 0.3

Standby Current

1, 2

VDD and VIO = 5 V, 25°C

Power Dissipation

VDD = 5 V, 100 SPS Throughput

3.3

µW

VDD = 5 V, 100 kSPS Throughput

3.3

VDD = 5 V, 500 kSPS Throughput

TEMPERATURE RANGE

Specified Performance

MIN

to T

MAX

-40

+85

°C

With all digital inputs forced to VIO or GND as required.

During acquisition phase.

Contact Analog Devices for extended temperature range.

Preliminary Technical Data

AD7946

Rev Pr D | Page 5 of 27

TIMING SPECIFICATIONS

-40°C to +85°C, VDD = 4.5 V to 5.5 V, VIO = 2.3 V to 5.5 V or VDD + 0.3 V, whichever is the lowest, unless otherwise stated.

Table 4.

Symbol Min Typ Max Unit

Conversion Time: CNV Rising Edge to Data Available

CONV

0.5

1.6

µs

Acquisition Time

ACQ

400

Time between Conversions

CYC

µs

CNV Pulse Width ( CS Mode )

CNVH

SCK Period ( CS Mode )

SCK

SCK Period ( Chain Mode )

SCK

VIO above 4.5 V

VIO above 3 V

VIO above 2.7 V

VIO above 2.3 V

SCK Low Time

SCKL

SCK High Time

SCKH

SCK Falling Edge to Data Remains Valid

HSDO

SCK Falling Edge to Data Valid Delay

DSDO

VIO above 4.5 V

VIO above 3 V

VIO above 2.7 V

VIO above 2.3 V

CNV or SDI Low to SDO D15 MSB Valid (CS Mode)

VIO above 4.5 V

VIO above 2.7 V

VIO above 2.3 V

CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode)

DIS

SDI Valid Setup Time from CNV Rising Edge (CS Mode)

SSDICNV

15 ns

SDI Valid Hold Time from CNV Rising Edge (CS Mode)

HSDICNV

0 ns

SCK Valid Setup Time from CNV Rising Edge (Chain Mode)

SSCKCNV

SCK Valid Hold Time from CNV Rising Edge (Chain Mode)

HSCKCNV

SDI Valid Setup Time from SCK Falling Edge (Chain Mode)

SSDISCK

5 ns

SDI Valid Hold Time from SCK Falling Edge (Chain Mode)

HSDISCK

4 ns

SDI High to SDO High (Chain Mode with BUSY indicator)

DSDOSDI

VIO above 4.5 V

VIO above 2.3 V

See Figure 2 and Figure 3 for load conditions.

AD7946

Preliminary Technical Data

Rev Pr D | Page 6 of 27

ABSOLUTE MAXIMUM RATINGS

Table 5.

Parameter Rating

Analog Inputs

IN+

, IN-

, REF

GND - 0.3 V to VDD + 0.3 V
or ±130 mA

Supply Voltages

VDD, VIO to GND

-0.3 V to +7 V

VDD to VIO

±7 V

Digital Inputs to GND

-0.3 V to VIO + 0.3 V

Digital Outputs to GND

-0.3 V to VIO + 0.3 V

Storage Temperature Range

-65°C to +150°C

Junction Temperature

150°C

Thermal Impedance

200°C/W (MSOP-10)

Thermal Impedance

44°C/W (MSOP-10)

Lead Temperature Range

Vapor Phase (60 sec)

215°C

Infrared (15 sec)

220°C

See the Analog Input section.

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

500

1.4V

TO SDO

50pF

02968-P

r
H-002

Figure 2. Load Circuit for Digital Interface Timing

30% VIO

70% VIO

2V OR VIO 0.5V

0.8V OR 0.5V

2V OR VIO 0.5V

DELAY

NOTES
1. 2V IF VIO ABOVE 2.5V, VIO 0.5V IF VIO BELOW 2.5V.
2. 0.8V IF VIO ABOVE 2.5V, 0.5V IF VIO BELOW 2.5V.

02968-P

r
H-003

Figure 3. Voltage Reference Levels for Timing

Preliminary Technical Data

AD7946

Rev Pr D | Page 7 of 27

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

AD7946

REF

VDD

IN+

IN

GND

VIO

SDI

SCK

SDO

CNV

Figure 4.10-Lead MSOP and QFN (LFCSP) Pin Configuration

Table 6. Pin Function Descriptions

Pin No.

Mnemonic

Type

Function

1 REF AI

Reference Input Voltage. The REF range is from 0.5 V to VDD. It is referred to the GND pin. This pin should
be decoupled closely to the pin with a 10 µF capacitor.

2 VDD P

Power

Supply.

3 IN+ AI

Analog Input. It is referred to in IN-. The voltage range, i.e., the difference between IN+ and IN-, is 0 V to
V

REF

IN-

Analog Input Ground Sense. To be connected to the analog ground plane or to a remote sense ground.

GND

Power Supply Ground.

6 CNV DI

Convert Input. This input has multiple functions. On its leading edge, it initiates the conversions and
selects the interface mode of the part, chain or CS mode. In CS mode, it enables the SDO pin when low. In
chain mode, the data should be read when CNV is high.

SDO

Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK.

SCK

Serial Data Clock Input. When the part is selected, the conversion result is shifted out by this clock.

SDI

Serial Data Input. This input provides multiple features. It selects the interface mode of the ADC as follows:
Chain mode is selected if SDI is low during the CNV rising edge. In this mode, SDI is used as a data input to
daisy chain the conversion results of two or more ADCs onto a single SDO line. The digital data level on
SDI is output on SDO with a delay of 14 SCK cycles.
CS mode is selected if SDI is high during the CNV rising edge. In this mode, either SDI or CNV can enable
the serial output signals when low, and if SDI or CNV is low when the conversion is complete, the BUSY
indicator feature is enabled.

10 VIO P Input/Output Interface Digital Power. Nominally at the same supply as the host interface (1.8 V, 2.5 V, 3 V,

or 5 V).

AI = Analog Input, DI = Digital Input, DO = Digital Output, and P = Power

AD7946

Preliminary Technical Data

Rev Pr D | Page 8 of 27

TERMINOLOGY

Integral Nonlinearity Error (INL)
Linearity error refers to the deviation of each individual code
from a line drawn from negative full scale through positive full
scale. The point used as negative full scale occurs 1/2 LSB
before the first code transition. Positive full scale is defined as a
level 1 1/2 LSB beyond the last code transition. The deviation is
measured from the middle of each code to the true straight line
(Figure 21).

Differential Nonlinearity Error (DNL)
In an ideal ADC, code transitions are 1 LSB apart. DNL is the
maximum deviation from this ideal value. It is often specified in
terms of resolution for which no missing codes are guaranteed.

Offset Error
The first transition should occur at a level 1/2 LSB above analog
ground (152.6 µV for the 0 V to 5 V range). The offset error is
the deviation of the actual transition from that point.

Gain Error
The last transition (from 111 . . . 10 to 111 . . . 11) should occur
for an analog voltage 1 1/2 LSB below the nominal full scale
(4.999542 V for the 0 V to 5 V range). The gain error is the
deviation of the actual level of the last transition from the ideal
level after the offset has been adjusted out.

Spurious-Free Dynamic Range (SFDR)
The difference, in decibels (dB), between the rms amplitude of
the input signal and the peak spurious signal.

Effective Number of Bits (ENOB)
ENOB is a measurement of the resolution with a sine wave
input. It is related to S/(N+D) by the following formula

[

]

(

)

ENOB

and is expressed in bits.

Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first five harmonic
components to the rms value of a full-scale input signal and is
expressed in dB.

Signal-to-Noise Ratio (SNR)
SNR is the ratio of the rms value of the actual input signal to the
rms sum of all other spectral components below the Nyquist
frequency, excluding harmonics and dc. The value for SNR is
expressed in dB.

Signal-to-(Noise + Distortion) Ratio (S/[N+D])
S/(N+D) is the ratio of the rms value of the actual input signal
to the rms sum of all other spectral components below the
Nyquist frequency, including harmonics but excluding dc. The
value for S/(N+D) is expressed in dB.

Aperture Delay
Aperture delay is a measure of the acquisition performance and
is the time between the rising edge of the CNV input and when
the input signal is held for a conversion.

Transient Response
The time required for the ADC to accurately acquire its input
after a full-scale step function was applied.

AD7946

Preliminary Technical Data

Rev Pr D | Page 12 of 27

SW+

MSB

4,096C

IN+

LSB

COMP

CONTROL

LOGIC

SWITCHES CONTROL

BUSY

OUTPUT CODE

CNV

REF

GND

IN

8,192C

SW

MSB

4,096C

LSB

8,192C

Figure 20. ADC Simplified Schematic

CIRCUIT INFORMATION

The AD7946 is a fast, low power, single-supply, precise 14-bit
ADC using a successive approximation architecture.

The AD7946 is capable of converting 500,000 samples per
second (500 kSPS) and powers down between conversions.
When operating at 100 SPS, for example, it consumes typically
3.3µW, ideal for battery-powered applications.

The AD7946 provides the user with an on-chip track-and-hold
and does not exhibit any pipeline delay or latency, making it
ideal for multiple multiplexed channel applications.

The AD7946 is specified from 4.5 V to 5.5 V, and can be
interfaced to either 5 V, 3.3 V, 2.5 V, or 1.8 V digital logic. It is
housed in a 10-lead MSOP or a tiny 10-lead QFN (LFCSP) that
combines space savings and allows flexible configurations.

It is pin-for-pin-compatible with the 16 Bit ADC

AD7686

CONVERTER OPERATION

The AD7946 is a successive approximation ADC based on a
charge redistribution DAC. Figure 20 shows the simplified
schematic of the ADC. The capacitive DAC consists of two
identical arrays of 14 binary weighted capacitors, which are
connected to the two comparator inputs.

During the acquisition phase, terminals of the array tied to the
comparator's input are connected to GND via SW+ and SW-.
All independent switches are connected to the analog inputs.
Thus, the capacitor arrays are used as sampling capacitors and
acquire the analog signal on the IN+ and IN- inputs. When the
acquisition phase is complete and the CNV input goes high, a
conversion phase is initiated. When the conversion phase
begins, SW+ and SW- are opened first. The two capacitor
arrays are then disconnected from the inputs and connected to
the GND input. Therefore, the differential voltage between the
inputs IN+ and IN- captured at the end of the acquisition phase
is applied to the comparator inputs, causing the comparator to
become unbalanced. By switching each element of the capacitor
array between GND and REF, the comparator input varies by
binary weighted voltage steps (V

REF

/2, V

REF

/4 . . . V

REF

/16384).

The control logic toggles these switches, starting with the MSB,
in order to bring the comparator back into a balanced
condition. After the completion of this process, the part returns
to the acquisition phase and the control logic generates the
ADC output code and a BUSY signal indicator.

Because the AD7946 has an on-board conversion clock, the
serial clock, SCK, is not required for the conversion process.

Preliminary Technical Data

AD7946

Rev Pr D | Page 13 of 27

Transfer Functions

The ideal transfer characteristic for the AD7946 is shown in
Figure 21 and Table 7.

000...000

000...001

000...010

111...101

111...110

111...111

ADC CODE

TRAIGHT BINARY

)

ANALOG INPUT

+FS 1.5 LSB

+FS 1 LSB

FS + 1 LSB

FS

FS + 0.5 LSB

02968-P

r
H-006

Figure 21. ADC Ideal Transfer Function

Table 7. Output Codes and Ideal Input Voltages

Description

Analog Input
V

REF

= 5 V

Digital Output Code Hexa

FSR 1 LSB

4.999695 V

3FFF

Midscale + 1 LSB

2.500305 V

2001

Midscale

2.5 V

2000

Midscale 1 LSB

2.499695 V

1FFF

FSR + 1 LSB

305.2 µV

0001

FSR

0 V

0000

This is also the code for an overranged analog input (V

IN+

above V

REF

GND

This is also the code for an underranged analog input (V

IN+

below V

GND

TYPICAL CONNECTION DIAGRAM

Figure 22 shows an example of the recommended connection
diagram for the AD7946 when multiple supplies are available.

AD7946

REF

GND

VDD

IN

IN+

VIO

SDI

SCK

SDO

CNV

3- OR 4-WIRE INTERFACE (NOTE 5)

100nF

(NOTE 2)

2V

1.8V TO VDD

REF

0 TO VREF

2.7nF

(NOTE 3)

(NOTE 4)

(NOTE 1)

NOTE 1: SEE REFERENCE SECTION FOR REFERENCE SELECTION.
NOTE 2: C

REF

IS USUALLY

NOTE 3: SEE DRIVER AMPLIFIER CHOICE SECTION.
NOTE 4: OPTIONAL FILTER. SEE ANALOG INPUT SECTION.
NOTE 5: SEE DIGITAL INTERFACE FOR MOST CONVENIENT INTERFACE MODE.

A 10

F CERAMIC CAPACITOR (X5R).

Figure 22. Typical Application Diagram with multiple supplies

AD7946

Preliminary Technical Data

Rev Pr D | Page 14 of 27

Analog Input

Figure 23 shows an equivalent circuit of the input structure of
the AD7946.

The two diodes, D1 and D2, provide ESD protection for the
analog inputs IN+ and IN-. Care must be taken to ensure that
the analog input signal never exceeds the supply rails by more
than 0.3 V because this will cause these diodes to become
forward-biased and start conducting current. However, these
diodes can handle a forward-biased current of 130 mA
maximum. For instance, these conditions could eventually
occur when the input buffer's (U1) supplies are different from
VDD. In such a case, an input buffer with a short-circuit
current limitation can be used to protect the part.

PIN

IN+

OR IN

GND

VDD

Figure 23. Equivalent Analog Input Circuit

This analog input structure allows the sampling of the
differential signal between IN+ and IN-. By using this
differential input, small signals common to both inputs are
rejected, as shown in Figure 24, which represents the typical
CMRR over frequency. For instance, by using IN- to sense a
remote signal ground, ground potential differences between the
sensor and the local ADC ground are eliminated.

Figure 24. Analog Input CMRR vs. Frequency

During the acquisition phase, the impedance of the analog
input IN+ can be modeled as a parallel combination of
capacitor C1 and the network formed by the series connection
of R1 and C2. C1 is primarily the pin capacitance. R1 is typically
600 and is a lumped component made up of some serial
resistors and the on resistance of the switches. C2 is typically
30 pF and is mainly the ADC sampling capacitor. During the
conversion phase, where the switches are opened, the input
impedance is limited to C1. R1 and C2 make a 1-pole, low-pass
filter that reduces undesirable aliasing effect and limits the
noise.

When the source impedance of the driving circuit is low, the
AD7946 can be driven directly. Large source impedances
significantly affect the ac performance, especially total
harmonic distortion (THD). The dc performances are less
sensitive to the input impedance. The maximum source
impedance depends on the amount of THD that can be
tolerated. The THD degrades as a function of the source
impedance and the maximum input frequency, as shown in
Figure 25.

Figure 25. THD vs. Analog Input Frequency and Source Resistance

Preliminary Technical Data

AD7946

Rev Pr D | Page 15 of 27

Driver Amplifier Choice

Although the AD7946 is easy to drive, the driver amplifier
needs to meet the following requirements:

The noise generated by the driver amplifier needs to be
kept as low as possible in order to preserve the SNR and
transition noise performance of the AD7946. Note that the
AD7946 has a noise much lower than most of the other 14-
bit ADCs and, therefore, can be driven by a noisier op amp
while preserving the same or better system performance.
The noise coming from the driver is filtered by the AD7946
analog input circuit 1-pole, low-pass filter made by R1 and
C2 or by the external filter, if one is used.

For ac applications, the driver needs to have a THD
performance suitable to that of the AD7946. Figure 12
gives the THD versus frequency that the driver should
exceed.

For multichannel multiplexed applications, the driver
amplifier and the AD7946 analog input circuit must be
able to settle for a full-scale step of the capacitor array at a
14-bit level (0.006%). In the amplifier's data sheet, settling
at 0.1% to 0.01% is more commonly specified. This could
differ significantly from the settling time at a 14-bit level
and should be verified prior to driver selection.

Table 8. Recommended Driver Amplifiers.

Amplifier

Typical Application

AD8021

Very low noise and high frequency

AD8022

Low noise and high frequency

OP184

Low power, low noise, and low frequency

AD8605

AD8615

5 V single-supply, low power

AD8519

Small, low power and low frequency

AD8031

High frequency and low power

Voltage Reference Input

The AD7946 voltage reference input, REF, has a dynamic input
impedance and should therefore be driven by a low impedance
source with efficient decoupling between the REF and GND
pins as explained in the Layout section.

When REF is driven by a very low impedance source, e.g., a
reference buffer using the

AD8031

or the

AD8605

, a 10 µF

(X5R, 0805 size) ceramic chip capacitor is appropriate for
optimum performance.

If an unbuffered reference voltage is used, the decoupling value
depends on the reference used. For instance, a 22 µF (X5R, 1206
size) ceramic chip capacitor is appropriate for optimum
performance using a low temperature drift

ADR43x

reference.

If desired, smaller reference decoupling capacitor values down
to 2.2 µF can be used with a minimal impact on performance,
especially DNL.

AD7946

Preliminary Technical Data

Rev Pr D | Page 16 of 27

Power Supply

The AD7946 is specified 4.5 V to 5.5 V. It uses two power
supply pins: a core supply VDD and a digital input/output
interface supply VIO. VIO allows direct interface with any logic
between 1.8 V and VDD. To reduce the supplies needed, the
VIO and VDD can be tied together. The AD7946 is
independent of power supply sequencing between VIO and
VDD. Additionally, it is very insensitive to power supply
variations over a wide frequency range, as shown in Figure 26,
which represents PSRR over frequency.

Figure 26. PSRR vs. Frequency

The AD7946 powers down automatically at the end of each
conversion phase and, therefore, the power scales linearly with
the sampling rate as shown in see Figure 27. This makes the
part ideal for low sampling rate (even a few Hz) and low
battery-powered applications.

Figure 27. Operating Currents vs. Sampling Rate

Supplying the ADC from the Reference

For simplified applications, the AD7946, with its low operating
current, can be supplied directly using the reference circuit, as
shown in Figure 28. The reference line can be driven by either:

The system power supply directly

A reference voltage with enough current output
capability, such as the ADR43x

A reference buffer, such as the AD8031, that can also
filter the system power supply, as shown in Figure 28.

AD8031

AD7946

VIO

REF

VDD

10k

(NOTE 1)

NOTE 1: OPTIONAL REFERENCE BUFFER AND FILTER

Figure 28. Example of Application Circuit

Preliminary Technical Data

AD7946

Rev Pr D | Page 17 of 27

DIGITAL INTERFACE

Though the AD7946 has a reduced number of pins, it offers
flexibility in its serial interface modes.

The AD7946, when in CS mode, is compatible with SPI, QSPI,
digital hosts, and DSPs, e.g., Blackfin® ADSP-BF53x or ADSP-
219x). This interface can use either 3-wire or 4-wire. A 3-wire
interface using the CNV, SCK, and SDO signals minimizes
wiring connections useful, for instance, in isolated applications.
A 4-wire interface using the SDI, CNV, SCK, and SDO signals
allows CNV, which initiates the conversions, to be independent
of the readback timing (SDI). This is useful in low jitter
sampling or simultaneous sampling applications.

The AD7946, when in chain mode, provides a daisy chain
feature using the SDI input for cascading multiple ADCs on a
single data line similar to a shift register.

The mode in which the part operates depends on the SDI level
when the CNV rising edge occurs. The CS mode is selected if
SDI is high and the chain mode is selected if SDI is low. The
SDI hold time is such that when SDI and CNV are connected
together, the chain mode is always selected.

In either mode, the AD7946 offers the flexibility to optionally
force a start bit in front of the data bits. This start bit can be
used as a BUSY signal indicator to interrupt the digital host and
trigger the data reading. Otherwise, without a BUSY indicator,
the user must time out the maximum conversion time prior to
readback.

The BUSY indicator feature is enabled as follows:

In the CS mode, if CNV or SDI is low when the ADC
conversion ends (Figure 32 and Figure 36).

In the chain mode, if SCK is high during the CNV rising edge
(Figure 40).

AD7946

Preliminary Technical Data

Rev Pr D | Page 18 of 27

CS MODE 3-Wire, No BUSY Indicator

This mode is usually used when a single AD7946 is connected
to an SPI compatible digital host. The connection diagram is
shown in Figure 29 and the corresponding timing is given in
Figure 30.

With SDI tied to VIO, a rising edge on CNV initiates a
conversion, selects the CS mode, and forces SDO to high
impedance. Once a conversion is initiated, it will continue to
completion irrespective of the state of CNV. For instance, it
could be useful to bring CNV low to select other SPI devices,
such as analog multiplexers, but CNV must be returned high
before the minimum conversion time and held high until the
maximum conversion time to avoid the generation of the BUSY
signal indicator. When the conversion is complete, the AD7946
enters the acquisition phase and powers down. When CNV
goes low, the MSB is output onto SDO. The remaining data bits

are then clocked by subsequent SCK falling edges. The data is
valid on both SCK edges. Although the rising edge can be used
to capture the data, a digital host also using the SCK falling edge
will allow a faster reading rate provided it has an acceptable
hold time. After the 14th SCK falling edge or when CNV goes
high, whichever is earlier, SDO returns to high impedance.

CNV

SCK

SDO

SDI

DATA IN

CLK

CONVERT

VIO

DIGITAL HOST

AD7946

Figure 29. CS Mode 3-Wire, No BUSY Indicator

Connection Diagram (SDI High)

04656-P

r
C-008

SDO

D13

D12

D11

DIS

SCK

SCKL

SCKH

HSDO

DSDO

CNV

CONVERSION

ACQUISITION

CONV

CYC

ACQUISITION

SDI = 1

CNVH

ACQ

Figure 30. CS Mode 3-Wire, No BUSY Indicator Serial Interface Timing (SDI High)

Preliminary Technical Data

AD7946

Rev Pr D | Page 19 of 27

CS Mode 3-Wire with BUSY Indicator

This mode is usually used when a single AD7946 is connected
to an SPI compatible digital host having an interrupt input.

The connection diagram is shown in Figure 31 and the
corresponding timing is given in Figure 32.

With SDI tied to VIO, a rising edge on CNV initiates a
conversion, selects the CS mode, and forces SDO to high
impedance. SDO is maintained in high impedance until the
completion of the conversion irrespective of the state of CNV.
Prior to the minimum conversion time, CNV could be used to
select other SPI devices, such as analog multiplexers, but CNV
must be returned low before the minimum conversion time and
held low until the maximum conversion time to guarantee the
generation of the BUSY signal indicator. When the conversion
is complete, SDO goes from high impedance to low. With a
pull-up on the SDO line, this transition can be used as an
interrupt signal to initiate the data reading controlled by the
digital host. The AD7946 then enters the acquisition phase and

powers down. The data bits are then clocked out, MSB first, by
subsequent SCK falling edges. The data is valid on both SCK
edges. Although the rising edge can be used to capture the data,
a digital host also using the SCK falling edge will allow a faster
reading rate provided it has an acceptable hold time. After the
optional 15th SCK falling edge, or when CNV goes high,
whichever is earlier, SDO returns to high impedance.

CNV

SCK

SDO

SDI

DATA IN

IRQ

CLK

CONVERT

VIO

DIGITAL HOST

AD7946

47k

Figure 31. CS Mode 3-Wire with BUSY Indicator

Connection Diagram (SDI High)

04656-P

r
C-010

SDO

D13

D12

DIS

SCK

SCKL

SCKH

HSDO

DSDO

CNV

CONVERSION

ACQUISITION

CONV

CYC

CNVH

ACQ

ACQUISITION

SDI = 1

Figure 32. CS Mode 3-Wire with BUSY Indicator Serial Interface Timing (SDI High)

AD7946

Preliminary Technical Data

Rev Pr D | Page 20 of 27

CS Mode 4-Wire, No BUSY Indicator

This mode is usually used when multiple AD7946s are
connected to an SPI compatible digital host.

A connection diagram example using two AD7946s is shown in
Figure 33 and the corresponding timing is given in Figure 34.

With SDI high, a rising edge on CNV initiates a conversion,
selects the CS mode, and forces SDO to high impedance. In this
mode, CNV must be held high during the conversion phase and
the subsequent data readback (if SDI and CNV are low, SDO is
driven low). Prior to the minimum conversion time, SDI could
be used to select other SPI devices, such as analog multiplexers,
but SDI must be returned high before the minimum conversion

time and held high until the maximum conversion time to
avoid the generation of the BUSY signal indicator. When the
conversion is complete, the AD7946 enters the acquisition
phase and powers down. Each ADC result can be read by
bringing low its SDI input which consequently outputs the MSB
onto SDO. The remaining data bits are then clocked by
subsequent SCK driving edges. The data is valid on both SCK
edges. Although the nondriving edge can be used to capture the
data, a digital host also using the SCK falling edge will allow a
faster reading rate provided it has an acceptable hold time. After
the 14th SCK falling edge, or when SDI goes high, whichever is
earlier, SDO returns to high impedance and another AD7946
can be read.

CNV

SCK

SDO

SDI

DATA IN
CLK

CS1
CONVERT

CS2

DIGITAL HOST

AD7946

CNV

SCK

SDO

SDI

AD7946

Figure 33. CS Mode 4-Wire, No BUSY Indicator Connection Diagram

04656-P

r
C-012

SDO

D13

D12

D11

DIS

SCK

HSDO

DSDO

CONVERSION

ACQUISITION

CONV

CYC

ACQ

ACQUISITION

SDI(CS1)

CNV

SSDICNV

HSDICNV

SCK

SCKL

SCKH

D13

D12

SDI(CS2)

Figure 34. CS Mode 4-Wire, No BUSY Indicator Serial Interface Timing

Preliminary Technical Data

AD7946

Rev Pr D | Page 21 of 27

CS Mode 4-Wire with BUSY Indicator

This mode is usually used when a single AD7946 is connected
to an SPI compatible digital host, which has an interrupt input,
and it is desired to keep CNV, which is used to sample the
analog input, independent of the signal used to select the data
reading. This requirement is particularly important in
applications where low jitter on CNV is desired.

The connection diagram is shown in Figure 35 and the
corresponding timing is given in Figure 36.

low. With a pull-up on the SDO line, this transition can be used
as an interrupt signal to initiate the data readback controlled by
the digital host. The AD7946 then enters the acquisition phase
and powers down. The data bits are then clocked out, MSB first,
by subsequent SCK driving edges. The data is valid on both
SCK edges. Although the rising edge can be used to capture the
data, a digital host also using the SCK falling edge will allow a
faster reading rate provided it has an acceptable hold time. After
the optional 15th SCK falling edge, or SDI going high,
whichever is earlier, the SDO returns to high impedance.

CNV

SCK

SDO

SDI

DATA IN

IRQ

CLK

CONVERT

CS1

VIO

DIGITAL HOST

AD7946

47k

Figure 35. CS Mode 4-Wire with BUSY Indicator Connection Diagram

04656-P

r
C-014

SDO

D13

D12

DIS

SCK

SCKL

SCKH

HSDO

DSDO

CONVERSION

ACQUISITION

CONV

CYC

ACQ

ACQUISITION

SDI

CNV

SSDICNV

HSDICNV

Figure 36. CS Mode 4-Wire with BUSY Indicator Serial Interface Timing

AD7946

Preliminary Technical Data

Rev Pr D | Page 22 of 27

Chain Mode, No BUSY Indicator

This mode can be used to daisy chain multiple AD7946s on a 3-
wire serial interface. This feature is useful for reducing
component count and wiring connections, e.g., in isolated
multiconverter applications or for systems with a limited
interfacing capacity. Data readback is analogous to clocking a
shift register.

A connection diagram example using two AD7946s is shown in
Figure 37 and the corresponding timing is given in Figure 38.

When SDI and CNV are low, SDO is driven low. With SCK low,
a rising edge on CNV initiates a conversion, selects the chain
mode, and disables the BUSY indicator. In this mode, CNV is
held high during the conversion phase and the subsequent data
readback. When the conversion is complete, the MSB is output

onto SDO and the AD7946 enters the acquisition phase and
powers down. The remaining data bits stored in the internal
shift register are then clocked by subsequent SCK falling edges.
For each ADC, SDI feeds the input of the internal shift register
and is clocked by the SCK falling edge. Each ADC in the chain
outputs its data MSB first, and 14 × N clocks are required to
readback the N ADCs. The data is valid on both SCK edges.
Although the rising edge can be used to capture the data, a
digital host also using the SCK falling edge will allow a faster
reading rate and, consequently more AD7946s in the chain,
provided the digital host has an acceptable hold time. The
maximum conversion rate may be reduced due to the total
readback time. For instance, with a 5 ns digital host set-up time
and 3 V interface, up to five AD7946s running at a conversion
rate of 333 kSPS can be daisy-chained on a 3-wire port.

CNV

SCK

SDO

SDI

CLK

CONVERT

DATA IN

DIGITAL HOST

AD7946

CNV

SCK

SDO

SDI

AD7946

Figure 37. Chain Mode, No BUSY Indicator Connection Diagram

04656-P

r
C-016

SDO

= SDI

SCK

SSDISCK

HSDISC

CONVERSION

ACQUISITION

CONV

CYC

ACQ

ACQUISITION

CNV

SCK

SCKL

SCKH

SDI

= 0

SDO

HSDO

DSDO

SSCKCNV

HSCKCNV

Figure 38. Chain Mode, No BUSY Indicator Serial Interface Timing

Preliminary Technical Data

AD7946

Rev Pr D | Page 23 of 27

Chain Mode with BUSY Indicator

This mode can also be used to daisy chain multiple AD7946s on
a 3-wire serial interface while providing a BUSY indicator. This
feature is useful for reducing component count and wiring
connections, e.g., in isolated multiconverter applications or for
systems with a limited interfacing capacity. Data readback is
analogous to clocking a shift register.

A connection diagram example using three AD7946s is shown
in Figure 39 and the corresponding timing is given in Figure 40.

When SDI and CNV are low, SDO is driven low. With SCK
high, a rising edge on CNV initiates a conversion, selects the
chain mode, and enables the BUSY indicator feature. In this
mode, CNV is held high during the conversion phase and the
subsequent data readback. When all ADCs in the chain have
completed their conversions, the nearend ADC ( ADC C in

Figure 39) SDO will be driven high. This transition on SDO can
be used as a BUSY indicator to trigger the data readback
controlled by the digital host. The AD7946 then enters the
acquisition phase and powers down. The data bits stored in the
internal shift register are then clocked out, MSB first, by
subsequent SCK falling edges. For each ADC, SDI feeds the
input of the internal shift register and is clocked by the SCK
falling edge. Each ADC in the chain outputs its data MSB first,
and 14 × N + 1 clocks are required to readback the N ADCs.
Although the rising edge can be used to capture the data, a
digital host also using the SCK falling edge will allow a faster
reading rate and, consequently more AD7946s in the chain,
provided the digital host has an acceptable hold time. For
instance, with a 5 ns digital host set-up time and 3 V interface,
up to five AD7946s running at a conversion rate of 333 kSPS
can be daisy-chained to a single 3-wire port.

CNV

SCK

SDO

SDI

CLK

CONVERT

DATA IN

IRQ

DIGITAL HOST

AD7946

CNV

SCK

SDO

SDI

AD7946

CNV

SCK

SDO

SDI

AD7946

Figure 39. Chain Mode with BUSY Indicator Connection Diagram

04656-P

r
C-018

SDO

= SDI

13 D

12 D

SCK

CONVERSION

ACQUISITION

CONV

CYC

ACQ

ACQUISITION

CNV = SDI

SCK

SCKH

SCKL

SDO

= SDI

13 D

12 D

0 D

13 D

SSDISCK

HSDISC

HSDO

DSDO

SDO

13 D

12 D

0 D

13 D

DSDOSDI

SSCKCNV

HSCKCNV

Figure 40. Chain Mode with BUSY Indicator Serial Interface Timing

AD7946

Preliminary Technical Data

Rev Pr D | Page 24 of 27

APPLICATION HINTS

LAYOUT

The printed circuit board that houses the AD7946 should be
designed so that the analog and digital sections are separated
and confined to certain areas of the board. The pinout of the
AD7946 with all its analog signals on the left side and all its
digital signals on the right side eases this task.

Avoid running digital lines under the device because these
couple noise onto the die, unless a ground plane under the
AD7946 is used as a shield. Fast switching signals, such as CNV
or clocks, should never run near analog signal paths. Crossover
of digital and analog signals should be avoided

At least one ground plane should be used. It could be common
or split between the digital and analog section. In such a case, it
should be joined underneath the AD7946s.

The AD7946 voltage reference input REF has a dynamic input
impedance and should be decoupled with minimal parasitic
inductances. That is done by placing the reference decoupling
ceramic capacitor close to, and ideally right up against, the REF
and GND pins and connect these pins with wide, low
impedance traces.

Finally, the power supply VDD and VIO of the AD7946 should
be decoupled with ceramic capacitors, typically 100 nF, placed
close to the AD7946 and connected using short and large traces
to provide low impedance paths and reduce the effect of glitches
on the power supply lines.

An example of layout following these rules is shown in Figure
41 and Figure 42.

EVALUATING THE AD7946'S PERFORMANCE

Other recommended layouts for the AD7946 are outlined in the
evaluation board for the AD7946 (

EVAL-AD7946

). The

evaluation board package includes a fully assembled and tested
evaluation board, documentation, and software for controlling
the board from a PC via the

EVAL-CONTROL BRD2

Figure 41. Example of Layout of the AD7946 (Top Layer)

Figure 42. Example of Layout of the AD7946 (Bottom Layer)

Preliminary Technical Data

AD7946

Rev Pr D | Page 25 of 27

OUTLINE DIMENSIONS

0.23
0.08

0.80
0.60
0.40

8°
0°

0.15
0.00

0.27
0.17

0.95
0.85
0.75

SEATING

PLANE

1.10 MAX

0.50 BSC

3.00 BSC

4.90 BSC

PIN 1

COPLANARITY

0.10

COMPLIANT TO JEDEC STANDARDS MO-187BA

Figure 43.10-Lead Micro Small Outline Package [MSOP]

(RM-10)

Dimensions shown in millimeters

3.00

BSC SQ

INDEX

AREA

TOP VIEW

1.50

BCS SQ

EXPOSED PAD

(BOTTOM VIEW)

1.74
1.64
1.49

2.48
2.38
2.23

0.50 BSC

0.50
0.40
0.30

0.80
0.75
0.70

0.05 MAX
0.02 NOM

SEATING

PLANE

0.30
0.23
0.18

0.20 REF

0.80 MAX
0.55 TYP

PIN 1

INDICATOR

PADDLE CONNECTED TO GND.

THIS CONNECTION IS NOT

REQUIRED TO MEET THE

ELECTRICAL PERFORMANCES

Figure 44. 10-Lead Lead Frame Chip Scale Package [ QFN (LFCSP)]

3 mm × 3 mm Body

(CP-10)

Dimensions shown in millimeters

AD7946

Preliminary Technical Data

Rev Pr D | Page 26 of 27

ORDERING GUIDE

Models

Temperature Range

Package (Option)

Transport Media, Quantity

Brand

AD7946BRM

40°C to +85°C

MSOP (RM-10)

Tube, 50

C1E

AD7946BRMRL7

40°C to +85°C

MSOP (RM-10)

Reel, 1,000

C1E

AD7946BCPWP

40°C to +85°C

QFN [LFCSP] (CP-10)

Waffle pack, 50

C1E

AD7946BCPRL7

40°C to +85°C

QFN [LFCSP] (CP-10)

Reel, 1,500

C1E

EVAL-AD7946CB

Evaluation Board

EVAL-CONTROL BRD2

Controller Board

EVAL-CONTROL BRD3

Controller Board

This board can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRDx for evaluation/demonstration purposes.

These boards allow a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators.

Part Number AD7946