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Part Number AT89C5132

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Rev. 4173C­USB­07/04
Features
·
Programmable Audio Output for Interfacing with Common Audio DAC
­ PCM Format Compatible
­ I
2
S Format Compatible
·
8-bit MCU C51 Core-based (F
MAX
= 20 MHz)
·
2304 Bytes of Internal RAM
·
64K Bytes of Code Memory
­ AT89C5132: Flash (100K Write/Erase Cycles)
·
4K Bytes of Boot Flash Memory (AT89C5132)
­ ISP: Download from USB or UART to any External Memory Cards
·
USB Rev 1.1 Device Controller
­ "Full Speed" Data Transmission
·
Built-in PLL
·
MultiMedia Card
®
Interface Compatibility
·
Atmel DataFlash
®
SPI Interface Compatibility
·
IDE/ATAPI Interface
·
2 Channels 10-bit ADC, 8 kHz (8 True Bits)
­ Battery Voltage Monitoring
­ Voice Recording Controlled by Software
·
Up to 44 Bits of General-purpose I/Os
­ 4-bit Interrupt Keyboard Port for a 4 x n Matrix
­ SmartMedia
®
Software Interface
·
Two Standard 16-bit Timers/Counters
·
Hardware Watchdog Timer
·
Standard Full Duplex UART with Baud Rate Generator
·
Two Wire Master and Slave Modes Controller
·
SPI Master and Slave Modes Controller
·
Power Management
­ Power-on Reset
­ Software Programmable MCU Clock
­ Idle Mode, Power-down Mode
·
Operating Conditions
­ 3V,
±
10%, 25 mA Typical Operating at 25°C
­ Temperature Range: -40
°
C to +85
°
C
·
Packages
­ TQFP80, PLCC84 (Development Board Only)
­ Dice
Description
The AT89C5132 is a mass storage device controlling data exchange between various
Flash modules, HDD and CD-ROM.
The AT89C5132 includes 64K Bytes of Flash memory and allows In-System Program-
ming through an embedded 4K Bytes of Boot Flash Memory.
The AT89C5132 include 2304 Bytes of RAM memory.
The AT89C5132 provides all the necessary features for man-machine interface
including, timers, keyboard port, serial or parallel interface (USB, SPI, IDE), ADC
input, I
2
S output, and all external memory interface (NAND or NOR Flash, SmartMe-
dia, MultiMedia, DataFlash cards).
Typical Applications
·
Flash Recorder/Writer
·
PDA, Camera, Mobile Phone
·
PC Add-on
USB
Microcontroller
with 64K Bytes
Flash Memory
AT89C5132
Preliminary
4
AT89C5132
4173C­USB­07/04
Block Diagram
Figure 1. AT89C5132 Block Diagram
Notes:
1. Alternate function of Port 3
2. Alternate function of Port 4
3. Alternate function of Port 1
8-BIT INTERNAL BUS
Clock and PLL
Unit
C51 (X2 CORE)
RAM
2304 Bytes
Flash
Interrupt
Handler Unit
FILT
X2
X1
MMC
Interface
I/O
MDAT
P0 - P5
10-bit A-to-D
Converter
V
SS
V
DD
Keyboard
Interface
KIN3:0
I
2
S/PCM
Audio Interface
AVSS
AV
DD
AIN1:0
Ports
INT0
INT1
MOSI
MISO
Timers 0/1
T1
T0
SPI/DataFlash
Controller
MCLK
MCMD
SCK
RST
AREF
DSEL
DCLK
SCLK
DOUT
64K Bytes
USB
Controller
D+
D-
UART
RXD
TXD
IDE
Interface
SS
Watchdog
Flash Boot
4K Bytes
UVSS
UV
DD
and
BRG
1
1
1
1
1
1
2
2
2
2
3
TWI
Controller
SCL SDA
1
1
5
AT89C5132
4173C­USB­07/04
Pin Description
Figure 2. AT89C5132 80-pin TQFP Package
P0
.
3
/A
D
3
P0
.
4
/A
D
4
P0
.
5
/A
D
5
VS
S
VD
D
P0
.
6
/A
D
6
P0
.
7
/A
D
7
P2
.
0
/A
8
P2
.
1
/A
9
P3.
1
/
T
XD
P
3
.2/IN
T
0
P
3
.3/IN
T
1
P
3
.4/T
0
P
3
.0
/RX
D
1
2
3
4
5
6
7
8
13
11
10
P2.2/A10
P2.3/A11
P2.4/A12
P2.6/A14
P2.5/A13
P2.7/A15
MCLK
MDAT
MCMD
P0
.
2
/A
D
2
P0
.
1
/A
D
1
P0
.
0
/A
D
0
PVSS
VSS
X2
X1
TST
VS
S
9
12
14
15
16
P4
.
3
/S
S
P4
.
2
/S
C
K
P4
.
1
/M
OSI
P4
.
0
/M
IS
O
VSS
VDD
RST
SCLK
DSEL
DCLK
DOUT
AI
N
1
AI
N
0
AR
E
F
N
AR
E
F
P
AV
S
S
AV
D
D
P3
.
7
/R
D
P3
.6
/
W
R
P
3
.5/T
1
VD
D
P1.0/KIN0
P1.1/KIN1
P1.2/KIN2
P1.3/KIN3
P1.4
P1.5
P1.7/SDA
FILT
PVDD
VDD
P1.6/SCL
17
18
19
20
21
22
23
24
25
26
27
28
33
31
30
29
32
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
53
51
50
49
52
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
73
71
70
69
72
74
75
76
77
78
79
80
ALE
ISP
UVDD
UVSS
P5
.
0
P5
.
1
P4
.
7
P4
.
6
D-
D+
P5
.3
P5
.2
VSS
VDD
P4.5
P4.4
TQFP80
6
AT89C5132
4173C­USB­07/04
Figure 3. AT89C5132 84-pin PLCC
(1)
Note:
1. For development board only.
PLCC84
P0
.
3
/A
D
3
P0
.
4
/A
D
4
P0
.
5
/A
D
5
VS
S
VD
D
P0
.
6
/A
D
6
P0
.
7
/A
D
7
P2
.
0
/A
8
P2
.
1
/A
9
P
3
.3/IN
T
1
P
3
.4/T
0
P
3
.5/T
1
P
3
.6/W
R
P
3
.2/IN
T
0
65
64
63
62
61
60
59
58
55
56
57
12
13
14
15
16
17
22
20
19
33
34
35
36
37
4
3
2
1
84
83
82
81
80
79
78
NC
P2.3/A11
P2.4/A12
P2.6/A14
P2.5/A13
P2.7/A15
MCLK
MDAT
MCMD
P0
.
2
/A
D
2
P0
.
1
/A
D
1
P5
.
0
PAVSS
VSS
X2
NC
X1
P3
.
1
/TX
D
18
21
23
24
25
38
39
40
41
42
69
68
67
66
70
5
6
7
8
9
P4
.
3
/S
S
P4
.
2
/S
C
K
P
4
.1
/
M
OS
I
P
4
.0
/
M
ISO
VSS
VDD
RST
SCLK
DSEL
DCLK
DOUT
AI
N
1
AI
N
0
AR
E
F
N
AR
EF
P
AV
S
S
AV
D
D
VS
S
VD
D
P
3
.7
/RD
P3.
0
/R
XD
P1.0/KIN0
P1.1/KIN1
P1.2/KIN2
P1.3/KIN3
P1.4
P1.5
P1.7/SDA
FILT
PAVDD
VDD
P1.6/SCL
26
43
TST
P5
.2
P0
.
0
/A
D
0
77
P2.2/A10
54
ALE
ISP
NC
P5
.
1
P4
.
7
P4
.
6
76
75
10
11
28
27
29
30
31
32
UVDD
UVSS
44
45
46
47
48
49
50
51
52
53
74
73
72
71
P4.4
P4.5
VDD
VSS
D-
D+
NC
P5
.3
7
AT89C5132
4173C­USB­07/04
Signals
All the AT89C5132 signals are detailed by functionality in Table 1 to Table 15.
Table 1. Ports Signal Description
Table 2. Clock Signal Description
Signal
Name
Type
Description
Alternate
Function
P0.7:0
I/O
Port 0
P0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1s
written to them float and can be used as high impedance inputs. To
avoid any parasitic current consumption, floating P0 inputs must be
polarized to V
DD
or V
SS
.
AD7:0
P1.7:0
I/O
Port 1
P1 is an 8-bit bidirectional I/O port with internal pull-ups.
KIN3:0
SCL
SDA
P2.7:0
I/O
Port 2
P2 is an 8-bit bidirectional I/O port with internal pull-ups.
A15:8
P3.7:0
I/O
Port 3
P3 is an 8-bit bidirectional I/O port with internal pull-ups.
RXD
TXD
INT0
INT1
T0
T1
WR
RD
P4.7:0
I/O
Port 4
P4 is an 8-bit bidirectional I/O port with internal pull-ups.
MISO
MOSI
SCK
SS
P5.3:0
I/O
Port 5
P5 is a 4-bit bidirectional I/O port with internal pull-ups.
-
Signal
Name
Type
Description
Alternate
Function
X1
I
Input to the on-chip inverting oscillator amplifier
To use the internal oscillator, a crystal/resonator circuit is connected to
this pin. If an external oscillator is used, its output is connected to this
pin. X1 is the clock source for internal timing.
-
X2
O
Output of the on-chip inverting oscillator amplifier
To use the internal oscillator, a crystal/resonator circuit is connected to
this pin. If an external oscillator is used, leave X2 unconnected.
-
FILT
I
PLL Low Pass Filter input
FILT receives the RC network of the PLL low pass filter.
-